TW342501B - Data input circuit including echo clock generator - Google Patents

Data input circuit including echo clock generator

Info

Publication number
TW342501B
TW342501B TW086112832A TW86112832A TW342501B TW 342501 B TW342501 B TW 342501B TW 086112832 A TW086112832 A TW 086112832A TW 86112832 A TW86112832 A TW 86112832A TW 342501 B TW342501 B TW 342501B
Authority
TW
Taiwan
Prior art keywords
data
input circuit
clock generator
echo clock
data input
Prior art date
Application number
TW086112832A
Other languages
Chinese (zh)
Inventor
Lee Sang-Bo
Jung-Bae Lee
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Application granted granted Critical
Publication of TW342501B publication Critical patent/TW342501B/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1093—Input synchronization
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1084—Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/225—Clock input buffers

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)

Abstract

A data input circuit for a semiconductor memory device for synchronously inputting data with an echo clock signal generated by a data clock signal inputted synchronous with the data, the data input circuit comprising: an echo clock generator for generating a predetermined amount of pulses by calculating the number of pulses of an externally inputted data; and an input data transmission unit for responding to an output signal of the echo clock generator and transmitting input data.
TW086112832A 1997-01-30 1997-09-05 Data input circuit including echo clock generator TW342501B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019970002885A KR100224687B1 (en) 1997-01-30 1997-01-30 Semiconductor memory device having retroclock receiver

Publications (1)

Publication Number Publication Date
TW342501B true TW342501B (en) 1998-10-11

Family

ID=19496031

Family Applications (1)

Application Number Title Priority Date Filing Date
TW086112832A TW342501B (en) 1997-01-30 1997-09-05 Data input circuit including echo clock generator

Country Status (3)

Country Link
JP (1) JP4198770B2 (en)
KR (1) KR100224687B1 (en)
TW (1) TW342501B (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013131277A (en) 2011-12-22 2013-07-04 Elpida Memory Inc Semiconductor device and manufacturing method for the same
KR20160045270A (en) 2014-10-17 2016-04-27 박종민 Fishing hook assembly for catching squids

Also Published As

Publication number Publication date
KR100224687B1 (en) 1999-10-15
JPH10214483A (en) 1998-08-11
JP4198770B2 (en) 2008-12-17
KR19980067040A (en) 1998-10-15

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Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees