JPH10214483A - Data input circuit and method for semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten the cycle time of a clock by counting the number of pulses of a data clock signal to be inputted at the same timing as the input data and transmitting the input data to a semiconductor memory device synchronized with an echo clock signal generated until arriving at a specified number. SOLUTION: A data input buffer 301 buffers the input data DIN. Further, an echo clock generator 303 generates a pulse of an output signal XCON whenever an external data clock DCLK is transited to generate the pulse until the number of the external data clock DCLK arrives at a prescribed number decided by an external system. Further, an input data transmission part 305 outputs the output signal DI of the data input buffer 301 as DIX in response to the pulse of the output signal XCON of the echo clock generator 303 to transmit it.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data input circuit and a data input method for a semiconductor memory device, and more particularly to a data input circuit and a data input method for a synchronous semiconductor memory device having an echo clock generator to shorten a clock cycle period. Regarding the input method.

2. Description of the Related Art Generally, a computer system includes a central processing unit (CP) for executing instructions for a given task.
U) and a main memory for storing data and programs requested by the CPU. Therefore, in order to improve the performance of the computer system, it is required that the operation speed of the CPU be improved and that the CPU operate without waiting time to shorten the access time to the main memory as much as possible. In response to such a request, a synchronous DRAM (SDRAM) that operates under the control of a system clock and has a significantly reduced access time to a main memory has appeared.

Generally, the operation of an SDRAM is controlled in response to a pulse signal generated by a transition of a system clock. However, in a synchronous semiconductor memory device that operates in synchronization with a clock, a clock cycle time (tCC) is limited by various factors.

[0003] That is, the limit of tCC (CLOCK CYCLE TIME) is the difference between the required time of the clock input to the memory and the data control unit (hereinafter referred to as tSW), the required time from clock synchronization to data output (hereinafter referred to as tAC). ), The time during which data is transmitted from the memory to the control unit (hereinafter, referred to as tFL), the data setup time at the control unit (hereinafter, tS).
S).

FIG. 1 is a block diagram showing a data input / output circuit according to the prior art. It can be seen that externally input data is simply input to a memory device via an input buffer 10.

[0005] FIG. 2 is a diagram showing various required times that cause the limit of tCC in the conventional technology. here,
CLK_SYS represents the waveform of the system clock and CLK_C
NTR represents the waveform of the clock input to the control unit as CLK
_DRAM shows the waveform of the clock input to the DRAM,
DATA_DRAM indicates data output from the DRAM, and DATA_CNTR indicates data generated from the control unit.

[0006]

The above-mentioned conventional SDRAM
In FIG. 2, referring to FIG.
Has a limit that it must be greater than the sum of tSW, tAC, tFL and tSS.
Therefore, in a conventional data input / output circuit, for example, 300 MHz
It has not been possible to realize an SDRAM having a frequency higher than z. The present invention has been devised to achieve the above object, and has as its object to provide a data input circuit and a data input method of a semiconductor memory device capable of reducing a clock cycle time.

In order to achieve the above object, a data input circuit of a semiconductor memory device according to the present invention generates a data input circuit in a semiconductor memory device based on a data clock signal input at the same timing as input data. The input data is input to the semiconductor memory device in synchronization with a reverberation clock signal. For example, a reverberation clock generator that counts the number of pulses of the data clock signal and generates pulses up to a specified number, and the input data is synchronized with a pulse generated by the reverberation clock generator. Input data transmission means for transmitting the data to the semiconductor memory device.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment according to the present invention will be described below in detail with reference to the accompanying drawings. In the drawings, the same reference numerals represent the same components.

FIG. 3 is a block diagram showing a data input circuit having the reverberation clock generator of this embodiment. As shown in the figure, the data input / output circuit of the semiconductor memory device of this embodiment includes a data input buffer 301, an echo clock generator 303, and an input data transmission unit 305.

The data input buffer 301 buffers input data DIN input from the outside. Also,
The reverberation clock generator 303 has an external data clock DCL.
A pulse is generated in response to the transition of the external data clock DCLK until the number of K reaches the specified number. The input data transmission unit 305 transmits the output signal DI of the data input buffer 301 in response to the pulse of the output signal XCON of the reverberation clock generator 303.

FIG. 4 shows the input data transmission unit 30 shown in FIG.
FIG. 5 is a diagram showing a detailed configuration of the fifth embodiment. According to the figure, the input data transmission unit 305 includes a first inversion buffer 401, a transmission gate 403, a second inversion buffer 405, and the like. The first inversion buffer 401 is the data input buffer 30
1 is buffered and inverted. An echo clock generator 3 is connected to one end of the transmission gate 403.
03 is input, and the XCON inverted through the third inversion buffer 407 is input to the other end.
An output signal (N402) of the first inversion buffer 401 is transmitted in response to the input pulse. Further, the second inversion buffer 405 buffers and inverts the output signal (N402) of the first inversion buffer 401 transmitted by the transmission gate 403.

Therefore, every time a transition of the external data clock DCLK occurs, the output signal XCON of the reverberation clock generator 303 generates a pulse. Accordingly, the transmission gate 403 of the input data transmission unit 305 is turned on, and transmits the output signal DI of the data input buffer 301 to the inside of the memory chip. The reverberation clock generator 303 is connected to an external data clock DC.
When the number of LK reaches a predetermined number determined by the external system, the generation of the pulse is stopped. Therefore, the input data DI
As for N, only a predetermined number determined by the external system is input into the chip.

FIG. 5 is a diagram showing a detailed configuration of the reverberation clock generator 303 in the data input circuit of the present embodiment. According to the figure, the echo clock generator 303 includes an echo clock buffer 501, an echo pulse generator 503, a bust length counter 505, a latch 507, and a reset pulse generator 509.

The reverberation clock buffer 501 buffers the external data clock signal DCLK and outputs XPUL. Then, the echo pulse generator 503 is enabled by a predetermined pulse enable signal PULEN,
In response to the transition of the output signal XPUL of the reverberation clock buffer 501, it generates its own output signal XCON pulse.
The bust length counter 505 is pre-charged by a predetermined reset pulse RESET, and the echo pulse generator 503
When the number of pulses of the output signal XCON generated from the output signal XCON matches the designated number, its own output signal BLCNT is transited.

The latch unit 507 is provided with a reset pulse RE
Pre-charged by SET, echo clock buffer 501
The pulse enable signal PULEN is latched by the first transition of the output signal XPUL of the BUSL and is unlatched by the transition of the output signal BLCNT of the bust length counter 505.
Occurs. Hereinafter, the configuration of the latch unit 507 will be described more specifically. The latch unit 507 includes a first logical sum inversion unit 511
And a second logical sum inverting unit 513. The first OR gate 511 includes a signal XPU responsive to the DCLK.
L and the output VPRE of the second OR gate 513 are input signals. The second OR gate 513 uses the output signal BLCNT of the bust length counter 505 and the output signal (N512) of the first OR gate 513 as input signals. Less than,
The operation of the latch unit 507 will be described. At the initial stage of the operation of the latch unit 507, the output signal BLCNT of the bust length counter 505 is in a "low" state. Then, when the output signal XPUL of the reverberation clock buffer 501 changes to “high”, the output (N512) of the first OR gate 511 becomes “low”, and the output signal of the second OR gate 513 changes. VPRE is latched in the "high" state. Therefore, even if the output signal XPUL of the reverberation clock buffer 501 subsequently transitions, the output signal PUL of the latch
The logic state of EN is not changed.

When the number of pulses designated by the echo pulse generation section 503, that is, pulses corresponding to the data bust length, are generated, the output signal BLC of the bust length counter 505 is output.
NT transitions to “high”. Then, when the output signal XPUL of the reverberation clock buffer 501 becomes “low”,
The output signal PULEN of the latch unit 507 becomes “low”, and the output signal XCON of the echo pulse generation unit 503 does not generate any pulse. Then, the reset pulse generator 5
09 generates a reset pulse RESET in response to the transition of the pulse enable signal PULEN. Here, the latch unit 507 of the present embodiment includes a latch release unit 515. The latch release unit 515 is powered up (POWER-
When an (UP) or reset (RESET) pulse occurs,
The latch of the output signal VPRE of the second OR gate 513 is released.

FIG. 6 is a diagram showing a detailed configuration example of the echo clock buffer 501 shown in FIG. According to FIG.
The reverberation clock buffer 501 of this embodiment includes a lower current mirror 601, an upper current mirror 603, and a latch unit 60.
5 is comprised. The lower current mirror 601 uses the data clock DCLK based on a predetermined lower reference voltage VRL.
Buffer voltage. Also, the upper current mirror 6
03 buffers the data clock DCLK voltage with reference to a predetermined upper reference voltage VRH higher than the lower reference voltage VRL. In addition, the latch unit 605 uses the output signal (N602) of the lower current mirror 601 as a first input signal and the output signal (N604) of the upper current mirror 603 as a second input signal.
Input signal. Note that XPUL which is an output signal of the reverberation clock buffer 501 is connected to the data clock signal DCLK
Transitions when the level of the data clock signal DCLK falls below the lower reference voltage VRL, and when the level of the data clock signal DCLK rises above the upper reference voltage VRH.

The lower current mirror 601 includes a pull-up transistor 607, a first PMOS transistor 609, a second PMOS transistor 611, a first NMOS transistor 613, and a second NMOS transistor 615. The source of the pull-up transistor 607 is connected to the power supply voltage VCC, and when a predetermined echo clock enable signal XEN is active, it is input as a low signal via the inverter 628 and turned on. The source of the first PMOS transistor 609 is connected to the drain of the pull-up transistor 607, and the lower reference voltage VRL is applied to its gate. The source of the second PMOS transistor 611 is connected to the drain of the pull-up transistor 607, and the data clock signal DCLK is applied to its gate. The first NMOS transistor 613 has a common connection point (N610) whose source is connected to the ground voltage VSS and whose gate and drain are commonly connected to the drain of the first PMOS transistor 609. Also, the second NMO
The S transistor 615 has its source connected to the ground voltage VSS, its gate connected to the common connection point (N610), its drain connected to the drain of the second PMOS transistor 611, and the output signal of the lower current mirror.
(N602) is generated.

Accordingly, when the XEN is enabled to a "high", the lower current mirror 601 responds to the data clock signal DCLK. When the level of the data clock signal DCLK is higher than the lower reference voltage VRL, the first P
Voltage V between gate and source of MOS transistor 609
gs becomes larger than Vgs of the second PMOS transistor 611. Therefore, the voltage of the terminal N610 increases, and the influence of the second NMOS transistor 615 becomes larger than the influence of the second PMOS transistor 611. Therefore, the voltage of the output terminal N602 of the lower current mirror 601 is VSS
To descend to the side.

On the other hand, when the level of the data clock signal DCLK is lower than the lower reference voltage VRL, the first PMO
Vgs of the S transistor 609 becomes smaller than Vgs of the second PMOS transistor 611. Accordingly, the voltage at the common connection point (N610) decreases, and the effect of the second NMOS transistor 615 becomes smaller than the effect of the second PMOS transistor 611. Therefore, the voltage of the output terminal N602 of the lower current mirror 601 rises toward VCC.

The lower current mirror 601 has its source connected to the ground voltage VSS, its drain connected to the output (N602) of the lower current mirror 601, and is "turned on" when the echo clock enable signal XEN is disabled. And a third NMOS transistor 617. Accordingly, when XEN is disabled to “low”, the third NMOS transistor 617 is “turned on” and the output terminal of the lower current mirror 601 (N60).
Level 2) is set to VSS. Also, when XEN is enabled to “high”, the third NMOS transistor 617 is “turned off” and the lower current mirror 60 is turned off.
The setting of the output terminal (N602) of No. 1 is released.

The upper current mirror 603 includes a pull-down transistor 619, a fourth NMOS transistor 621, a fifth NMOS transistor 623, a third PMOS transistor 625, and a fourth PMOS transistor 627. The pull-down transistor 619 has its source connected to the ground voltage VSS, and is turned on when a predetermined echo clock enable signal XEN is activated. The source of the fourth NMOS transistor 621 is connected to the drain of the pull-down transistor 619, and the upper reference voltage VRH is applied to its gate. The fifth NMOS transistor 623 has a source connected to the drain of the pull-down transistor 619 and a gate to which the data clock signal DCLK is applied. The third PMOS transistor 625 has a common connection point (N622) whose source is connected to the power supply voltage VCC and whose gate and drain are commonly connected to the drain of the fourth NMOS transistor 621. Also,
The fourth PMOS transistor 627 has its source connected to the power supply voltage VCC and its gate connected to the common connection point (N62).
2), and its drain is commonly connected to the drain of the fifth NMOS transistor 623 to generate the output signal (N604) of the upper current mirror 603.

Therefore, when XEN is enabled to “high”, the upper current mirror 603 outputs the data clock signal D
Respond to CLK. If the level of the data clock signal DCLK is lower than the upper reference voltage VRH, the fifth NMO
Vgs of the S transistor 621 becomes larger than Vgs of the fifth NMOS transistor 623. Accordingly, the voltage at the common connection point (N622) decreases, and the effect of the third PMOS transistor 627 becomes greater than the effect of the fifth NMOS transistor 623. Therefore, the voltage of the output terminal N604 of the upper current mirror 603 rises toward VCC. On the other hand, when the level of the data clock signal DCLK is higher than the upper reference voltage VRH, Vgs of the fourth NMOS transistor 621 becomes
23 Vgs. Therefore, the common connection point (N
622), the effect of the third PMOS transistor 627 becomes smaller than the effect of the fifth NMOS transistor 623. Therefore, the voltage of the output terminal N604 of the upper current mirror 603 falls toward VSS.

The upper current mirror 603 is "turned on" when its source is connected to the power supply voltage VCC, its drain is connected to the output (N604) of the upper current mirror 603, and the echo clock enable signal XEN is disabled. And a fifth PMOS transistor 629. Accordingly, when XEN is disabled to “low”, the fifth PMOS transistor 629 is “turned on” and the output terminal (N60) of the upper current mirror 603 is turned on.
The level of 4) is set to VCC. Also, when XEN is enabled to “high”, the fifth PMOS transistor 629 is “turned off” and the upper current mirror 60 is turned off.
The setting of the output terminal No. 3 (N604) is released.

The latch unit 605 includes an inverting unit 631, a first logical product inverting unit 633, a second logical product inverting unit 635, and an inverting buffer 637. The inverting unit 631 inverts the level of the output signal (N602) of the lower current mirror 601. Then, the first logical product inverting unit 633 uses the output signal (N632) of the inverting unit 631 as a first input signal. Also, the second
The logical product inverting unit 635 outputs the output signal of the upper current mirror 603.
(N604) and the output signal (N6
34) and inverts the output signal (N63).
6) is the second input signal of the first AND gate 633. The inversion buffer 637 stores the first logical product inversion unit 6
The output signal XPUL of the reverberation clock buffer 501 is generated by inverting and buffering the output signal (N634) of 33.

With the above configuration, the data clock signal D
When the level of CLK becomes lower than the lower reference voltage VRL, the level of the output signal (N602) of the lower current mirror 601 increases. In addition, the output signal (N6
The level of (32) becomes "low", and the level of the output signal XPUL of the echo clock buffer 501 falls to "low". At this time, the level of the output signal (N604) of the upper current mirror 603 becomes “high”, and the logic state of the output signal (N636) of the second AND circuit 635 becomes “low”.

The level of the data clock signal DCLK is changed from "lower reference voltage VRL or less" to "VRL and VRH".
In this case, the level of the output signal (N602) of the lower current mirror 601 decreases. Therefore, the level of the output signal (N632) of the inverting unit 631 becomes "high". Since the logical state of the output signal (N636) of the second logical product inverting unit 635 keeps "low",
The level of the output signal XPUL of the echo clock buffer 501 does not change. Also, the data clock signal DCL
When the level of K becomes higher than the upper reference voltage VRH, the level of the output signal (N602) of the lower current mirror 601 decreases. Then, the level of the output signal (N632) of the inverting unit 631 becomes “high”. At this time, the level of the output signal (N604) of the upper current mirror 603 becomes “low”, and the output signal of the second logical product inversion unit 635
The logic state of (N636) becomes "high". Therefore, the level of the output signal XPUL of the reverberation clock buffer 501 rises to “high”.

The level of the data clock signal DCLK is changed from "above the upper reference voltage VRH" to "VRL and VRL".
When the voltage falls between "RH", the upper current mirror 60
3, the level of the output signal (N604) rises. However, the output signal (N
Since the logical state of the output signal (N636) of the second logical product inverting section 635 keeps the "high" state. Therefore, the level of the output signal XPUL of the reverberation clock buffer 501 does not change.

Next, FIG. 7 shows a detailed configuration of the echo pulse generator 503 shown in FIG. According to the figure, the echo pulse generator 503 includes an inversion delay unit 701 and a first AND unit 70.
3, a logical sum inverting unit 705, a logical sum unit 707, and a second logical product unit 709. The inversion delay unit 701 inverts and delays the output signal XPUL of the echo clock buffer 501. The first AND unit 703 outputs the output signal XPUL of the echo clock buffer 501 and the inverted delay unit 7.
The logical product of the output signal (N702) of No. 01 is obtained. The logical sum inverting unit 705 outputs the output signal XPUL of the echo clock buffer 501 and the output signal (N702) of the inverting delay unit 701.
And invert the result. And the OR unit 70
Numeral 7 inverts the output signal (N704) of the first logical product unit 703 and the output signal (N706) of the logical sum inverting unit 705 by taking a logical sum. The second AND unit 709 is enabled by the pulse enable signal PULEN, and the
7 in response to the output signal (N708). FIG. 8 is a timing chart at main terminals of the echo pulse generator 503 in FIG. 7 according to the transition of the signal XPUL. Referring to FIG.
When the logic state of the signal XPUL changes from “high to low” or “low to high”,
The output signal (N708) of the OR unit 707 is generated as a pulse. Therefore, when the logic state of the pulse enable signal PULEN is “high”, the echo pulse generator 5
03 is the output signal of the OR unit 707
The pulse is also generated in response to the transition of (N708). However, when the logic state of the pulse enable signal PULEN is “low”, the echo pulse generator 50
3 does not generate a pulse. FIG. 9 is a diagram showing a detailed configuration of the reset pulse generator 509 of FIG. The reset pulse generator 509 generates a reset pulse when a clock signal of a designated number, that is, a data bus length is input. Referring to FIG. 9, the reset pulse generating unit 509 includes an inversion delay unit 901, a logical sum inverting unit 903, and a logical sum unit 905. The inversion delay unit 901 inverts and delays the pulse enable signal PULEN. The logical sum inverting unit 903 outputs the pulse enable signal PULEN and the output signal (N90) of the inverting delay unit 901.
Let 2) be an input signal. Therefore, each time the logic state of the pulse enable signal PULEN changes from “high” to “low”, the output signal (N904) of the OR gate 903 generates a pulse from “low” to “high”. And
The OR unit 905 receives the power-up signal VCCHB, which generates a pulse at power-up, and the output signal (N904) of the OR unit 903 as input signals. Therefore, at power-up or when the logic state of PULEN changes from “high” to “low”.
, The reset signal RESET which is the output signal of the OR unit 905 is generated as a pulse. FIG.
6 is a diagram showing a detailed configuration of a bust length counter 505 in FIG. As shown in the figure, the bust length counter 505 includes a counting signal generator 1001 and a bust signal generator 1003. Counting signal generation section 1001 measures the number of pulses of output signal XCON generated from reverberation pulse generation section 503, and generates counting signal groups CNT0 to CNT8 as the output signals.
The bust signal generator 1003 receives the counting signal group and generates a signal BLCNT representing the bust length. FIG. 11 is a diagram illustrating a detailed configuration of the counting signal generator 1001 of FIG. Referring to FIG. 10, a counting signal generator 1001 includes an A-type counter 1101.
And B-type counters (1102, 1103, ...). FIG. 12 is a diagram showing a detailed configuration of the A-type counter 1101 in FIG. According to FIG.
101 is a logical sum inverting unit 1201, first and second inverting units 1
203, 1215, a first transmission gate 1205, a first latch unit 1207, a second transmission gate 1209, a second latch unit 1211 and an NMOS transistor 1213. The logical sum inverting unit 1201 outputs the reset pulse R
ESET and output signal XCON of echo pulse generating section 503
Invert the logical sum of Then, the first reversing unit 1203
Inverts the logical state of CNT0, which is the output signal of the A-type counter 1101. The first transmission gate 1205 outputs the output signal XCO of the echo pulse generator 503 in a state where the reset pulse RESET is disabled to “low”.
When N is disabled low, the first inverting unit 1
The output signal (N1204) of 203 is transmitted. Then, the first latch unit 1207 latches the signal transmitted by the first transmission gate 1205. Also, the second transmission gate 1
209 transmits the output signal (N1208) of the first latch unit 1207 when the reset pulse RESET is enabled to "high" or when XCON is enabled to "high". The second latch unit 1211 is connected to the second transmission gate 1
The signal transmitted by 207 is latched. And
The source of the NMOS transistor 1213 is connected to the ground voltage VSS, gated by the reset pulse RESET, and connected to the input terminal (N120) of the first latch unit 1207.
6) is precharged to VSS.

A-type counter 1101 having the above configuration
Will be described below. First, when the reset pulse RESET is activated to “high”, NMO
S-transistor 1213 is "turned on". Therefore, the input terminal (N1206) of the first latch unit 1207 is at V
SS is charged first. And the second transmission gate 1209
Is turned on, and the logic state of the output signal CNT0 of the A-type counter 1101 is "low". Also, the output signal (N1204) of the first inversion unit 1203 is "high", and the first transmission gate 1205 is "turned off".
Then, when the reset pulse RESET is disabled to “low”, the NMOS transistor 1213 is “turned off”. Also, the first transmission gate 1205
Is turned on, and the logic state of the output signal (N1208) of the first latch unit 1207 becomes "low". On this occasion,
The second transmission gate 1209 is "turned off".
When the output signal XCON of the echo pulse generator 503 is activated to “high”, the second transmission gate 120 is activated.
9 is turned on, and the logic state of the output signal CNT0 of the A-type counter 1101 is changed to "high". Also, when the output signal XCON of the echo pulse generator 503 is disabled to “low”, the first transmission gate 120 is disabled.
9 is turned on, and the logic state of the output signal (N1208) of the first latch unit 1207 changes. As described above, every time the output signal XCON of the reverberation pulse generator 503 forms a pulse, the output signal C of the A-type counter 1101 is output.
The logic state of NT0 repeats the transition. FIG.
12 is a diagram showing a detailed configuration of a B-type counter (1102, 1103,...) In FIG. Referring to FIG.
Are similar to the A-type counter 1101 shown in FIG. That is, the A-type counter 110
1 logical sum inverting section 1201 outputs reset pulse RESET
And the output signal XCON of the echo pulse generator 503 as an input signal, the OR inverting unit 1301 of the B-type counter (1102, 1103,...) Outputs the reset pulse RESET, the output signal XCON of the echo pulse generator 503, and A signal CARRYB representing the logic state of the output signal of the stage counter
i-1 is the input signal. Only when all the logic states of the output signals of the previous stage are "high", the signal C
The logic state of ARRYBi-1 becomes "low". Also, when the logic state of the signal CARRYBi-1 is "low",
The type counter operates similarly to the A type counter.

The operation of the counting signal generator 1001 shown in FIG. 11 will be described below with reference to the A-type counter shown in FIG. 12 and the B-type counter shown in FIG. First, when a reset operation is performed by a reset pulse RESET,
A type counter 1101 and B type counter (1102, 110
, CNT0 to CNT8, which are output signals of (3,...), Are all pre-charged to “0”. When the signal XCON generates the first pulse, the logic state of CNT0 becomes “1”. When the signal XCON generates the second pulse, the logic state of CNT0 becomes “0” and the logic state of CNT1 becomes “1”. When the signal XCON generates the third pulse, the logic state of CNT0 becomes "1" again. Then, when the signal XCON generates the fourth pulse, the logic states of CNT0 and CNT1 become “0”,
The logic state of CNT2 becomes "1". As described above, every time the signal XCON generates a pulse, the output signals CNT0 to CNT8 of the counting signal generator 1001 are sequentially converted, and the pulse of the signal XCON is measured. Further, when XCON generates a specified number of pulses, the reset signal RESET is activated, and the signals CNT0 to CNT8 are all pre-charged to "0". FIG. 14 shows the bust length counter 505 of FIG.
5 is a diagram showing a bust signal generation unit 1003 of FIG. The bust signal generation unit 1003 includes a counting signal group CNT
In response to 0 to CNT8, an output signal BLCNT to which a transition is made when the number of pulses of the output signal XCON generated from the echo pulse generator 503 matches the designated number of input pulses is generated. SZ2B shown in FIG. 14 is a signal that goes “high” when the bust length of the input data is 2 or more. SZ4B is a signal that goes “high” when the bust length of the input data is 4 or more, and SZ8B is a signal that goes “high” when the bust length of the input data is 8 or more. Also, SZFULL indicates that the bust length of the input data is F
This signal is “high” when it is ULL. Here, for example, assuming that the bust length of the input data is 4, in this case, SZ2B and SZ4B are “high”, and SZ8B and SZFULL are “low”. At this time, the output signal XC generated from the echo pulse generator 503 is output.
When the fourth pulse of ON is generated, CNT2 becomes “high” and the remaining counting signal groups CNT0, CN
T1, CNT3 to CNT8 become "low". On this occasion,
The logic state of the output signal BLCNT changes from “low” to “high”.
Will be transitioned to.

As described above, in the data input circuit including the reverberation clock generator according to the present embodiment,
At the time of data input, a pulse is generated in response to the number specified by the reverberation clock generator 303, that is, the data bust length. Then, the external data DIN input through the data input buffer 301 is transmitted to the inside of the semiconductor memory chip using the pulse of the reverberation clock generator 303.

Therefore, when data is input, the time required from clock synchronization to data output (data access time)
The data access operation speed of the synchronous semiconductor memory device can be improved by eliminating the influence of tAC and the time tFL during which data is transmitted from the memory to the control unit.

It should be noted that the present invention is not limited to the present embodiment, and it is obvious that many modifications can be made by those having ordinary knowledge in the art within the technical idea to which the present invention belongs.

As described above, according to the data input circuit provided with the reverberation clock generator according to the present invention, the time tAC and the data required from the clock synchronization to the output of the data with respect to the clock cycle time tCC are stored in the memory. Since the influence of the time tFL required for the transmission from the semiconductor memory device to the control unit can be eliminated, the cycle time tCC of the clock of the semiconductor memory device can be shortened, and the data access operation speed can be improved.

[0033]

[Brief description of the drawings]

FIG. 1 is a block diagram showing a conventional data input / output circuit configuration.

FIG. 2 is a timing chart for determining a conventional clock cycle time.

FIG. 3 is a block diagram illustrating a configuration of a data input circuit having an echo clock generator according to an embodiment of the present invention.

FIG. 4 is a block diagram illustrating a detailed configuration of an input data transmission unit according to the embodiment;

FIG. 5 is a block diagram illustrating a detailed configuration of a reverberation clock generator according to the present embodiment.

FIG. 6 is a block diagram illustrating a detailed configuration of a reverberation clock buffer according to the embodiment.

FIG. 7 is a block diagram illustrating a detailed configuration of a reverberation pulse generation unit according to the embodiment.

FIG. 8 is a timing chart of main terminals of a reverberation pulse generator according to the embodiment.

FIG. 9 is a block diagram illustrating a detailed configuration of a reset pulse generation unit according to the embodiment.

FIG. 10 is a block diagram illustrating a detailed configuration of a bust length counter according to the embodiment.

FIG. 11 is a block diagram illustrating a detailed configuration of a counting signal generator according to the embodiment.

FIG. 12 is a block diagram illustrating a detailed configuration of an A-type counter according to the present embodiment.

FIG. 13 is a block diagram illustrating a detailed configuration of a B-type counter according to the present embodiment.

FIG. 14 is a block diagram illustrating a detailed configuration of a bust signal generation unit according to the present embodiment.

[Explanation of symbols]

 301 data input buffer 303 echo clock generator 305 data transmission section 501 echo clock buffer 503 echo pulse generator 505 bust length counter 509 reset pulse generator

Claims (15)

[Claims] 1. In a semiconductor memory device, the input data is input to the semiconductor memory device in synchronization with an echo clock signal generated based on a data clock signal input at the same timing as input data. Data input circuit. 2. A reverberation clock generator that counts the number of pulses of the data clock signal and generates pulses until the number reaches a specified number, and the input is synchronized with a pulse generated by the reverberation clock generator. 2. The data input circuit according to claim 1, further comprising: input data transmission means for transmitting data to the semiconductor memory device. 3. The reverberation clock generator, wherein the reverberation pulse generator generates a pulse in response to a transition of the data clock signal, and a number of pulses generated by the reverberation pulse generator matches a designated number. The data input circuit according to claim 2, further comprising: a bust length counter that transitions an output signal at a time. 4. The reverberation clock generator is latched by a first transition of the data clock signal, unlatched by a transition of an output signal of the bust length counter, and starts and stops the operation of the reverberation pulse generator. 4. The data input circuit according to claim 3, further comprising a latch unit for generating a pulse enable signal to be adjusted. 5. The data input circuit according to claim 4, wherein the echo clock generator further comprises a reset pulse generator for generating a reset pulse in response to a transition of the pulse enable signal. 6. The data input circuit according to claim 2, wherein the echo clock generator further comprises an echo clock buffer for buffering the data clock signal with a plurality of reference voltages. 7. The data input circuit according to claim 2, further comprising a data input buffer for buffering external input data and supplying the input data to said input data transmission means. 8. The reverberation pulse generating section includes: pulse inversion delay means for inverting and delaying an input signal; pulse logical AND means for performing an AND operation of the input signal and an output signal of the pulse inversion delay means; Pulse OR sum inverting means for inverting the logical sum of the input signal and the output signal of the pulse inversion delaying means; and inverting the logical sum of the output signal of the pulse AND product and the output signal of the pulse OR summing means. 4. The data input circuit according to claim 3, further comprising a pulse OR circuit. 9. A counting signal generator for measuring the number of pulses of an output signal generated from the echo pulse generator and generating a counting signal group of the output signal, wherein the bust length counter responds to the counting signal group. And a bust signal generator for generating an output signal to be transitioned when the number of pulses of the output signal generated from the echo pulse generator matches the specified number of pulses. 4. The data input circuit according to 3. 10. The latch section, wherein: a first logical sum inverting means using a signal responsive to the data clock signal as a first input signal; an output signal of the bust length counter and an output of the first logical sum inverting means; The data input circuit according to claim 4, further comprising: a second logical sum inverting unit that receives a signal as an input signal. 11. The reset pulse generating section includes: a pulse enable inversion delay section that inverts and delays the pulse enable signal; and a pulse enable logical sum that uses the pulse enable signal and an output signal of the pulse enable inversion delay section as input signals. The data input circuit according to claim 5, further comprising: inverting means. 12. The reset pulse generating section further comprises a reset OR circuit that uses a power-up signal that generates a pulse at power-up and an output of the pulse enable OR circuit as input signals. The data input circuit according to claim 11. 13. The reverberation clock buffer, comprising: a lower current mirror configured to buffer a voltage of the data clock based on a predetermined lower reference voltage; and a lower current mirror configured to reference a predetermined upper reference voltage higher than the lower reference voltage. An upper current mirror for buffering the voltage of the data clock; an output signal of the lower current mirror as a first input signal; an output signal of the upper current mirror as a second input signal; Latch means for generating an output signal of the reverberation clock buffer, which transitions when the data clock signal falls below a reference voltage and when the level of the data clock signal rises above the upper reference voltage. The data input circuit according to claim 6. 14. In a semiconductor memory device, the input data is input to the semiconductor memory device in synchronization with an echo clock signal generated based on a data clock signal input at the same timing as input data. Data input method. 15. A reverberation clock generating step for counting the number of pulses of the data clock signal and generating pulses until the number reaches a designated number, and wherein the input is synchronized with a pulse generated in the reverberation clock generating step. The data input method according to claim 14, further comprising an input data transmitting step of transmitting data to the semiconductor memory device.