KR970049691A - Serial Data Transfer Control - Google Patents

Serial Data Transfer Control Download PDF

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Publication number
KR970049691A
KR970049691A KR1019950055623A KR19950055623A KR970049691A KR 970049691 A KR970049691 A KR 970049691A KR 1019950055623 A KR1019950055623 A KR 1019950055623A KR 19950055623 A KR19950055623 A KR 19950055623A KR 970049691 A KR970049691 A KR 970049691A
Authority
KR
South Korea
Prior art keywords
clock
rate
data
variable rate
signal
Prior art date
Application number
KR1019950055623A
Other languages
Korean (ko)
Inventor
김계수
Original Assignee
문정환
Lg 반도체 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 문정환, Lg 반도체 주식회사 filed Critical 문정환
Priority to KR1019950055623A priority Critical patent/KR970049691A/en
Priority to TW088220394U priority patent/TW430221U/en
Priority to JP8336045A priority patent/JP2926544B2/en
Publication of KR970049691A publication Critical patent/KR970049691A/en
Priority to US09/199,162 priority patent/US6002733A/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/382—Information transfer, e.g. on bus using universal interface adapter
    • G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/24—Resetting means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Communication Control (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

본 발명은 직렬 데이타 전송 제어장치는, 데이타를 다른 시스템으로 전송하기 전에 먼저 상대 시스템측에 자신의 데이타 전송률에 적합한 전송률 가변속도 클럭을 제공하는 전송클럭 제공부와, 상대 시스템측에서 전송된 상대 데이타 전송률에 따라 이에 적합한 전송률 가변속도 클럭을 발생하여 데이타를 수신하기 위한 수신클럭 발생부를 포함하여 구성되며, 상기와 같이 다른 시스템에 자신의 전송률 가변속도 클럭을 제공하고, 다른 시스템으로부터 전송된 전송률 가변속도 클럭을 이용하여 전송률 가변속도 클럭을 발생하고 이에따라 원격조정 호스트측의 데이타를 호컬 호스트 측으로 인터페이스하도록 함으로써 전송률 에러발생과 선로장애에 의한 데이타 미스 매치(miss match) 에러발생을 최소화할 수 있는 효과가 있다.According to the present invention, a serial data transmission control apparatus includes a transmission clock providing unit that provides a rate variable rate clock suitable for its data rate to a counterpart system side before transmitting data to another system, and the relative data transmitted from the counterpart system side. It consists of a receiving clock generator for receiving data by generating a rate variable rate clock according to the rate, and provides its own rate variable rate clock to another system as described above, and transmits a variable rate rate transmitted from another system By using the clock to generate a variable rate clock and interfacing the data on the remote host to the local host, it is possible to minimize the occurrence of data rate error and data miss match due to line failure. .

Description

직렬 데이타 전송 제어장치Serial Data Transfer Control

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2도는 본 발명에 의한 직렬 데이타 전송 제어장치의 구성블럭도2 is a block diagram of a serial data transmission control device according to the present invention.

제3도는 본 발명에 의한 직렬 데이타 전송 제어장치의 수신 클럭 발생부의 상세 회로도3 is a detailed circuit diagram of a reception clock generator of a serial data transmission control apparatus according to the present invention.

Claims (2)

데이타를 다른 시스템으로 전송하기 전에 먼저 상대 시스템측에 자신의 데이타 전송률에 적합한 전송률 가변속도 클럭을 제공하는 전송클럭 제공부와, 상기 시스템측에서 전송된 상대 데이타 전송률에 따라 이에 적합한 전송을 가변속도클럭을 발생하여 데이타를 수신하기 위한 수신클럭 발생부를 포함하여 구성된 것을 특징으로 하는 직렬 데이타 전송 제어장치.Before transmitting data to another system, a transmission clock providing unit which provides a rate variable rate clock suitable for its data rate to the other system side, and transmits a variable rate clock according to the relative data rate transmitted from the system side. Serial data transmission control apparatus comprising a receiving clock generator for receiving data by generating a. 제1항에 있어서, 상기 수신클럭 발생부는, 상대 시스템으로부터 전송된 클럭 셋업 데이타를 클럭신호로 하며, 마스터 리셋신호에 의해 초기화되는 제1플립플롭과, 상기 클럭 셋업 데이타의 반전신호를 클럭신호로 하며, 마스터 리셋신호에 의해 초기화되는 제2플립플롭과, 상기 제1 및 제2플립플롭의 출력을 배타논리합하여 전송률 가변속도 클럭을 발생하는 논리게이타와, 상기 마스터 리셋신호에 의해 초기화되며, 상기 전송률 가변 속도 클럭을 7까지 카운트하면 상기 클럭 셋업 데이타를 디스에이블시키기 위한 카운터를 포함하여 구성된 것을 특징으로 하는 직렬 데이타 전송 제어장치.The clock signal of claim 1, wherein the reception clock generator comprises a clock set data transmitted from a counterpart system as a clock signal, a first flip-flop initialized by a master reset signal, and an inverted signal of the clock set data as a clock signal. And a second flip-flop initialized by a master reset signal, a logic analyzer for generating a variable rate clock by exclusively combining the outputs of the first and second flip-flops, and the master reset signal, And a counter for disabling the clock setup data when the rate variable rate clock is counted up to seven. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950055623A 1995-12-23 1995-12-23 Serial Data Transfer Control KR970049691A (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
KR1019950055623A KR970049691A (en) 1995-12-23 1995-12-23 Serial Data Transfer Control
TW088220394U TW430221U (en) 1995-12-23 1996-11-28 Universal asynchronous receiver and transmitter and aninterface thereof
JP8336045A JP2926544B2 (en) 1995-12-23 1996-12-16 Serial data transmission control device
US09/199,162 US6002733A (en) 1995-12-23 1998-11-25 Universal asynchronous receiver and transmitter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950055623A KR970049691A (en) 1995-12-23 1995-12-23 Serial Data Transfer Control

Publications (1)

Publication Number Publication Date
KR970049691A true KR970049691A (en) 1997-07-29

Family

ID=19443853

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950055623A KR970049691A (en) 1995-12-23 1995-12-23 Serial Data Transfer Control

Country Status (3)

Country Link
JP (1) JP2926544B2 (en)
KR (1) KR970049691A (en)
TW (1) TW430221U (en)

Also Published As

Publication number Publication date
JP2926544B2 (en) 1999-07-28
TW430221U (en) 2001-04-11
JPH09214579A (en) 1997-08-15

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Free format text: TRIAL DECISION FOR APPEAL AGAINST DECISION TO DECLINE REFUSAL REQUESTED 19990104

Effective date: 19990731