KR980007260A - Circuit for transmitting data through the serial bus - Google Patents

Circuit for transmitting data through the serial bus Download PDF

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Publication number
KR980007260A
KR980007260A KR1019960021887A KR19960021887A KR980007260A KR 980007260 A KR980007260 A KR 980007260A KR 1019960021887 A KR1019960021887 A KR 1019960021887A KR 19960021887 A KR19960021887 A KR 19960021887A KR 980007260 A KR980007260 A KR 980007260A
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KR
South Korea
Prior art keywords
serial bus
transmission
data
bus
serial
Prior art date
Application number
KR1019960021887A
Other languages
Korean (ko)
Other versions
KR100190184B1 (en
Inventor
문강영
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019960021887A priority Critical patent/KR100190184B1/en
Publication of KR980007260A publication Critical patent/KR980007260A/en
Application granted granted Critical
Publication of KR100190184B1 publication Critical patent/KR100190184B1/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L65/00—Network arrangements, protocols or services for supporting real-time applications in data packet communication

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Information Transfer Systems (AREA)
  • Bus Control (AREA)
  • Multi Processors (AREA)

Abstract

1. 청구범위에 기재된 발명이 속한 기술분야 : 다수의 프로세서들이 연결되어 있는 직렬버스를 통해 데이터를 송신하는 회로에 관한 것이다.1. TECHNICAL FIELD The invention described in the claims pertains to a circuit for transmitting data over a serial bus to which a plurality of processors are connected.

2. 발명이 해결하려고 하는 기술적 과제 : 직렬버스를 점유하는 시간을 단축시켜 직렬버스의 통신효율을 증대시킨다.2. The technical problem to be solved by the invention: Shorten the time to occupy the serial bus to increase the communication efficiency of the serial bus.

3. 발명의 해결방법의 용지 : 본 발명은 다수의 프로세서들을 연결하고 있는 직렬버스에 접속된 각 프로세서가 그 버스로 데이터를 송신하고자 하는 경우 버스점유신호를 발생시킴과 동시에 직렬 송/수신회로를 활성화시키는 데이터 송신회로를 제공한다. 이러한 데이터 송신회로는 소정 프로세서로부터 데이터 송신 요청이 있을시 상기 직렬버스의 점유를 위한 버스점유신호를 발생하는 버스점유신호 발생회로와, 직렬버스 점유요청시 프로세서에 의해 활성화되고 상기 버스점유신호에 의해 데이터 송신클럭을 공급받게 되어 메모리 상의 송신데이타를 병렬로 수신하였다가 직렬로 송신하는 직렬 송/수신 회로와, 상기 직렬 송/수신회로로부터 직렬로 송신되는 데이터 및 송신 데이터 클럭을 송신제어신호에 따라 상기 직렬버스상에 직렬로 송신 도는 차단하는 출력버퍼로 이루어진다.3. Paper of Solution of the Invention: The present invention generates a bus occupancy signal and generates a serial transmission / reception circuit when each processor connected to a serial bus connecting a plurality of processors wishes to transmit data to the bus. A data transmission circuit for activating is provided. These data transmission circuits are bus occupancy signal generation circuits that generate a bus occupancy signal for occupancy of the serial bus when a data transmission request is made from a predetermined processor, and activated by a processor when the serial bus occupancy request is requested. The serial transmission / reception circuit receives data transmission clocks and receives transmission data in memory in parallel and transmits them serially, and the data and transmission data clocks transmitted serially from the serial transmission / reception circuits according to transmission control signals. It consists of an output buffer which transmits or blocks serially on the serial bus.

4. 발명의 중요한 용도 : 다수의 프로세서들이 직렬버스를 통해 연결되는 교환시스템에 유용하게 이용될 수 있다.4. Significant use of the invention: It can be useful for an exchange system in which multiple processors are connected via a serial bus.

Description

직렬버스를 통해 데이터를 송신하는 회로Circuit for transmitting data through the serial bus

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2도는 본 발명에 따른 데이터 송신회로의 구성을 보여주는 도면.2 is a diagram showing the configuration of a data transmission circuit according to the present invention.

Claims (2)

다수의 프로세서들이 연결되어 있는 직렬버스를 통해 데이터를 송신하는 회로에 있어서, 소정 프로세서로부터 데이터 송신요청이 있을 시 상기 직렬버스의 점유를 위한 버스점유신호를 발생하고 상기 버스점유신호가 발생된 후 상기 프로세서의 추가적인 관계없이 송신을 위한 데이터를 상기 직렬버스상에 직렬로 송신하는 것을 특징으로 하는 데이터 송신회로.A circuit for transmitting data through a serial bus to which a plurality of processors are connected, comprising: generating a bus occupancy signal for occupying the serial bus when a data transmission request is received from a predetermined processor; and after the bus occupancy signal is generated, And transmitting data for transmission serially on the serial bus irrespective of the processor. 다수의 프로세서들이 연결되어 있는 직렬버스를 통해 데이터를 송신하는 회로에 있어서, 소정 프로세서로부터 데이터 송신요청이 있을 시 상기 직렬버스의 점유를 위한 버스점유신호를 발생하는 버스점유신호 발생회로와, 상기 버스점유신호에 의해 데이터 송신클럭을 제공받게 되고, 내부의 DMA 및 SIO가 활성화된 상태에서 직렬버스 점유시점부터 상기 데이터 송신클럭이 공급되면 소정 메모리상의 데이터를 직렬로 송신하는 직렬 송/수신회로와, 상기 직렬 송/수신회로로부터 직렬로 송신되는 데이터 및 송신데이터 클럭을 상기 직렬버스상에 직렬로 송신 또는 차단하는 출력버퍼로 구성함을 특징으로 하는 데이터 송신회로.A circuit for transmitting data through a serial bus to which a plurality of processors are connected, the circuit comprising: a bus occupying signal generating circuit for generating a bus occupying signal for occupying the serial bus when a data transmission request is received from a predetermined processor; A serial transmission / reception circuit which receives a data transmission clock by an occupancy signal and transmits data in a predetermined memory serially when the data transmission clock is supplied from a serial bus occupancy state while the internal DMA and SIO are activated; And an output buffer which serially transmits or blocks data transmitted in series from the serial transmission / reception circuit and a transmission data clock on the serial bus.
KR1019960021887A 1996-06-17 1996-06-17 Transmitting circuit for data with serial bus line KR100190184B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019960021887A KR100190184B1 (en) 1996-06-17 1996-06-17 Transmitting circuit for data with serial bus line

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019960021887A KR100190184B1 (en) 1996-06-17 1996-06-17 Transmitting circuit for data with serial bus line

Publications (2)

Publication Number Publication Date
KR980007260A true KR980007260A (en) 1998-03-30
KR100190184B1 KR100190184B1 (en) 1999-06-01

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KR1019960021887A KR100190184B1 (en) 1996-06-17 1996-06-17 Transmitting circuit for data with serial bus line

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100539908B1 (en) * 1998-12-24 2006-03-09 삼성전자주식회사 High-Speed Interprocessor Communication Devices at the Exchange_
KR101275657B1 (en) * 2009-01-09 2013-06-17 알까뗄 루슨트 Transmission of parallel data flows on a parallel bus

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100539908B1 (en) * 1998-12-24 2006-03-09 삼성전자주식회사 High-Speed Interprocessor Communication Devices at the Exchange_
KR101275657B1 (en) * 2009-01-09 2013-06-17 알까뗄 루슨트 Transmission of parallel data flows on a parallel bus

Also Published As

Publication number Publication date
KR100190184B1 (en) 1999-06-01

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