KR970056168A - Master-Master Structure Implementation in Synchronous Microwave System - Google Patents
Master-Master Structure Implementation in Synchronous Microwave System Download PDFInfo
- Publication number
- KR970056168A KR970056168A KR1019950064241A KR19950064241A KR970056168A KR 970056168 A KR970056168 A KR 970056168A KR 1019950064241 A KR1019950064241 A KR 1019950064241A KR 19950064241 A KR19950064241 A KR 19950064241A KR 970056168 A KR970056168 A KR 970056168A
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- South Korea
- Prior art keywords
- master
- clock
- reference clock
- transmission
- processing unit
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Abstract
1. 청구 범위에 기재된 발명이 속한 기술분야1. TECHNICAL FIELD OF THE INVENTION
동기식 마이크로웨이브장치에서 마스터-마스터 구조를 구현하는 장치.Implementing a master-master structure in a synchronous microwave device.
2. 발명이 해결하려고 하는 기술적 과제2. The technical problem to be solved by the invention
디지탈 마이크로 웨이브 장치의 망운용을 가변적 상황에도 적합하게 운용될 수 있게 마스터-마스터 구조를 구현한다.The master-master structure is implemented so that the network operation of the digital microwave device can be operated in a variable situation.
3. 발명의 해결방법의 요지3. Summary of Solution to Invention
본 발명은 타이밍발생부에서 송/수신 클럭을 분리하도록 설계하고, 메인 트래픽을 처리하는 ASIC에서 클럭 경로를 분리하며, 대국 통신을 이용한 변경 타이밍 모드를 수행하며, 또한 대국 망운용 상태를 감시를 통한 자신의 타이밍 모드를 결정한다.The present invention is designed to separate the transmission and reception clock in the timing generator, separate the clock path from the ASIC processing the main traffic, perform the change timing mode using the power communication, and also monitor the network operation status Determine your own timing mode.
4. 발명의 중요한 용도4. Important uses of the invention
동기식 마이크로웨이브장치에서 마스터-마스터 구조를 구현.Implement master-master architecture in synchronous microwave devices.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.
제2도는 본 발명에 따라 마스터-마스터 구조로 동작되게 구현된 장치 구성도,2 is an apparatus configuration diagram implemented to operate in a master-master structure according to the present invention;
제3도는 송신클럭 유니트 30의 구체 블럭 구성도,3 is a detailed block diagram of the transmission clock unit 30,
제4도는 수신클럭 유니트 32의 구체 블럭 구성도.4 is a detailed block diagram of the reception clock unit 32.
Claims (2)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019950064241A KR970056168A (en) | 1995-12-29 | 1995-12-29 | Master-Master Structure Implementation in Synchronous Microwave System |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019950064241A KR970056168A (en) | 1995-12-29 | 1995-12-29 | Master-Master Structure Implementation in Synchronous Microwave System |
Publications (1)
Publication Number | Publication Date |
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KR970056168A true KR970056168A (en) | 1997-07-31 |
Family
ID=66622343
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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KR1019950064241A KR970056168A (en) | 1995-12-29 | 1995-12-29 | Master-Master Structure Implementation in Synchronous Microwave System |
Country Status (1)
Country | Link |
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KR (1) | KR970056168A (en) |
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1995
- 1995-12-29 KR KR1019950064241A patent/KR970056168A/en not_active Application Discontinuation
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