KR970056153A - Variable delay generator - Google Patents
Variable delay generator Download PDFInfo
- Publication number
- KR970056153A KR970056153A KR1019950066517A KR19950066517A KR970056153A KR 970056153 A KR970056153 A KR 970056153A KR 1019950066517 A KR1019950066517 A KR 1019950066517A KR 19950066517 A KR19950066517 A KR 19950066517A KR 970056153 A KR970056153 A KR 970056153A
- Authority
- KR
- South Korea
- Prior art keywords
- value
- variable delay
- frequency
- operation signal
- input
- Prior art date
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- Synchronisation In Digital Transmission Systems (AREA)
- Pulse Circuits (AREA)
Abstract
본 발명은 고속 디지탈망의 동기 신호 공급장치 정합장치의 코드 분활 다중 접속등의 무선 통신망 기지국등에 이용이 가능한 가변 딜레이 발생 장치에 있어서, 전체 딜레이 범위의 중간값에 맞춘 중앙 처리 장치의 초기값을 기준 오실레이터 주파수와 비교하여, 상기 비교값에 의해 인가되는 4 비트 데이타의 제어값에 따라 입력 주파수를 일정 딜레이 값으로 지연시켜 출력하여 위상을 동기시켜, 사용자의 의도에 따라 제어가 용이하도록 하고, 프로그램 가능한 로직 디바이스(Programmable Logic Device : PLD)의 하나의 칩에 패키지화하여 제조비용을 낮추며, 또한 입력 주파수를 최대 100MHz까지 처리할 수 있는 효과가 있다.The present invention relates to a variable delay generator that can be used in a wireless communication network base station such as a code division multiple access of a synchronization signal supply device matching device of a high-speed digital network, wherein an initial value of a central processing unit is set based on an intermediate value of the entire delay range. Compared with the oscillator frequency, according to the control value of the 4-bit data applied by the comparison value, the input frequency is delayed and outputted by a predetermined delay value to synchronize the phase, so that the control is easy and programmable according to the intention of the user. Packaged on one chip of a programmable logic device (PLD) to reduce manufacturing costs, and can also handle input frequencies up to 100MHz.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.
제1도는 본 발명의 블록도,1 is a block diagram of the present invention,
제2도는 본 발명의 회로도.2 is a circuit diagram of the present invention.
Claims (3)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019950066517A KR970056153A (en) | 1995-12-29 | 1995-12-29 | Variable delay generator |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019950066517A KR970056153A (en) | 1995-12-29 | 1995-12-29 | Variable delay generator |
Publications (1)
Publication Number | Publication Date |
---|---|
KR970056153A true KR970056153A (en) | 1997-07-31 |
Family
ID=66637338
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019950066517A KR970056153A (en) | 1995-12-29 | 1995-12-29 | Variable delay generator |
Country Status (1)
Country | Link |
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KR (1) | KR970056153A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100883353B1 (en) * | 2006-09-26 | 2009-02-11 | (주)나노알앤씨 | Variable delay block and method for embodying the block |
-
1995
- 1995-12-29 KR KR1019950066517A patent/KR970056153A/en not_active Application Discontinuation
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100883353B1 (en) * | 2006-09-26 | 2009-02-11 | (주)나노알앤씨 | Variable delay block and method for embodying the block |
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WITN | Withdrawal due to no request for examination |