KR970056153A - Variable delay generator - Google Patents

Variable delay generator Download PDF

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Publication number
KR970056153A
KR970056153A KR1019950066517A KR19950066517A KR970056153A KR 970056153 A KR970056153 A KR 970056153A KR 1019950066517 A KR1019950066517 A KR 1019950066517A KR 19950066517 A KR19950066517 A KR 19950066517A KR 970056153 A KR970056153 A KR 970056153A
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KR
South Korea
Prior art keywords
value
variable delay
frequency
operation signal
input
Prior art date
Application number
KR1019950066517A
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Korean (ko)
Inventor
안만순
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019950066517A priority Critical patent/KR970056153A/en
Publication of KR970056153A publication Critical patent/KR970056153A/en

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  • Synchronisation In Digital Transmission Systems (AREA)
  • Pulse Circuits (AREA)

Abstract

본 발명은 고속 디지탈망의 동기 신호 공급장치 정합장치의 코드 분활 다중 접속등의 무선 통신망 기지국등에 이용이 가능한 가변 딜레이 발생 장치에 있어서, 전체 딜레이 범위의 중간값에 맞춘 중앙 처리 장치의 초기값을 기준 오실레이터 주파수와 비교하여, 상기 비교값에 의해 인가되는 4 비트 데이타의 제어값에 따라 입력 주파수를 일정 딜레이 값으로 지연시켜 출력하여 위상을 동기시켜, 사용자의 의도에 따라 제어가 용이하도록 하고, 프로그램 가능한 로직 디바이스(Programmable Logic Device : PLD)의 하나의 칩에 패키지화하여 제조비용을 낮추며, 또한 입력 주파수를 최대 100MHz까지 처리할 수 있는 효과가 있다.The present invention relates to a variable delay generator that can be used in a wireless communication network base station such as a code division multiple access of a synchronization signal supply device matching device of a high-speed digital network, wherein an initial value of a central processing unit is set based on an intermediate value of the entire delay range. Compared with the oscillator frequency, according to the control value of the 4-bit data applied by the comparison value, the input frequency is delayed and outputted by a predetermined delay value to synchronize the phase, so that the control is easy and programmable according to the intention of the user. Packaged on one chip of a programmable logic device (PLD) to reduce manufacturing costs, and can also handle input frequencies up to 100MHz.

Description

가변 딜레이 발생 장치Variable delay generator

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명의 블록도,1 is a block diagram of the present invention,

제2도는 본 발명의 회로도.2 is a circuit diagram of the present invention.

Claims (3)

기준 오실레이터에서 발생되는 주파수와 비교 주파수의 위상을 동기시키는 가변 딜레이 장치에 있어서, 중앙 처리 장치로부터 입력된 4개의 어드레스를 16개의 동작 신호로 출력하는 역다중화부(10)와; 상기 역다중화부(10)를 통해 동작 신호가 입력되는 순간의 출력을 계속 유지하여 동작 신호를 출력하는 동작 제어부(20)와; 입력 주파수를 지연시키는 딜레이 회로(31)와, 상기 동작 제이버(20)에서 출력되는 동작신호로 제어되어 기준 주파수의 비교에 의한 데이타 값에 따라, 상기 딜레이 회로(31)에서 지연된 신호를 출력하는 다중화기(32)로 이루어진 256 비트 다중화부(30)로 구성됨을 특징으로 하는 가변 딜레이 발생 장치.A variable delay device for synchronizing a phase of a reference frequency with a frequency generated by a reference oscillator, comprising: a demultiplexer (10) for outputting four addresses input from a central processing unit as sixteen operation signals; An operation control unit 20 for continuously outputting an operation signal while maintaining an output at the moment of inputting an operation signal through the demultiplexer 10; A delay circuit 31 for delaying an input frequency and an operation signal output from the operation jaw 20 to output a delayed signal from the delay circuit 31 according to a data value obtained by comparison of a reference frequency. Variable delay generation device characterized in that it consists of a 256-bit multiplexer (30) consisting of a multiplexer (32). 제1항에 있어서, 상기 동작 제어부(20)는 동작신호가 입력되는 순간의 출력을 계속 유지하여 동작신호를 출력하는 D 플립플롭(20-1)를 포함하여 이루어짐을 특징으로 하는 가변 딜레이 발생 장치.The apparatus of claim 1, wherein the operation control unit 20 includes a D flip-flop 20-1 for continuously outputting an operation signal while maintaining an output at the moment when the operation signal is input. . 제1항에 있어서, 상기 딜레이 회로(31)는 입력 주파수를 256 단게로 딜레이하는 CMOS 버퍼소자를 포함하여 이루어짐을 특징으로 하는 가변 딜레이 발생 장치.2. The variable delay generating apparatus according to claim 1, wherein the delay circuit (31) comprises a CMOS buffer element for delaying an input frequency by 256 steps. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950066517A 1995-12-29 1995-12-29 Variable delay generator KR970056153A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950066517A KR970056153A (en) 1995-12-29 1995-12-29 Variable delay generator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950066517A KR970056153A (en) 1995-12-29 1995-12-29 Variable delay generator

Publications (1)

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KR970056153A true KR970056153A (en) 1997-07-31

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Application Number Title Priority Date Filing Date
KR1019950066517A KR970056153A (en) 1995-12-29 1995-12-29 Variable delay generator

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100883353B1 (en) * 2006-09-26 2009-02-11 (주)나노알앤씨 Variable delay block and method for embodying the block

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100883353B1 (en) * 2006-09-26 2009-02-11 (주)나노알앤씨 Variable delay block and method for embodying the block

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