SU739511A1 - Interface - Google Patents

Description

one

The invention relates to the field of computer automation and is intended to organize the exchange of information both within the computer and between computers and peripheral devices.

A device for transmitting and exchanging information is known that is intended for organizing the operation of computers 1 and contains an exchange register, a priority selection block, a peripheral register, an output and an input of which are connected via an exchange register. The control unit is connected to the output of the central processor and the output of the highlight 15 of the selection of priority. The control unit peripheral device is connected, the output to the input block priority selection. The first output of the control unit is connected to the control input of the register- 20 tpa exchange, connected by information buses to the central processor. The system switch is connected to the first and second inputs to the first and second outputs of the control unit, respectively, to peripheral devices. The control input of the switch is connected to the second output of the control unit, and the output is connected to the control input of the peripheral register, 30

Of the known devices and systems for transmitting and exchanging information, the closest to the invention is a device comprising a clock generator, connected to the AND element and clock buses, an information source and receivers connected to the information buses, an operation end bus, a delay block connected with a memory block, request and synchronization buses connected to an AND 2 element.

The disadvantage of such devices is low performance due to the fact that they cannot exchange information between sources and receivers of information in several directions. Information transfer is possible only in one receiver from several sources, which requires a large amount of electronic equipment. In addition, when simultaneously requesting the transmission of two or more sources, almost all units of the system are involved in choosing the most priority receiver, which reduces the reliability of its operation,

The aim of the invention is to increase the speed and reliability of the device.

The goal is achieved by introducing decoders connected to the source and receivers of information to the known device, to the buses. The end of operations, interrogation, clock information buses, and the sequentially connected driver of the priority code connected to the clock buses, bus and synchronization buses, and the driver of the code. addresses connected to the AND element, information buses, request buses and end of operations. The drawing shows a block diagram of a device for conjugation. The request part of the device is formed by block locks 1 connected by the output to the first input of the memory block TI 2. Information receiver 3 is connected to the output of the decoder 4, input of the information source 5 is connected to the output of the similar decoder 6. The generator of pulse pulses 7 is connected to the same input of the And 8 element The first output of the address code generator 9 is connected to the first inputs of the decoder 4 and b, the second input to the second inputs of the decoder 4 and b, the second inputs of the priority code 10 emitter, the second inputs of the memory block 2 and the first inputs of the delay block ki 1, the third input is an input of a memory block with an output of an And 8 element and the first input of a priority code generator 10.

VELKHOD driver 10 is connected via driver 9 with third inputs 1 F1 of decryptors 4 and 6. Fourth inputs of decoders 4 and about badi; noon between the two, one 1t1 input of memory 2 and the third input of generator 10. Another fourth output of the driver 9 is connected to another the input element and

Delay unit 1 contains a trigger 11 connected by a single output to an element 12. The memory block 2 contains a trigger 13 connected via an element 14 and a counter 15 to the inputs of the element 16.

The decoder 4 contains the Shift register 17 connected via element 18 to the input xpHriepa 19, clock pulse 7, element 8, the driver 8, address 9, and the device nipHo 10, form the synchronized part of the device.

Descrambler b and source of information; . 5 form the transmitter, the devices, and the decoder 4 and the information receiver 3 are the receiving part of the device.

 The bus 2A, connected with the input device, is connected to the second input of the delay unit 1. The device contains Synchronization buses 21, end-of-operation buses 22, -query bus 23, informational 24, and clock 25 buses.

The device works as follows .-. .

In the initial state, the pulses from the generator 7 come through the open element And 8 to the synchronization bus 21. From the other output of the generator 7, the pulses go to the clock bus 25. The source of information 5 accumulates information about any calculation or measurement. During device operation, the requirement for information exchange between information source 5 and information receiver 3 comes from input 20 to unit shoulder of trigger 11 of delay block 1. Resolution from trigger 11 goes to AND 12 element. Another synchronization pulse passes through AND 12 element and sets trigger 13 in one state. Striger 13 on the element And 14 behaves resolution. The pulses from the clock | bus 25 begin to flow through the element AND 14 into the counter 15, in which the counting in the binary code is performed. Element 16 is connected to the triggers of counter 15 in such a way that the signal at its output appears with a certain code in counter 15. This code is the priority code of the requested block. The signal from the output of the element 16 sets the trigger 11 to the zero state and goes to the query bus 23. From the query bus, it is only perceived by the driver 10. The driver 10 has the same counter, (not shown in the drawing, as the counter 15, counting pulses synchronously With the name of the signal from the output of the element AND 16, the priority code from the generator 10 is transferred to the driver 9. At the same time, this code is the start code of a certain information transfer program, which is formed by the driver 9. The driver 9 sets the ban on the element of both 8 and the synchronization pulses no longer go to the synchronization bus, and also transmits an address code between the requesting unit (receiver) and the unit to which information needs to be transmitted over the information bus. clock bus. The address code is received by the shift registers 17 of the decoders 4 and 6. After the address code has been transmitted, the driver 9 forms a command to the 1 st request. This command in decoder 4 and 6 interrogates the elements AND lie associated with the shift registers. 17 and the triggers 19 are installed into one unit. From the decoder b, into the SOURCE of information 5, and from the forerunner 4 to the information receiver 3 receives permission to transmit and receive information, respectively. From 1 ohm of pulse shear pulses from a clock bus to information is transmitted from a source

Claims (1)

. Claim 1. The device for interfacing, containing a clock generator connected to the element AI clock buses, a source and receivers of information connected to information buses, buses of the end of operations and a block, delays connected to a memory block, request and synchronization buses connected to an element And, with the fact that, in order to increase the speed and reliability of the device, decoders connected to it are introduced into it; a source and receivers of information, with buses of the end of operations, request, clock and information, buses, and a shaper of priority code connected to clock buses, request and synchronization buses, and an address code shaper connected to the And element, · information buses, buses request and end of operations.