KR940027299A

KR940027299A - Modular Clock Signal Generation Circuit

Info

Publication number: KR940027299A
Application number: KR1019930008929A
Authority: KR
Inventors: 에이취. 제이. 리 로버트; 디. 케니 존
Original assignee: 캐롤린 에이. 로저스; 피코파워 테크놀러지 인크.
Priority date: 1993-05-24
Filing date: 1993-05-24
Publication date: 1994-12-10

Abstract

클럭신호발생 회로는 전자 시스템의 선택된 부분에 제공된 클럭신호를 이들 부분이 사용되지 않는 동안에 선택적으로 디스에이블하여 전자 시스템의 하나 이상의 부분에 클럭신호를 제공함으로써, 전자 시스템에 의해 소모된 전력을 효과적으로 감소시킨다.The clock signal generation circuit selectively disables clock signals provided to selected portions of the electronic system while those portions are not used to provide clock signals to one or more portions of the electronic system, thereby effectively reducing the power consumed by the electronic system. Let's do it.

클럭신호발생 회로는 클럭신호를 전자 시스템의 하나 이상의 부분에 전송하는 수단, 및 전자 시스템의 상기 부분에 상기 클럭신호의 전송을 방지하기 위해 상기 전송수단을 디스에이블시키는 수단을 포함한다.The clock signal generation circuit includes means for transmitting a clock signal to one or more portions of an electronic system, and means for disabling the transmitting means to prevent transmission of the clock signal to the portion of the electronic system.

또한, 모듈러 클럭 회로는 돌연한 고장 또는 이와 유사한 성질의 다른 문제점이 없는 논리 회로 또는 시스템을 동기하여 동작시킬 수 있도록 회로 또는 서브시스템의 각각의 부분에 제공된 클럭신호를 동기시킨다.In addition, the modular clock circuitry synchronizes the clock signal provided to each part of the circuit or subsystem so that the logic circuit or system can operate synchronously without sudden failure or other problems of similar nature.

Description

Modular Clock Signal Generation Circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제 1 도는 본 발명의 한 실시예를 도시한 블럭도, 제 2 도는 제 1 도의 회로를 사용하여 발생된 파형을 도시한 도면, 제 3 도는 본 발명에 따른 다수의 모듈러 클럭을 이용하는 시스템을 도시한 도면.1 is a block diagram illustrating an embodiment of the present invention, FIG. 2 is a diagram showing waveforms generated using the circuit of FIG. 1, and FIG. 3 is a system using a plurality of modular clocks in accordance with the present invention. drawing.

Claims

A clock signal generation circuit for providing a clock signal to at least one portion of an electronic system and selectively disabling the clock signal in relation to that provided to the portion of the electronic system, wherein the clock signal is transmitted to the portion of the electronic system. And means for disabling said transmission means to prevent transmission of said clock signal to said portion of said electronic system.

The AND gate of claim 1, wherein the transmission means enables or disables a flip-flop, an AND gate, as needed, which can generate an output signal having first and second states. Means for transmitting to one input lead of the clock signal source, and means for transmitting the clock signal to another input lead of the AND gate, the AND gate being on the output lead from the flip flop under a first state. Sends the clock signal to the output read from the AND gate in response to a signal, and the AND gate does not transmit the clock signal to the output read from the AND gate in response to a signal from the flip flop under a second state. And a clock signal generating circuit.

An electronic system comprising at least one circuit of claim 2.

An electronic system comprising at least two circuits of claim 1.

※ Note: The disclosure is based on the initial application.