KR960006272A - Primary / dependent flip-flop - Google Patents

Primary / dependent flip-flop Download PDF

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Publication number
KR960006272A
KR960006272A KR1019940018514A KR19940018514A KR960006272A KR 960006272 A KR960006272 A KR 960006272A KR 1019940018514 A KR1019940018514 A KR 1019940018514A KR 19940018514 A KR19940018514 A KR 19940018514A KR 960006272 A KR960006272 A KR 960006272A
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KR
South Korea
Prior art keywords
clock pulse
inverted
signal
multiplexer
input signal
Prior art date
Application number
KR1019940018514A
Other languages
Korean (ko)
Other versions
KR0131163B1 (en
Inventor
김용범
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019940018514A priority Critical patent/KR0131163B1/en
Publication of KR960006272A publication Critical patent/KR960006272A/en
Application granted granted Critical
Publication of KR0131163B1 publication Critical patent/KR0131163B1/en

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/3562—Bistable circuits of the master-slave type
    • H03K3/35625—Bistable circuits of the master-slave type using complementary field-effect transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01—Details
    • H03K3/012—Modifications of generator to improve response time or to decrease power consumption

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  • Electronic Switches (AREA)
  • Logic Circuits (AREA)

Abstract

본 발명은 클럭펄스(CLK+)로 제어받아 입력신호(IN+)및 그 입력신호의 반전신호(IN-)를 각각 출력하는 제1멀티플렉서(MUX1), 클럭펄스(CLK+)가 로우에서 하이로 전이할때 상기 제1멀티플렉서(MUX1)로부터 입력신호(IN+)및 그 반전신호(IN-)를 전달받아 래치하는 마스터 래치부, 반전된 클럭펄스(CLK-)로 제어받아 상기 마스터 래치부의 출력신호(노드 A및/A의 신호)를 각각 출력하는 제2멀티플렉서(MUX2), 상기 반전 클럭펄스(CLK-)가 로우에서 하이로 전이할때 상기 제2멀티플레서(MUX2)로부터 상기 마스터 래치부의 출력신호(노드 A및/A의 신호)을 래치하는 슬레이브 래치부를 포함하여 이루어지는 것을 특징으로 하는 주/종속 플립-플롭(master/slave flip-flop)에 관한 것으로 주/종속 플립-플롭이 치밀하게 구성되어 칩 영역을 줄이고, 고속동작을 이루는 효과가 있다.According to the present invention, the first multiplexer MUX1 and the clock pulse CLK +, which are controlled by the clock pulse CLK + and output the input signal IN + and the inverted signal IN− of the input signal, respectively, may transition from low to high. The master latch unit receives the input signal IN + and its inverted signal IN− from the first multiplexer MUX1, and is controlled by an inverted clock pulse CLK- and output signal (node) of the master latch unit. A second multiplexer MUX2 that outputs A and / A signals, respectively, and an output signal of the master latch unit from the second multiplexer MUX2 when the inverted clock pulse CLK- transitions from low to high; A master / slave flip-flop, comprising a slave latch section for latching signals of nodes A and / A). It is effective in reducing the area and achieving high speed operation.

Description

주/종속 플립-플롭Primary / dependent flip-flop

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제3도는 본 발명에 따른 주/종속 플립-플롭 회로도3 is a main / dependent flip-flop circuit diagram in accordance with the present invention.

제4도는 클럭펄스(CLK+)가 하이에서 로우 상태로 전이할때 실제 동작되는 회로도.4 is a circuit diagram that actually operates when the clock pulse CLK + transitions from high to low.

Claims (2)

클럭펄스로 제어받아 입력신호 및 그 입력신호의 반전신호를 각각 출력하는 제1멀티플렉서, 클럭펄스가 로우에서 하이로 전이할 때 상기 제1멀티플렉서로부터 입력신호 및 그 반전신호를 전달받아 래치하는 마스터 래치부, 반전된 클럭펄스로 제어받아 상기 마스터 래치부의 출력신호를 각각 출력하는 제2멀티플렉서, 상기 반전 클럭펄스가 로우에서 하이로 전이할때 상기 제2멀티플렉서로부터 상기 마스터 래치부의 출력신호를 래치하는 슬레이브 래치부를 포함하여 이루어지는 것을 특징으로 하는 주/종속 플립-플롭(master/slave flip-flop)A first multiplexer which is controlled by a clock pulse and outputs an input signal and an inverted signal of the input signal, respectively, and a master latch that receives and inputs an input signal and the inverted signal from the first multiplexer when the clock pulse transitions from low to high A second multiplexer controlled by an inverted clock pulse to output an output signal of the master latch unit, and a slave latching an output signal of the master latch unit from the second multiplexer when the inverted clock pulse transitions from low to high; Master / slave flip-flop, characterized in that it comprises a latch portion 제1항에 있어서, 상기 슬레이브 래치부는 상기 반전된 클럭펄스가 로우에서 하이로 전이할때 마스터 래치부와 포지티브 피드백을 이루도록 구성된 제1인버터부 및 제2인버터부를 포함하여 이루어지는 것을 특징으로 하는 주/종속 플립-플롭.The main / second inverter unit of claim 1, wherein the slave latch unit includes a first inverter unit and a second inverter unit configured to form positive feedback with the master latch unit when the inverted clock pulse transitions from low to high. Dependent flip-flop. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940018514A 1994-07-28 1994-07-28 Flip-flop circuit KR0131163B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940018514A KR0131163B1 (en) 1994-07-28 1994-07-28 Flip-flop circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940018514A KR0131163B1 (en) 1994-07-28 1994-07-28 Flip-flop circuit

Publications (2)

Publication Number Publication Date
KR960006272A true KR960006272A (en) 1996-02-23
KR0131163B1 KR0131163B1 (en) 1998-10-01

Family

ID=19389207

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019940018514A KR0131163B1 (en) 1994-07-28 1994-07-28 Flip-flop circuit

Country Status (1)

Country Link
KR (1) KR0131163B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100342454B1 (en) * 1998-11-27 2002-06-28 가네꼬 히사시 Latch circuit

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101494519B1 (en) * 2013-04-30 2015-02-23 인하대학교 산학협력단 Low power FlipFlop Circuit composed of a Charge steering latch and a Dynamic Current Mode Latch

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100342454B1 (en) * 1998-11-27 2002-06-28 가네꼬 히사시 Latch circuit

Also Published As

Publication number Publication date
KR0131163B1 (en) 1998-10-01

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