KR101494519B1 - Low power FlipFlop Circuit composed of a Charge steering latch and a Dynamic Current Mode Latch - Google Patents

Abstract

A low power flip-flop circuit and method of operation for high-speed data processing are presented. And is connected to a master and a master using a charge-driven latch that consumes a low power. When an NRZ pattern is applied with an input voltage, the same NRZ To a low power flip-flop circuit including a slave using a dynamic current mode latch in which a pattern is output. In addition, the proposed flip-flop can reduce the power consumption by flowing current only during the half period of the clock.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a low-power flip-flop circuit comprising a charge-driven latch and a dynamic current mode latch,

The present invention relates to low power flip-flop circuit implementations for high speed data processing. More particularly, the present invention relates to a method and apparatus for controlling power consumption, including a master using a charge-driven latch that consumes a low power and a slave using a dynamic current mode latch, outputting an output voltage pattern identical to the pattern of the input voltage without additional circuitry, To a low power flip-flop circuit for high speed data processing.

A semiconductor device includes a memory cell array in which data is stored and a plurality of circuits for storing data in the memory cell array or for reading stored data. Of the plurality of circuits, the page buffer controls the voltage of the bit lines connected to the memory cell array in response to page buffer signals output from the control circuit.

Korean Unexamined Patent Publication No. 2001-0136533 discloses a technique of connecting a bit line connected to the cell strings and a latch for storing data according to cell strings and page buffer control signals including the plurality of memory cells, A page buffer including circuits for free charge, and the like.

A latch circuit widely used in such a semiconductor is generally used in a flip-flop circuit as a circuit having a function of capturing a signal and holding it, and is applicable and applicable to many fields. For example, when the latch circuit is applied to a vehicle, the latch circuit maintains the current state when the power is applied. However, the conventional latch circuit has a problem that current consumption is large in a normal state and the current state can not be maintained when the applied power is cut off. Further, the latch circuit ignores the previous state and does not memorize the current operation state even when the operating power source is re-input, thereby causing the latch circuit to become the default state.

Conventionally, a circuit of a current mode logic (CML) latch has been commonly used to configure a master-slave flip-flop. Such a current mode logic (CML) latch performs a latch function by varying a direction of a current according to a clock signal. Current Mode Logic (CML) latches do not require the use of rail-to-rail signals compared to CMOS static structures. For example, in the context of a signal chain, when an op amp drives an ADC, you can see the output limits of an op amp with a rail-to-rail swing. The typical closed loop bandwidth of the amplifier is about 3 MHz at a typical slew rate of 2.3 V / μs. The output voltage swing of the amplifier is 140mV to 4.66V, and the headroom between the signal and the rail is 140mV in this 5V supply system. The minimum value of VOL in this amplifier is +15 mV, and the maximum value of VOH may be VDD-20 mV. Single-supply CMOS amplifiers can exhibit nonlinear output stage effects that exhibit distortion over 2/3/4 kHz. By reducing the amplifier output signal from each rail to 272mV, the data can have a perfect appearance with only ADC distortion.

In addition, the current mode logic (CML) latch has an advantage in that data can be processed at a higher speed than a CMOS static structure. However, since the current continues to flow throughout the latch operation, high power consumption is a disadvantage.

As another example according to the prior art, a circuit of a charge steering latch is also commonly used. In this charge steering latch, when the clock is low, the PMOS switch at the upper end of the input voltage is turned on but the NMOS switch at the lower end of the input voltage is turned off so that both ends of the output voltage are both VDD After the battery is charged, the clock goes high, and the capacitance is charged by the voltage difference of the input voltage to evaluate the latch operation. This charge steering latch circuit has the advantage of consuming low power in the latch operation. In addition, when a non-return to zero (NRZ) pattern is applied, an output of a RZ (return to zero) pattern can be output. This disadvantageously requires additional circuitry for cascading the latch circuits in parallel to perform a flip-flop operation and for generating a non-return to zero (NRZ) pattern.

Such a conventional flip-flop circuit using charge steering can perform a flip-flop operation. However, like the circuit of the charge steering latch, when a non-return to zero (NRZ) pattern is applied, the output of the RZ (return to zero) pattern is output and the NRZ (non-return to zero) There is a disadvantage in that additional circuitry is required.

SUMMARY OF THE INVENTION The present invention provides a low-power flip-flop circuit for high-speed data processing. In addition, when power consumption is reduced and a non-return to zero (NRZ) pattern is applied without additional circuitry for outputting an NRZ pattern unlike the prior art charge steering latch, will be.

In one aspect, a low-power flip-flop circuit incorporating a charge-driven latch and a dynamic current mode latch proposed in the present invention performs a latch operation by charging a capacitance by an input voltage difference and performs a charge operation by consuming a low- And a slave using a dynamic current mode latch that is connected to a master and a master using a latch type and outputs the same NRZ pattern without an additional circuit when an NRZ pattern is applied with an input voltage.

The slave of the low-power flip-flop circuit that combines the charge-driven latch and the dynamic current-mode latch has the MOS switch turned on when the clock is high and the current flows, And performs an operation. Further, when the clock is Low, the MOS switch is turned off and no current flows.

A low-power flip-flop circuit that combines a charge-driven latch and a dynamic current-mode latch can reduce power consumption by allowing current to flow only during a half-clock period of the clock.

In one aspect, a method for operating a low-power flip-flop circuit that combines a charge-driven latch and a dynamic current mode latch proposed in the present invention utilizes a difference in input voltage through a charge- Transferring the output voltage of the master to the input voltage of the slave using the dynamic current mode latch and the slave receiving the input voltage and outputting the same pattern as the input voltage pattern without additional circuit And outputting a voltage.

A low-power flip-flop circuit that combines a charge-driven latch and a dynamic current mode latch. The slave according to the method of operating the circuit receives an input voltage and outputs an output voltage having the same pattern as the input voltage pattern without any additional circuit. When applied, the same NRZ pattern is output. In addition, the flip-flop can reduce power consumption by flowing current only during a half-period of the clock.

According to embodiments of the present invention, a low-power flip-flop circuit for high-speed data processing uses a master using a charge-driven latch that consumes low power and a slave using a dynamic current mode latch, And the current can flow only during the half period of the clock to reduce the power consumption.

1 is a diagram showing a charge steering latch circuit according to the prior art.
2 is a diagram showing a charge steering flip-flop circuit according to the prior art.
3 is a diagram illustrating a low-power flip-flop circuit that combines a charge-driven latch and a dynamic current mode latch.
4 is a flowchart for explaining the operation of the low-power flip-flop circuit combining the charge-driven latch and the dynamic current mode latch.
5 is a diagram showing simulation results of a low-power flip-flop circuit according to an embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a diagram showing a charge steering latch circuit according to the prior art.

1, a charge steering latch circuit M1 is turned on when the clock CK is low, M2 is turned on but M5 is turned off, Both of the output voltage Vout and the output voltage Vout are charged by the supply voltage VDD and the clock becomes high and the capacitor is charged by the voltage difference of the input voltage Vin input to M3 and M4 Thereby performing a latch operation. Such a charge steering latch circuit has an advantage of consuming low power in performing the latch operation. In the above circuit, when the NRZ pattern is applied to the input voltage, the output voltage of the RZ pattern is outputted. As a result, a flip-flop operation can not be performed by connecting a latch circuit with a cascade, and there is a disadvantage that an additional circuit for generating an NRZ pattern output voltage is required.

The types of the digital signal codes are RZ (return to zero) and NRZ (non-return to zero). NRZ (non-return to zero) is a type of digital signal coding method, which is used when a physical layer transmits a signal. In NRZ, the binary values of '1' and '0' are converted into positive (+) voltage values and negative (-) voltage values, respectively.

NRZ is composed of a pulse waveform with a time width equal to the pulse interval, and there is no change in voltage when the marks are continuous. On the contrary, it may be preferable to separate consecutive marks for each mark. In this manner, RZ is constituted by a pulse waveform having a time width shorter than the pulse interval. In the case of RZ (pulse width / pulse interval), it is called duty factor and expressed in%. An RZ signal having an impact coefficient of 50% is usually used. In the case of a bipolar signal, it is composed of NRZ and RZ. In a wired transmission line, an RZ anode type signal having an ordinary duty factor of 50% is used.

In the positive logic NRZ, the low state is represented by a lower negative (-) voltage or a lower positive (+) voltage, and the higher state is represented by a lower negative voltage or a higher constant voltage.

For example, for a positive logic NRZ,

In the negative logic NRZ, a low state is represented by a higher constant voltage or a lower voltage, and a higher state is represented by a lower positive voltage or a lower negative voltage.

For example, the negative logic NRZ can be expressed as:

2 is a diagram showing a charge steering flip-flop circuit according to the prior art.

Conventionally, a circuit of a current mode logic (CML) latch is commonly used to configure a master-slave flip-flop. Such a current mode logic (CML) latch performs a latch function by varying a direction of a current according to a clock signal. Current Mode Logic (CML) latches do not require the use of rail-to-rail signals compared to CMOS static structures. For example, in the context of a signal chain, when an op amp drives an ADC, you can see the output limits of an op amp with a rail-to-rail swing. The typical closed loop bandwidth of the amplifier is about 3 MHz at a typical slew rate of 2.3 V / μs. The output voltage swing of the amplifier is 140mV to 4.66V, and the headroom between the signal and the rail is 140mV in this 5V supply system. The minimum value of VOL in this amplifier is +15 mV, and the maximum value of VOH may be VDD-20 mV. Single-supply CMOS amplifiers can exhibit nonlinear output stage effects that exhibit distortion over 2/3/4 kHz. By reducing the amplifier output signal from each rail to 272mV, the data can have a perfect appearance with only ADC distortion.

In addition, the current mode logic (CML) latch has an advantage in that data can be processed at a higher speed than a CMOS static structure. However, since the current continues to flow throughout the latch operation, high power consumption is a disadvantage.

As another example according to the prior art, a circuit of a charge steering latch is also commonly used. In this charge steering latch, when the clock is low, the PMOS switch at the upper end of the input voltage is turned on but the NMOS switch at the lower end of the input voltage is turned off so that both ends of the output voltage are both VDD After the battery is charged, the clock goes high, and the capacitance is charged by the voltage difference of the input voltage to evaluate the latch operation. This charge steering latch circuit has the advantage of consuming low power in the latch operation. In addition, when a non-return to zero (NRZ) pattern is applied, an output of a RZ (return to zero) pattern can be output. This disadvantageously requires additional circuitry for cascading the latch circuits in parallel to perform a flip-flop operation and for generating a non-return to zero (NRZ) pattern.

Such a conventional flip-flop circuit using charge steering can perform a flip-flop operation. 2, a flip-flop having a structure of a master 210 and a slave 220 is used. However, like the circuit of a charge steering latch, a non-return to zero (NRZ) pattern There is a disadvantage in that an additional circuit for generating a non-return to zero (NRZ) pattern is required.

3 is a diagram illustrating a low-power flip-flop circuit that combines a charge-driven latch and a dynamic current mode latch.

A low-power flip-flop that combines a charge-driven latch and a dynamic current mode latch comprises a structure of a master 310 and a slave 320.

Charge steering latch circuits in a Master 310 using charge-driven latches have the advantage of consuming low power in performing latch operations. However, the charge steering latch circuit outputs the output voltage of the RZ pattern when the NRZ pattern is applied to the input voltage. As a result, a flip-flop operation can not be performed by connecting a latch circuit with a cascade, and there is a disadvantage that an additional circuit for generating an NRZ pattern output voltage is required. Therefore, when an NRZ pattern is applied without an additional circuit, it is possible to output an output voltage having the same pattern as that of the input voltage by connecting to a slave using a dynamic current mode latch in which the same NRZ pattern is output.

When the clock (CK) is high in the slave using the dynamic current mode latch, the PMOS switches M1 and M2 and the NMOS switch M5 are turned on and the current flows and the input voltage Vin Transparent operation is shown depending on the voltage. When the clock is low, the PMOS switches M1 and M2 and the NMOS switch M5 are turned off, so that the current can no longer flow and the latch operation is performed accordingly. In the proposed circuit, since the current flows only during the half period of the clock (CK), the power consumption can be reduced. Also, unlike Charge Steering, when the NRZ pattern is applied, the same NRZ pattern is output, so no additional circuit is required.

By connecting the master 310 using the charge-driven latch and the slave 320 using the dynamic current mode latch, a flip-flop circuit operating at low power can be implemented.

4 is a flowchart for explaining the operation of the low-power flip-flop circuit combining the charge-driven latch and the dynamic current mode latch.

The operation of the low-power flip-flop circuit that combines the charge-driven latch and the dynamic current mode latch includes performing (410) a latch operation using a difference in input voltage through a charge-driven master consuming low power (410) (420) the dynamic current mode latch to the input voltage of the slave using the slave, and the slave receives the input voltage and outputs (430) an output voltage of the same pattern as the input voltage pattern without additional circuitry.

A low-power flip-flop that combines a charge-driven latch and a dynamic current-mode latch consists of a master and a slave.

First, the operation of the low-power flip-flop circuit combining the charge-driven latch and the dynamic current mode latch performs a latch operation using the difference of the input voltage (Vin) through the charge-driven master consuming low power (410). Charge steering latch circuits in a master using charge-driven latches have the advantage of consuming low power in latch operation. However, the charge steering latch circuit outputs the output voltage of the RZ pattern when the NRZ pattern is applied to the input voltage. As a result, a flip-flop operation can not be performed by connecting a latch circuit with a cascade, and there is a disadvantage that an additional circuit for generating an NRZ pattern output voltage is required. Therefore, when an NRZ pattern is applied without an additional circuit, it is possible to output an output voltage having the same pattern as that of the input voltage by connecting to a slave using a dynamic current mode latch in which the same NRZ pattern is output. Thus, the output voltage of the master is transferred 420 to the input voltage of the slave using the dynamic current mode latch.

Thereafter, the slave receives the input voltage and outputs an output voltage of the same pattern as the input voltage pattern without any additional circuit (430). When the clock CK is high in the slave using the dynamic current mode latch, the PMOS switches M1 and M2 and the NMOS switch M5 are turned on and the current flows and the input voltage Vin Transparent operation is shown depending on the voltage. When the clock is low, the PMOS switches M1 and M2 and the NMOS switch M5 are turned off, so that the current can no longer flow and the latch operation is performed accordingly. In the proposed circuit, since the current flows only during the half period of the clock (CK), the power consumption can be reduced. Also, unlike Charge Steering, when the NRZ pattern is applied, the same NRZ pattern is output, so no additional circuit is required.

By connecting the master using the charge-driven latch and the slave using the dynamic current mode latch, a flip-flop circuit operating at low power can be realized.

5 is a diagram showing simulation results of a low-power flip-flop circuit according to an embodiment of the present invention.

Referring to FIG. 5, waveforms of the input voltage Vin, the clock CK, and the output voltage Vout, respectively, are shown. First, at the clock CK1 point 510, the input voltage Vin is high. Therefore, the output voltage Vout at the clock CK1 point 510 also shows HIGH. The output voltage Vout maintains this output voltage value until the input voltage Vin changes at the input of the next clock. At the clock CK2 point 520, the input voltage Vin is low. Therefore, the output voltage Vout at the clock CK2 point 520 also indicates a low level.

At another clock CK3 point 530, the input voltage Vin is at HIGH. The output voltage Vout at this time is high. At the next clock CK4 point 540, the input voltage Vin remains unchanged and the HIGH value at the previous clock remains unchanged. Therefore, the output voltage value maintains this value until the input voltage (Vin) changes at the input of the next clock. Thereafter, at the clock CK5 point 550, the input voltage Vin indicates a low level. The output voltage Vout at the point CK5 point 550, which has a change in the input voltage Vin, also indicates a low level.

The circuit that determines the output in accordance with input conditions given from outside is called a flip-flop. Once it is determined to be in a stable state by external input once, the circuit can maintain (remember) its stable state until a new input condition is given.

According to the embodiments of the present invention, a low-power flip-flop circuit for high-speed data processing is provided with a master using a charge-driven latch consuming low power and a slave using a dynamic current mode latch, It is possible to output an output voltage of the same pattern as that of the clock signal, and the current can flow only during the half period of the clock, thereby reducing power consumption.

The apparatus described above may be implemented as a hardware component, a software component, and / or a combination of hardware components and software components. For example, the apparatus and components described in the embodiments may be implemented within a computer system, such as, for example, a processor, a controller, an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable array (FPA) A programmable logic unit (PLU), a microprocessor, or any other device capable of executing and responding to instructions. The processing device may execute an operating system (OS) and one or more software applications running on the operating system. The processing device may also access, store, manipulate, process, and generate data in response to execution of the software. For ease of understanding, the processing apparatus may be described as being used singly, but those skilled in the art will recognize that the processing apparatus may have a plurality of processing elements and / As shown in FIG. For example, the processing unit may comprise a plurality of processors or one processor and one controller. Other processing configurations are also possible, such as a parallel processor.

The software may include a computer program, code, instructions, or a combination of one or more of the foregoing, and may be configured to configure the processing device to operate as desired or to process it collectively or collectively Device can be commanded. The software and / or data may be in the form of any type of machine, component, physical device, virtual equipment, computer storage media, or device , Or may be permanently or temporarily embodied in a transmitted signal wave. The software may be distributed over a networked computer system and stored or executed in a distributed manner. The software and data may be stored on one or more computer readable recording media.

The method according to an embodiment may be implemented in the form of a program command that can be executed through various computer means and recorded in a computer-readable medium. The computer-readable medium may include program instructions, data files, data structures, and the like, alone or in combination. The program instructions to be recorded on the medium may be those specially designed and configured for the embodiments or may be available to those skilled in the art of computer software. Examples of computer-readable media include magnetic media such as hard disks, floppy disks and magnetic tape; optical media such as CD-ROMs and DVDs; magnetic media such as floppy disks; Magneto-optical media, and hardware devices specifically configured to store and execute program instructions such as ROM, RAM, flash memory, and the like. Examples of program instructions include machine language code such as those produced by a compiler, as well as high-level language code that can be executed by a computer using an interpreter or the like. The hardware devices described above may be configured to operate as one or more software modules to perform the operations of the embodiments, and vice versa.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. For example, it is to be understood that the techniques described may be performed in a different order than the described methods, and / or that components of the described systems, structures, devices, circuits, Lt; / RTI > or equivalents, even if it is replaced or replaced.

Therefore, other implementations, other embodiments, and equivalents to the claims are also within the scope of the following claims.

Claims (5)

delete delete delete Performing a latch operation by charging a capacitance using a difference of an input voltage through a charge driving system master consuming low power;
Transferring an output voltage of the master to an input voltage of a slave using a dynamic current mode latch; And
The slave receives the input voltage and outputs an output voltage having the same pattern as the input voltage pattern without any additional circuit
/ RTI > 5. The method of claim 4,
Wherein the slave receives the input voltage and outputs an output voltage having the same pattern as that of the input voltage without any additional circuit, when the NRZ pattern is applied to the input voltage, the same NRZ pattern is output,
The flip-flop can reduce power consumption by flowing current only during a half-period of the clock
Low power flip flop operating method.

Images