KR970003222A - Self-Timed Logic Combination Circuit - Google Patents
Self-Timed Logic Combination Circuit Download PDFInfo
- Publication number
- KR970003222A KR970003222A KR1019950017092A KR19950017092A KR970003222A KR 970003222 A KR970003222 A KR 970003222A KR 1019950017092 A KR1019950017092 A KR 1019950017092A KR 19950017092 A KR19950017092 A KR 19950017092A KR 970003222 A KR970003222 A KR 970003222A
- Authority
- KR
- South Korea
- Prior art keywords
- self
- timed
- signal
- logic combination
- combination circuit
- Prior art date
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- Manipulation Of Pulses (AREA)
- Logic Circuits (AREA)
Abstract
본 발명의 셀프 타임드에 의한 논리조합회로는 하나의 래치회로를 상기 셀프 타임드 파형발생부의 입력단에 접속하여 논리조합된 신호가 안정되었을때 외부로 출력하게 함으로써, 레이아웃을 간단하며 전력소모를 감소할 수 있는 잇점을 제공한다. 또, 글리치 발생의 위험이 있는 모든 회로 설계에 적용 가능하며 전달 지연으로 인한 레이스(race) 문제나 다이나믹 해자드(dynamic hazard)를 제거할 수 있는 장점이 있다.In the self-timed logic combination circuit of the present invention, one latch circuit is connected to the input terminal of the self-timed waveform generator to output to the outside when the logic-combined signal is stabilized, thereby simplifying the layout and reducing power consumption. Provides benefits It is also applicable to any circuit design that is at risk of glitches and can eliminate race problems or dynamic hazards caused by propagation delays.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.
제2도는 본 발명의 실시예에 따른 셀프 타임드에 의한 논리회로의 블럭도.2 is a block diagram of a self-timed logic circuit in accordance with an embodiment of the present invention.
Claims (1)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019950017092A KR970003222A (en) | 1995-06-23 | 1995-06-23 | Self-Timed Logic Combination Circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019950017092A KR970003222A (en) | 1995-06-23 | 1995-06-23 | Self-Timed Logic Combination Circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
KR970003222A true KR970003222A (en) | 1997-01-28 |
Family
ID=66524632
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019950017092A KR970003222A (en) | 1995-06-23 | 1995-06-23 | Self-Timed Logic Combination Circuit |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR970003222A (en) |
-
1995
- 1995-06-23 KR KR1019950017092A patent/KR970003222A/en not_active Application Discontinuation
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
WITN | Withdrawal due to no request for examination |