TW354395B - A bus interface synchronous system for synchronously system clock and the inner clock of a central processing unit, comprising: - Google Patents

A bus interface synchronous system for synchronously system clock and the inner clock of a central processing unit, comprising:

Info

Publication number
TW354395B
TW354395B TW084105329A TW84105329A TW354395B TW 354395 B TW354395 B TW 354395B TW 084105329 A TW084105329 A TW 084105329A TW 84105329 A TW84105329 A TW 84105329A TW 354395 B TW354395 B TW 354395B
Authority
TW
Taiwan
Prior art keywords
clock
processing unit
central processing
synchronous
bus interface
Prior art date
Application number
TW084105329A
Other languages
Chinese (zh)
Inventor
Ya-Nan Mo
Shi-Jung Huang
Original Assignee
United Microelectronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by United Microelectronics Corp filed Critical United Microelectronics Corp
Priority to TW084105329A priority Critical patent/TW354395B/en
Application granted granted Critical
Publication of TW354395B publication Critical patent/TW354395B/en

Links

Landscapes

  • Information Transfer Systems (AREA)

Abstract

A bus interface synchronous system for synchronously system clock and the inner clock of a central processing unit, comprising: a synchronous device for inputting an input signal synchronous with system clock and the inner clock signal of the central processing unit, and converting the input signal synchronous to the system clock to a first signal output; a logic processing device for inputting the signal synchronous to the inner clock of the central processing unit and outputted from the synchronous device, and inputting signal synchronous to the inner clock of other central processing unit for performing logic processing, and the inner clock of the central processing unit is M times or N x 5 times of the system clocking signal, M and N are integer.
TW084105329A 1995-05-26 1995-05-26 A bus interface synchronous system for synchronously system clock and the inner clock of a central processing unit, comprising: TW354395B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW084105329A TW354395B (en) 1995-05-26 1995-05-26 A bus interface synchronous system for synchronously system clock and the inner clock of a central processing unit, comprising:

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW084105329A TW354395B (en) 1995-05-26 1995-05-26 A bus interface synchronous system for synchronously system clock and the inner clock of a central processing unit, comprising:

Publications (1)

Publication Number Publication Date
TW354395B true TW354395B (en) 1999-03-11

Family

ID=57940201

Family Applications (1)

Application Number Title Priority Date Filing Date
TW084105329A TW354395B (en) 1995-05-26 1995-05-26 A bus interface synchronous system for synchronously system clock and the inner clock of a central processing unit, comprising:

Country Status (1)

Country Link
TW (1) TW354395B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6904536B2 (en) 2000-06-29 2005-06-07 Kabushiki Kaisha Toshiba Semiconductor circuit and functional block including synchronizing circuit for determining operation timing

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6904536B2 (en) 2000-06-29 2005-06-07 Kabushiki Kaisha Toshiba Semiconductor circuit and functional block including synchronizing circuit for determining operation timing

Similar Documents

Publication Publication Date Title
TW278152B (en) A design method of clock generating circuit and pll circuit and semi-conductor device combined with clock generating circuit
TW347639B (en) System and method for processing video data
TW364076B (en) Apparatus and method for generating a phase-controlled clock signal
TW353176B (en) A semiconductor device capable of holding signals independent of the pulse width of an external clock and a computer system including the semiconductor
EP0292099A3 (en) Clock scheme for vlsi systems
TW359823B (en) Clocking scheme
ATE322774T1 (en) SYNCHRONOUS DIGITAL TRANSMISSION SYSTEM
TW354395B (en) A bus interface synchronous system for synchronously system clock and the inner clock of a central processing unit, comprising:
TW342558B (en) Low power oscillator
GB9605299D0 (en) Methods and apparatus for synchronizing a clock
ES2004148A6 (en) LOOK AHEAD TERMINAL COUNTER and method for generating a terminal count output signal.
SE9501608L (en) Delay clock and data generator
TW260845B (en) Synchronous counter and carry propagation method thereof
ATE205316T1 (en) DEVICE FOR HIERARCHICALLY CONNECTING A PLURALITY OF FUNCTIONAL UNITS IN A PROCESSOR
JPS63110840A (en) Synchronization detection circuit
TW371344B (en) Circuit for generating internal column address suitable for burst mode
TW251397B (en) Phase comparator
JPS57125425A (en) System for information transmission
JPS5563446A (en) Clock control system in board inspection
TW342501B (en) Data input circuit including echo clock generator
KR960009398A (en) Synchronous Clock Generation Circuit
KR970055611A (en) Audio Encoder Using Parallel Digital Signal Processor
KR970049270A (en) Interface device for switching between synchronous clock sources
KR970056528A (en) Analog Bus / I ^ 2C Bus Protocol Converters
JPS6413615A (en) Input interface for electronic controller

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees