KR100363411B1 - Channel selection logic circuit on group trunk line - Google Patents

Abstract

PURPOSE: A channel selection logic circuit on a group trunk line is provided to select an optional channel from a trunk line according to channel selection information and make latch time of the data received to a BCH(Bose Chaudhuri Hocquenghem) CODEC synchronized. CONSTITUTION: A channel selection register(12) receives and stores channel information for selecting from a control device. A counter(10) counts reference clock and frame synchronous signal and then generates a BCH CODEC transmission clock and a delay clock signal. A latch clock generating unit(14) generates a clock signal for latching BCH coding data corresponding to channel selection information from a group trunk line by comparing channel selection information outputted from the channel selection register and the counter with the delay clock signal. A BCH CODEC(18) latches and stores BCH code data of the corresponding channel from the group trunk line by a latch clock outputted from the latch clock generating unit(14) and thereafter outputs BCH coding data latched by BCH CODEC transmission and reception clock outputted from the counter(10).

Description

Channel selection logic circuit on group line

The present invention relates to an X.P.S. of an electronic exchange system, and more particularly, to a logic circuit for selecting an arbitrary channel from a group trunk according to channel selection information.

XPS stands for X.25 Protocol Supervisor. XPS is a device for extracting and observing X.25 data from a line that is encoded with BCH code to X.25 data (31, 21) to improve the performance against errors. The group trunk is a multiplexed trunk in which 32 channels (CHANNEL) of 32 Kbps each are multiplexed. The BCH-coated X.25 data on the interstellar group can occupy one channel and have a transmission rate of 32 Kbps, and can occupy any two channels and can achieve 64 Kbps. This will be described with reference to FIG. 1.

FIG. 1 shows a channel state diagram of an inter-group constellation to explain a process in which BCH-coded X.25 data is transmitted through an arbitrary channel in the inter-group constellation. In FIG. 1, (a) shows BCH-coded X.25 data, and (b) shows channel occupancy status when the BCH-coded X.25 data is transmitted at 32 Kbps by occupying one channel on the trunk line. It is seen. On the other hand, the BCH coding X.25 data and the channel occupancy state in the case of transmission at 64 Kbps by occupying any two channels in the intergroup configuration are shown in (c) and (d), respectively. That is, when transmitting BCH-coded X.25 data at 64 Kbps as shown in (d) of FIG. 1, data is alternately loaded on two arbitrary channels. If you want to get 64Kbps transmission rate between the group lines you want to observe with XPS, you have to occupy two channels because the rate per channel is 32Kbps. The two channels occupied at this time may come from any of the 32 channels. The BCH codec used to decode the BCH coded data carried on the group lines in the XPS uses a clock of 64KHz as the reception clock. Therefore, in order for the BCH codec to decode data transmitted by occupying any two channels within the group line, the data should be supplied to the reception data input pin in synchronization with the latching time of the 64 KHz reception clock.

Accordingly, an object of the present invention is to provide a logic circuit for synchronizing a data latch time of a clock received by a BCH codec by selecting an arbitrary channel from a group line according to channel selection information.

In order to achieve the above object, the present invention provides channel selection information storage means for receiving and storing channel information to be selected from the control means, and divides a reference clock and a frame synchronization signal to generate a BCH codec transmission / reception clock and a delay clock signal. A latch clock generating means for generating a clock for latching the BCH coding data corresponding to the channel selection information from the group line by comparing the channel selection information and the delay clock signal outputted from the channel information storing means and the distributing means, respectively; And latching and storing the BCH coding data of the corresponding channel from the trunk line by the latch clock outputted from the latch clock generating means, and then outputting the BCH coding data latched by the BCH codec transmission / reception clock outputted from the division means. Characterized in that the data storage means.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Also, many specific details, such as the specific process flows set forth in the following description and the accompanying drawings, are presented to provide a more general understanding of the invention, and it is common knowledge in the art that the invention may be practiced without these specific details. It will be obvious to those who have. And a detailed description of known functions and configurations that may unnecessarily obscure the subject matter of the present invention will be omitted.

2 is a block diagram of the XPS according to the present invention, and includes a divider 10, a channel select register 12, a latch clock generator 14, a buffer 16, and a BCH codec 18. FIG. . In FIG. 2, the channel select register 12 is controlled by a controller (not shown) and temporarily stores the channel number to be observed. At this time, the channel selection register 12 is composed of two equivalent registers (8 bits), each storing one channel number to be observed among 32 channels. That is, only the binary value stored in 5 bits represents the channel number to be selected. The reason for having these two registers is for a channel being transmitted at 64 Kbps. Since it is transmitted by occupying two group trunk channels, record each channel number in registers 1 and 2. When transmitting at 32 Kbps, record the same channel number in registers 1 and 2. Hereinafter, the channel number registers 1 and 2 will be referred to as channel select registers 1 and 2. On the other hand, the latch clock generation unit 14 compares the channel selection information (ie, the channel selection register value) output from the channel selection register 12 with the delayed clock (hereinafter referred to as DCLK). 1 ". The enable signal is gated with a 1.024 MHz clock output from the divider 10 and used as a latch clock LCLK of the buffer unit 16. The buffer unit 16 latches the BCH coding data selected by the channel selection registers 1 and 2 at the rising edges of the latch clocks LCLK1 and LCLK2, and then performs the BCH coding by the BCH codec transmission / reception CLK outputted from the divider 10. Output the data to the BCH codec.

3 is a detailed circuit diagram of the latch clock generator 14 in FIG. In FIG. 3, the latch clock generator 14 stores the channel selection register 1 (12) (the channel selection register 2 is not shown) for temporarily storing one channel selection number, and the delay divided by the divider 10. In FIG. An adder 22-30 that adds clocks D32, D64, Dl28, D256, and D512 KHz to the binary value of the channel select register 1 12, and an output of the adder 22-30, A NAND gate 32 generating EN1), and an AND gate 34 generating a first latch clock LCLK1 by gating 1.024 MHz output from the output terminal of the NAND gate 32 and the divider 10. . Hereinafter, the operation of the latch clock generator 14 will be described with reference to the timing diagram of FIG. 5.

5 illustrates an internal timing diagram of the latch clock generator 14. In FIG. 5, Sync represents a frame synchronization signal input to the divider 10, and 1024 MHz, 512 KHz, 256 KHz, 128 KHz, 64 KHz, and 32 KHz represent clocks divided from a reference clock (CLK), and D512 KHz, D256 KHz, D128 KHz, D64KHz and D32KHz represent the delay clock DCLK, respectively. First, the latch clock generation unit 14 compares the value of the channel selection register 1 (12) with the delay clock DCLK and outputs the enable signal EN1 to the "high" level when the logic levels are the same. The enable signal EN1 and the 1024 MHz clock are gated at the AND gate 34 and used as the latch clock LCLK1 of the buffer 16. If you want to extract the X.25 data transmitted by occupying channels 1 and 4 of the group trunk, set the values of the channel selection registers 1 and 2 to "00001" and "00100", respectively. At this time, as shown in FIG. 5, the latch clocks LCLK1 and LCLK2 are generated when the delay clocks DCLK and the values of the channel select registers 1 and 2 coincide.

4 shows a detailed configuration diagram of the buffer 16 during the second diagram, wherein the buffer 16 includes three D flip-flops 40, 42, and 44 and a MUX 46. The input terminal D and the clock terminal CLK of the D flip-flop 40 and 42 are connected to the group trunk and the latch clock generator 14, respectively, and the output terminal Q is connected to the P1 and P2 terminals of the MUX 46, respectively. The BCH coded data 1, 2 (hereinafter referred to as data 1, 2) latched by LCLK1 and LCLK2 are outputted to the MUX 46. On the other hand, the input terminal and the clock terminal of the D flip-flop 44 are connected to the transmission and reception CLK outputted from the power supply voltage Vcc and the divider 10, respectively, and the output terminal Q is the select of the MUX 46 (hereinafter referred to as SEL). It is connected to the terminal. At this time, the inverter 48 is connected between the clock stage of the D flip-flop 44 and the divider 10 so that the inverted transmit / receive CLK is input to the clock stage of the D flip-flop 44. On the other hand, the latch clock LCK1 output from the latch clock generator 14 is connected to the reset terminal of the D flip-flop 44 through the inverter 46, so that the D flip-flop 44 is initialized at the falling edge of the latch clock LCLK1. . The MUX 46 selects and outputs data 1 and 2 output from the D flip flops 40 and 42 according to the logic level output from the output terminal Q of the D flip flop 44. At this time, the data output from the MUX 46 is specified as the reception data. The received data output from the buffer 16 is latched into the BCH codec 18 with reference to FIG. 6 showing a timing diagram between the latch clocks LCLK1 and LCLK2 and the BCH codec 18 transmitting and receiving CLK according to the present invention. The process of becoming will be described.

6 shows a timing diagram between the latch clocks LCLK1 and LCLK2 and the BCH codec 18 transmit / receive clock according to the present invention. In Figure 6 (a), the transmit and receive CLK represents the BCH codec 18 transmit and receive clock of 64 KHz, and (b) and (c) indicate the latch clock LCLK1 and LCLK2 timing changes for the transmit and receive CLK. Two embodiments are shown. First, data 1 selected by the channel select register 1 is latched to the D flip-flop 40 at the rising edge of the latch clock LCLK1, and the D flip-flop 44 is initialized at the falling edge of the latch clock LCLK1. After the D flip-flop 44 is initialized, data 1 is latched into the BCH codec 18 at the rising edge of the BCH codec send and receive CLK, and the output of the D flip-flop 44 is "high" at the falling edge. Data 2 is loaded on the reception data. Thereafter, the data 2 is latched into the BCH codec 18 by the BCH codec transmission and reception CLK. That is, when the BCH codec transmit / receive CLK has the timing as shown in FIG. 6, there are two cases of receiving data between the latch clocks LCLK1 and LCLK2 and the BCH codec transmit / receive CLK as shown in (b) and (c). Can be safely latched into the BCH codec 18.

As described above, the present invention has the advantage that the channel data can be extracted from the group edges according to the channel selection information and safely latched into the BCH codec.

1 is a channel state diagram on a trunk line for explaining a process in which BCH-coded X.25 data is transmitted through an arbitrary channel on the trunk line.

2 is a block diagram of an XPS according to the present invention.

3 is a detailed configuration diagram of the latch clock generator 14 in FIG.

4 is a detailed configuration diagram of the buffer 16 in FIG.

5 is an internal timing diagram of the latch clock generator 14 according to the present invention.

6 is a timing diagram between the latch clocks LCLK1, LCLK2 and BCH codec 18 transmission and reception clocks according to the present invention.

Claims (7)

In the channel selection logic circuit on the group line, Channel selection information storage means for receiving and storing channel information to be selected from the control means; Division means for dividing a reference clock and a frame synchronization signal to generate a BCH codec transmission / reception clock and a delay clock signal; Latch clock generating means for generating a clock for latching the BCH coding data corresponding to the channel selection information from the group trunk by comparing the channel selection information output from the channel information storing means and the dividing means with the delay clock signal; BCH coding data storage for outputting the latched BCH coding data by the BCH codec transmission / reception clock outputted from the division means after latching the BCH coding data of the corresponding channel from the group edge by the latch clock outputted from the latch clock generating means. And a channel selection logic circuit on the main line. The method of claim 1, wherein the channel selection information storage means is: And channel selection information for selecting only two channels among the channels on the group trunk in two 8-bit registers. 3. The channel selection logic circuit of claim 2, wherein the 8-bit register uses only 5 bits to store channel selection information. The method of claim 3, wherein the latch clock generating means: An adder for adding bit information output from the channel selection bit of the 8-bit register and delay clock signal output from the frequency division means; A NAND gate generating an enable signal by gating a channel selection bit added to the delay clock signal; And an AND gate generating a latch clock by gating a clock divided by the enable signal and a reference clock. 5. The channel selection logic circuit of claim 4, wherein the latch clock generating means is connected to the two 8-bit registers, respectively. The method of claim 5, wherein the BCH coding data storage means: First and second latch means for latching the BCH coding data from the group line according to the logic level of the latch clock output from the latch clock generating means, respectively; Data selection means for selectively outputting BCH coding data output from the first and second latch means according to a logic level of a selection signal; And a selection signal generating means for generating the selection signal by clocking a power supply voltage to a latch clock output from the latch clock generating means. 7. The channel selection logic circuit of claim 6, wherein the selection signal generating means is reset by a BCH codec transmission and reception clock outputted from the division means.