KR970002708B1 - Virtual container signal transform circuit to multiplexing tu11 and tu12 - Google Patents

Abstract

A virtual container signal conversion circuit where convert the VC12 signal to VC11 signal and use to the TU11 signal multiple type, because of generating continuously the timing that is appended to the fixed inserting signal and the VC11 signal referring to the V5 timing of the virtual container(VC11) signal.

Description

Virtual Container (VC11) Signal Conversion Circuit for Multiplexing on Tee, TU 11 and Tee, TU 12

1 is an overall configuration diagram of the invention

2 is a block diagram of the VC12 clock generator 12

3 is a diagram illustrating conversion of a VC11 signal.

4 is a VC11 signal timing diagram

5 is a VC12 signal timing diagram

* Description of the main parts of the drawings

100: VC11 signal serial / parallel converter 200: write address generator

300: 16-stage buffer 400: VC12 clock generator

500: read address generator 600: 2: 1 multiplexer

700: Retimer

The present invention relates to a signal conversion circuit for performing a conversion function from a VC11 signal to a VC12 signal for multiplexing a TU12 signal after inserting a DS1 signal having a 1.544 Mb / s transmission rate into a VC11 virtual container in a synchronous multiplexed structure. will be.

1.544 Mb / s DS1 signal is based on mapping to VC11 signal and transmitted multiplexed to TU11 or TU12 signal. When multiplexed to TU12 signal, it is fixedly inserted into VC11 signal to compensate for the speed difference between VC11 signal and TU12 signal. By adding the signal, a signal having a speed of VC 12 is formed and multiplexed to TU12.

The present invention continuously forms the timing at which the VC11 signal is inserted and the timing at which the fixed insertion signal is added to the VC12 signal to be formed on the basis of the V5 timing of the periodically supplied VC11 signal, and then converts the VC11 signal from the VC11 signal to the VC12 signal. It is an object of the present invention to provide a signal conversion circuit that can be applied to multiple systems to TU11.

In order to achieve the above object, the present invention provides a VC11 signal serial / parallel conversion means for receiving a VC11 serial data, a transmission 1.664M clock and a transmission 208K clock to perform a serial / parallel conversion function, and a transmission signal 208K based on a reset signal. Write address generation means for generating a write address using a clock, and VC11 parallel data supplied from the transmission V5 and VC11 signal serial / parallel conversion means are sequentially written to an internal buffer in accordance with the write address generated by the write address generation means. VC12 clock and fixed signal insertion using the BV5 signal and the buffer to output BC12 formation data and V5 timing signal, and the BV5 signal read out from the buffer and externally supplied reset, multipath selection signal and transmit capping 280K clock. VC12 clock generating means for generating a signal, and multiplexing the VC12 clock or transmit capping 208K clock Read address generation means for selecting according to the path selection signal and generating a read address used to read data from the buffer based on an externally supplied reset; and a fixed insertion signal and a parallel VC12 type data read from the buffer. Multi-means to form VC12 parallel data by using the V5 timing signal supplied from the buffer and VC12 parallel data supplied from the multiple means to retime the transmission 864K clock supplied externally to generate transmission V5 and transmission VC12 parallel data. It has a means for making it.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;

1 is an overall configuration diagram of the present invention.

As shown in the figure, the present invention provides a VC11 signal serial for performing a serial / parallel conversion function by receiving a VC11 serial data 2 supplied from an external circuit, a transmission 1.664M clock 3 and a transmission 208K clock 4. Write address generator 200 for generating a write address 9 using the 208K clock 4 based on the external / parallel converter 100 and an externally supplied reset 7 signal, and an externally supplied transmission. The VC11 parallel data 8 supplied from the V5 (1) and the VC11 signal serial / parallel converter 100 are sequentially written to the internal buffer in accordance with the write address 9 generated by the write address generator 200, and the BV5 signal And a 16-stage buffer 300 for outputting the VC12 type data and the V5 timing signal, a BV5 signal read out from the 16-stage buffer 300, an externally reset (7), and a multi-path selection signal (61). And transmit gapping using the 280K clock (5) The VC12 clock generator 400 generating the VC12 clock 11 and the fixed signal insertion signal 12, the VC12 clock 11 generated by the VC12 clock generator 400, or a transmission gapping 208K clock 60 supplied from the outside. Is selected according to the multi-path selection signal 61 and a read address generator 500 for generating a read address 13 used for reading data from the 16-stage buffer 300 based on the reset 7 supplied from the outside. ), The fixed insertion signal 15 supplied from the external fixed value (“0” or “1”) and the parallel VC12 type data 14 read from the 16-stage buffer 300 are transferred from the VC clock generator 400. It is a 2: 1 multiplexer 600 and a V5 timing signal 16 supplied from the 16-stage buffer 300 that forms the VC12 parallel data 17 by using the generated fixed signal insert 12. Re-time the VC12 parallel data 17 supplied from the medium-terminal 600 to the transmission 864K clock 65 supplied externally. And a retimer 700 for generating V5 18 and transmitting VC12 parallel data 19.

FIG. 2 is a detailed configuration diagram of the VC12 clock generator 400. As shown in the drawing, the 36 division counter 420 and the 36 division frequency counter 420 receive the inverted transmission gapping 280K clock. A counter reset generator 430 that receives a recognition signal and receives a BV5 signal and outputs a reset signal, a 161 counter 450 that receives the inverted transmission gapping 280K clock and receives a counter reset signal, and the 161 counter Negative-OR gate 470 outputting a fixed signal insertion control signal by performing a negative logic multiplication on a part of the output of 450, and receiving and applying a counter reset signal and a fixed signal insertion control signal to the 161 counter 450 A logical AND gate 400 for providing a reset signal, a negative AND gate 460 for negatively performing a partial output signal of the 161 counter 450, and outputting a VC12 clock formation control signal; A logic gate 180 for generating a VC12 clock by receiving a VC12 clocking control signal and a transmission gapping 280K clock, and generating a VC12 clock, and inputs the VC12 clocking control signal to a data input terminal and a transmission gapping 280K clock to a clock input terminal. A 2: 1 selector 910 that receives the received D flip-flop 490, the output of the D flip-flop 490, and a power supply voltage signal, and selectively outputs the signal as a fixed signal insertion signal under the control of the multi-path selection signal 61. ).

3 to 5 are timing diagrams according to the present invention, which will be described in detail with reference to the accompanying drawings.

As shown in FIG. 3, the present invention mainly forms a converted VC12 signal having a transmission rate of VC12 based on the VC11 signal based on V5 bytes. In the circuit of the present invention, a 1.544 Mb / s DS1 signal is externally provided. As shown in FIG. 4, it is assumed that the VC11 serial data 2 are mapped and supplied based on the transmission 1.664M clock 3 as a reference. The VC11 signal serial-to-parallel converter 100 maintains the phase as described and stores the supplied VC11 serial data 2 in an eight-stage register with a transmit 1.664M clock and then parallel as the transmit 208K clock shown in FIG. By latching the data, the VC11 parallel data 8 bus is supplied to the 16-stage buffer 300. The VC11 parallel data is written to the register of each byte unit of the 16-stage buffer 600 designated by the write address 9 bus generated by the write address generator 200 based on the transmission 208K clock 4.

The transmission V5 (1) supplied from an external circuit together with the VC11 parallel data 8 bus is stored in a bit unit register designated by a write address to maintain the phase relationship with the VC11 parallel data 8. The circuit is basically configured to generate time slots for the VC11 data in the transformed VC12 signal and timeslots for the fixed insert signal to form the converted VC12 signal in FIG. 3, which is the transmit gapping 280K clock after the circuit is powered up. Based on (5), the VC12 clock 11 generated by the VC12 clock generator 400 is supplied to the read address generator 500 so as to have a read address having a value that is 8 bytes different from the value of any write address. 13) The bus is generated and started by being provided to the 16-stage buffer 300. When power is applied to the circuit, a read address is generated as described above, and the BV5 10 is provided from the 16-stage buffer 300 to the VC12 clock generator 400 with the same phase as the timing shown in FIG.

BV5 10 is generated in a 2KHZ period and this signal is supplied to the counter reset generator 430 of FIG. The counter reset generator 430 starts its operation by the reset 7 and transmits to maintain the phase relationship between the VC12 clock 11 and the fixed signal insertion 12 in FIG. 5 when the first BV5 10 is supplied. It is retimed by the gapping 280K clock 5 and then supplied to the 36 frequency counter 420. The 36-division counter 420 generates a 36-division acknowledgment signal 45 every 2KHZ cycles, i.e., every 125 μsec based on the V5 data, feeds it to the counter reset generator 430, and feeds back the 36-division counter. Initializing 420 and if the next BV5 10 is supplied to the counter reset generator 430 causes the same process to be performed repeatedly. As a result, the counter reset generator 430 generates a 36 counter reset 46 signal at a period of 2KHZ, which is supplied to the 2-input AND gate 440 and the AND gate of the AND gate. The output (6) loads the initial value of the counter 450 as shown in FIG. 2 and (6) the outputs of the counter 450 are combined as in the 3-input NAND gate 470. (6) By driving the counter 450, the output of the two-input NAND gate 460 (V480) and (490) has a VC12 clock (11) and a fixed signal insertion (12) with the phase shown in FIG. The fixed signal insertion 12 is selected by the multipath selection 61 signal according to the multipath.

The VC12 clock generated in this manner in the VC12 clock generator 400 has an average frequency of 208KHZ, and the counter in the read address generator 500 generates a read address (B) bus by driving a counter to generate a parallel VC12 formed data 14 bus and V5 timing. (16) is read from the 16-stage buffer 300. The 2: 1 multiplexer 600 multiplexes the parallel VC12 formation data 14 bus and the fixed insertion signal 15 based on the fixed signal insertion 12 and the VC12 parallel data 17 having the phase shown in FIG. It will generate a bus. The retiming machine 700 performs simple retiming based on the transmission 864K clock 6 and the transmission V5 (18) is V5 in the transmission VC12 parallel data 19 in the multiplexing to the TU12 from outside the circuit related to the present invention. Maintain a location where data can be known and be provided to external circuits. When the VC11 signal is to be multiplexed over the TU11 path, the fixed signal insert 12 is selected by the multipath selection 61 and the read address generator 500 selects the transmission gapping 208K clock 60 to counter the counter. By generating the read address 13 for the TU11, the re-timer 700 bypasses the 2: 1 multiplexer 600 as the actual VC11 data using the parallel VC12 formation data, which is the output of the 16-stage buffer 300, as the actual VC11 data. Is supplied.

Accordingly, the present invention, which is configured and operated as described above, has two multipaths of VC11-TU11 and VC11-VC12-TU12 for DS1 signals having a 1.544 Mb / s transmission rate in a synchronous multi-structure. In order to multiply the signal into a TU12 signal after converting it to a VC12 signal, a conversion is required.

Claims (2)

VC11 signal serial / parallel conversion means (100) for receiving a VC11 serial data (2), a transmission 1.664M clock (3), and a transmission 208KV clock (4) supplied from an external circuit and performing a serial / parallel conversion function; Write address generation means 200 for generating a write address 9 by using the transmission 208K clock 4 on the basis of the reset 7 signal supplied from < RTI ID = 0.0 >, < / RTI > The VC11 parallel data 8 supplied from the serial / parallel conversion means 100 is sequentially written to the internal buffer in accordance with the write address 9 generated from the write address generation means 200, and the BV5 signal and the parallel VC12 formed data are sequentially written. And a buffer 300 for outputting a V5 timing signal, a BV5 signal read from the buffer 300, an externally reset (7), a multipath selection signal 61, and a transmission gapping 280K clock (5). The VC12 clock 11 and the fixed signal insertion signal 12 VC12 clock generating means 400 and VC12 clock 11 generated by the VC12 clock generating means 400 or a transmission gapping 208K clock 60 supplied externally to the multipath selection signal 61. A read address generating means 500 for generating a read address 13 used for reading data from the buffer 300 based on a reset 7 supplied from an external source and a fixed value supplied from the outside. Multiple forming of the VC12 parallel data 17 using the fixed signal insertion 12 generated by the VC12 clock generating means 400 on the parallel VC12 formation data 14 read from the fixed insertion signal 15 and the buffer 300. Retiming means (600), V5 timing signal (16) supplied from the buffer (300) and VC12 parallel data (17) supplied from the multiple means (600) with an externally supplied transmission 864K clock (6). Generating transmit V5 18 and transmit VC12 parallel data 18 And a retiming means (700). A virtual container (VC11) signal converting circuit comprising: a retiming means; The VC12 clock generating unit 400 receives the 36-division counter 420 and the 36-division acknowledgment signal from the 36-division counter 420 to invert the transmission gapping 280K clock. A counter reset generator 430 for receiving the output signal and outputting a reset signal, the inverted transmission gapping 280K clock input, and a part of the output of the 161 counter 450 and the 161 counter 450 receiving the counter reset signal are negated. A first negative AND gate 470 for performing an AND operation to output a fixed signal insertion control signal, and receiving the counter reset signal and the fixed signal insertion control signal to perform an AND operation to provide a reset signal to the 161 counter 450. A second negative AND gate 460 for performing a negative AND operation on the first logical gate 440, a partial output signal of the 161 counter 450, and outputting a VC12 clock forming control signal, and the VC12 clock forming Control signal and A second logical gate 180 that receives a transmission gapping 280K clock and performs a logical multiplication to generate a VC12 clock, and a D flip-flop that receives a transmission gapping 280K clock as a data input terminal and a VC12 clock formation control signal as a data input terminal. 490 and a 2: 1 selector 910 which receives the output of the D flip-flop 490 and the power supply voltage signal and selectively outputs the fixed signal insertion signal under the control of the multipath selection signal 61. And a virtual container (CV11) signal conversion circuit.