JPH0326107A - Logic circuit - Google Patents

Abstract

PURPOSE:To made the frequency of a clock signal and the frequency of an input/output signal coincident by frequency-dividing an inputted clock signal, driving a logic circuit main body and executing either a processing to converge plural signals or a processing to divide them. CONSTITUTION:When a clock signal CLK1 is inputted to a dynamic frequency- dividing circuit, it is frequency-divided into 1/2 by the dynamic frequency- dividing circuit 1, it is inputted to a multiplexer 2 main body as a clock signal, signals D1 and D2 are fetched by a master.slave flip-flop 10 and a master.slave.master flip-flop 11 in synchronizing to the rise of a signal CLK2, and when the signals CLK2 falls, a signal D2' to latch an input signal D2 is outputted from the master.slave.master flip-flop 11. In such a way, the frequency of the clock signal CLK1 and the bit rate of a signal outputted from the multiplexer 2 main body can be made to coincident.

Description

[Detailed description of the invention]

[Object of the Invention] (Industrial Application Field) The present invention relates to logic circuits such as multiplexers and demultiplexers that bundle or distribute signals. (Conventional technology) In the field of high-speed communications, the technology of bundling and distributing signals is extremely important, and the performance of multiplexers and demultiplexers, which are central to such processing, has an impact on the performance of the entire system. also has a big impact. For example, when performing optical transmission at 1.6 Gbps between Tokyo and Osaka, multiplexers that gradually bundle signals with a transmission rate much lower than 1.6 Gbps and demultiplexers that distribute the signals must be placed in Tokyo and Osaka. Without these multiplexers and demultiplexers, it is impossible to construct a transmission line. By the way, recently, 1. Transmission formats faster than 6Gbps (2.4Gbps in Europe) are being researched. The transmission rate in this case is 9.6G bps
And it's very fast. For this reason, the technology required for multiplexers and demultiplexers is even more sophisticated than before. FIG. 14 is a block diagram showing an example of a multiplexer with a coupling ratio of 2:1 used in such technology.
a mask/slave flip-flop 102 that takes in and outputs the input signal D1 every time the clock signal CLK is supplied, and a master/slave flip-flop 10 that takes in the input signal D2 every time the clock signal CLK is supplied.
A mask/slave/master flip-flop 103 outputs an output shifted by half a cycle with respect to the output of the mask/slave/master flip-flop 103 according to the clock signal CLK. The multiplexer gate 104 selects and outputs one of the following. The master/slave flip-flop 102 is the fifteenth
As shown in the figure, SCFL (S
When the clock signal CLK rises, the input signal D1 is input to the multiplexer gate 104 until the clock signal CLK rises again, using the input signal D1 as the signal D1°. supply to. Further, the master/slave/master flip-flop 103 is a circuit in which a master flip-flop is added at the subsequent stage of the circuit shown in FIG. 15, and takes in and holds the input signal D2 when the clock signal CLK rises. Thereafter, when the clock signal CLK falls, the held input signal D2 is supplied to the multiplexer gate 104 as a signal D2°. The multiplexer gate 104 is a current switch type circuit as shown in FIG. 16, and selects one of the signals DI' and D2° according to the clock signal CLK and outputs it from the output terminal. Next, the operation of this multiplexer 101 will be explained with reference to the timing diagram shown in FIG. First, as shown in FIGS. 17(b) and (C), the input signal D1
, D2 are being supplied, if the clock signal CLK rises as shown in FIG. 17(a),
) as shown in the mask slave flip-flop 102.
The signal D1' obtained by latching the input signal D1 is output from the master flip-flop 103, and when the clock signal CLK falls, the signal obtained by latching the input signal D2 from the master flip-flop 103 is output as shown in FIG. D2' is output. Then, as shown in FIG. 17(f), these signals D1° and D2° are selected and output by the multiplexer gate 104 in synchronization with the rising and falling edges of the clock signal CLK. In this way, in this multiplexer 101, the input signals D1,
D2 is taken in, and the input signals D1 and D2 taken in are alternately selected and outputted in synchronization with the rise and fall of the clock signal CLK. (Problems to be Solved by the Invention) However, the conventional multiplexer 101 described above has the following problems. That is, in such a conventional multiplexer 101, the ratio between the frequency of the clock signal CLK and the bit rate of the signal output from the multiplexer 101 is "
1:2”, but originally these ratios were “1:1”.
”. Therefore, a 172 frequency divider circuit is provided at the clock signal input terminal of the multiplexer 101, and this 1/2 frequency divider circuit is used to divide the clock signal CLK and input it manually to the multiplexer 101. It is conceivable to set the ratio between the frequency of the clock signal CLK and the bit rate of the signal output from the multiplexer 101 to "121". However, a 1/2 frequency divider circuit like this is usually used. For example, a 1/2 frequency divider circuit using a mask/slave flip-flop as shown in FIG. 15 has an operating frequency of only about half of the operating frequency of the multiplexer gate 104 shown in FIG. 1
/2 The multiplexer 10 depends on the operating frequency of the divider circuit.
1 maximum operating frequency is limited. In order to prevent such inconvenience, a 1/2 frequency divider circuit made of a tC element such as a HBT (hetero bibolar transistor), which has a higher operating frequency, is used as a multiplexer.
Although it is conceivable to connect it to the clock input terminal of 01, such a method poses problems in that it becomes difficult to integrate the circuit and the cost increases. In view of the above circumstances, the present invention makes it possible to easily construct a system by matching the frequency of a clock signal and the frequency of an input/output signal with a simple configuration, and is suitable for use in next-generation optical communication technology. transmission rate (9.6Gb
The purpose of the present invention is to provide logic circuits such as multiplexers and demultiplexers that can also cover the following. [Structure of the invention] (Means for solving the problem) In order to achieve the above object, the logic circuit according to the present invention has the following features:
In a logic circuit that performs either convergence processing or division processing of multiple signals, a logic circuit body that performs either convergence processing or division processing of multiple signals, and a logic circuit that performs processing that converges or division processing of multiple signals, and a logic circuit that performs processing that converges or divides multiple signals, and a logic circuit that performs processing that converges or divides multiple signals, and divide the input clock signal. and a dynamic frequency divider circuit that drives the logic circuit main body. (Function) In the above configuration, when a clock signal is manually input, the dynamic frequency dividing circuit divides the clock signal, and the logic circuit main body is driven based on the signal obtained by this frequency dividing operation to generate multiple signals. Either convergence processing or division processing is performed. (Embodiment) FIG. 1 is a block diagram showing an example of a multiplexer to which a first embodiment of the logic circuit according to the present invention is applied. The multiplexer shown in this figure is B F L (Buf'
The clock signal CLKI is divided into 1 by the dynamic frequency divider circuit 1, and a multiplexer main body 2.
72, and the resulting signal CLK2 drives the multiplexer body 1 to take in the input signals D1 and D2, and alternately selects and outputs them. As shown in FIG. 2, the dynamic frequency divider circuit 1 includes an inverter circuit 3 that inverts an input signal, a transfer gate 4 that gates the output of the inverter circuit 3 in accordance with a signal CLKI that is a complementary signal of a clock signal CLKI. A source follower type buffer circuit 5 that transmits the signal that has passed through the transfer gate 4; and a transfer gate that gates the output of the buffer circuit 5 and returns it to the input side of the inverter circuit 3 in accordance with the black signal CLKI. 6. In this case, since the buffer circuit 5 is used for the purpose of stabilizing the operation of the inverter circuit 3, the third
The dynamic frequency divider circuit 1 can be equivalently represented by the circuit shown in the figure. As is clear from this equivalent circuit, as shown in FIG. 4 (Jl) for the transfer gate 6, the clock signal C
When LKI is applied, the output signal of the inverter circuit 3 is inverted, and the inverter circuit 3 outputs a signal CLK2 shown in FIG. 4(b). In this case, the delay time tpd between the rising and falling timings of the clock signal CLKI and the rising and falling timings of the signal output from the inverter circuit 3 is approximately determined by the delay time of the inverter circuit 3, so one operation It can operate faster than a static type frequency divider circuit, which requires 2 tpd. Note that in this dynamic frequency divider circuit 1, there is a cutoff frequency on the low frequency side in order to perform dynamic operation, but the clock signal CLK used in the present invention
Since I is a coherent signal and the field of application of the present invention is high-speed communication technology of about 9.6 Gbps using the clock signal CLK1, the cut-off frequency on the lower frequency side can be ignored in the present invention. The multiplexer body 2 also has a signal C as shown in FIG.
A mask/slave flip-flop 10 that captures and outputs an input signal D1 every time the signal LK2 is supplied; Mask that outputs at a timing shifted by half a cycle ◆
Slave master flip-flop 11 and the signal C
The multiplexer gate 12 selectively takes in and outputs either the output of the master slave flip-flop 10 or the output of the mask slave master flip-flop 11 according to the signal LK2. Then, the input signals D1 and D2 are taken in in synchronization with the rise of the signal CLK2, and the input signals D1 and D2 taken in in synchronization with the rise and fall of the signal CLK2 are alternately output. Next, the operation of this embodiment will be explained with reference to the timing diagram shown in FIG. First, in this multiplexer, as shown in FIG. 5(a), the clock signal CLK is applied to the dynamic frequency divider circuit 1.
When I is input, this dynamic frequency divider circuit 1 divides the frequency into 1/2 to produce the signal C shown in FIG. 5(b).
LK2 is generated and inputted to the multiplexer body 2 as a clock signal. In addition, in parallel with this operation, the input signals D1 and D are sent to the multiplexer body 2 at the timings shown in FIG. 5(c) and (d).
2 is supplied, the signal CLK is output as shown in FIG. 5(b).
These are taken in by the mask slave flip-flop 10 and the mask slave flip-flop 11 in synchronization with the rising edge of 2, and the input signal is input from the mask slave flip-flop 10 as shown in FIG. 5(e). A signal D1° obtained by latching D1 is output, which is selected by the multiplexer gate 12 and output as shown in FIG. 5(g). After this, when the signal CLK2 falls, FIG.

As shown in (), a signal D2' obtained by latching the human input signal D2 is output from the mask-slave-master flip-flop 11, which is selected by the multiplexer gate 12 and output as shown in FIG. 5(g). Thus, in this embodiment, the clock signal CLK
Since the frequency of I is divided by the dynamic frequency dividing circuit 1 and inputted to the multiplexer main body 2, the frequency of the clock signal CLKI can be matched with the bit rate of the signal output from the multiplexer main body 2. , the input signals D1, D.2 can be bundled at high speed without degrading the frequency performance of the multiplexer main body 2. FIG. 6 is a block diagram showing an example of a multiplexer to which the second embodiment of the logic circuit according to the present invention is applied. The multiplexer shown in this figure includes a plurality of multiplexer bodies 15 connected in multiple stages, and these multiplexer bodies 1.
The dynamic frequency divider circuit 1 is connected to the final stage of the clock signal CLK, and takes in the input signals D1 to D8, and also divides these human input signals D1 to D8 according to the clock signal CLK.
are sequentially and cyclically selected and output. The dynamic frequency divider circuit 1 has the same structure as that used in the first embodiment described above, and has a clock signal CLKI.
is input manually, it is divided into 1/2 and the signal CLK is generated.
2 is generated and supplied to the clock input terminal 15c of the final stage multiplexer main body 15. Each multiplexer main body 15 receives a signal CLKn (n is 2, 3
, 4) and outputs the signal CLK (n+1) obtained by this frequency division operation from the clock output terminal 15d, and the clock input terminal 15c. a mask slave flip-flop 17 that captures and outputs the signal input to the first human input terminal 15a every time the signal CLKn is input manually;
Every time the signal CLKn is input to the clock input terminal 15c, the signal input to the second human input terminal 15b is taken in, and the mask/slave flip-flop 1
A mask/slave/master flip-flop 18 whose output is shifted by half a cycle with respect to the output of CLK, and the signal CLK.
The mask slave flip-flop 17 according to n
The multiplexer gate 19 selectively takes in and outputs either the output of the master flip-flop 18 or the output of the master flip-flop 18. Note that in this case, since the clock signal CLKI has already been frequency-divided by the dynamic frequency divider circuit 1, the frequency divider circuit 16
may be of dynamic type or static type. In this multiplexer, each time the clock signal CLKI is manually input, the dynamic frequency divider circuit 1,
The frequency of the clock signal CLKI is sequentially divided by the frequency dividing circuit 16 of the multiplexer main body 15 provided at the final stage and the frequency dividing circuit 16 of the multiplexer main body 15 provided at the middle stage. In addition, in parallel with this operation, the signal CLK2 that can be output from the dynamic frequency divider circuit 1 and the multiplexer body 1 of each stage
The signal CLK output from the frequency dividing circuit 16 provided in
3. Multiplexer body 15 of each stage in synchronization with CLK4
cooperate to take in the input signals D1 to D8, and sequentially cyclically select each of these human input signals D1 to D8 and sequentially output them. In this embodiment, the frequency of the clock signal CLKI is divided by the dynamic frequency divider circuit 1 and is supplied to the last stage multiplexer main body 15, so that the frequency of the clock/i signal CI, Kl and the last stage of the clock signal CLKI are It is possible to match the frequency of the signal output from the multiplexer main body 15 of the stage, and the multiplexer main body 1
input signals D1 to D8 without compromising the frequency performance of 5.
can be bundled at high speed. FIG. 8 is a block diagram showing an example of a demultiplexer to which the third embodiment of the logic circuit according to the present invention is applied. The demultiplexer shown in this figure includes a plurality of demultiplexer bodies 2o connected in multiple stages, and a dynamic frequency divider circuit 1 connected to the first demultiplexer body 20 among these demultiplexer bodies 20, and is synchronized with a clock signal CLKI. Then, the input signal D1 is sequentially divided to generate and output eight output signals. The dynamic frequency divider circuit has the same structure as that used in the first embodiment, and the clock signal CLKI
is input, the frequency is divided by 1/2 and the signal CLK
2 is generated and supplied to the clock input terminal 20c of the first stage demultiplexer body 2o. Each demultiplexer body 2o receives a clock signal CLKn input to a clock input terminal 20c as shown in FIG.
(n is a value of 2, 3, or 4) and divides the signal CL.
K (n+1) is generated and sent to the clock output terminal 20.
a frequency divider circuit 21 that outputs from the clock input terminal 20e, and a mask slave flip-flop that takes in the signal input to the input terminal 20a every time the signal CLKn input to the clock output terminal 20e rises and outputs it from the first output terminal 20e. 22, and every time the signal CLKn input to the clock input terminal 20c falls, the signal input to the human input terminal 20a is taken in, and the signal is shifted by half HM with respect to the output of the mask/slave flip-flop 17 to output a second output. It is equipped with a mask◆slave●master flip-flop 23 that is output from the terminal 2Of. In this case, the frequency dividing circuit 21 may be of a dynamic type or a static type. Next, the operation of this embodiment will be explained with reference to the timing diagram shown in FIG. First, in this demultiplexer, every time the clock signal CLKI is manually input, the frequency of this clock signal CLKI is divided by 1/2 by the dynamic frequency divider circuit 1 to generate a signal CLK2, which is then sent to the first stage demultiplexer. It is supplied to the main body 2o. Then, the signal CLK2 output from the dynamic frequency divider circuit 1 is divided into 1/2 by the frequency divider circuit 21 provided in the first stage demultiplexer body 2o, and is supplied to the next stage demultiplexer body 2o. The frequency is further divided into 1/2 by a frequency dividing circuit 21 provided in the demultiplexer main body 2o of the stage, and this is supplied to the demultiplexer main body 20 of the final stage. In addition, in parallel with this operation, as shown in FIG. 10(b), the signal CLK2 output from the dynamic frequency divider circuit 1 and the frequency divider circuit 21 provided in the demultiplexer body 20 of each stage
The demultiplexer bodies 20 at each stage operate in synchronization with the signals CLK3 and CLK4 output from the
The input signal D1 shown in a) is sequentially time-divisionally divided into FIG.
As shown in C) and (d), eight output signals are generated and output. In this embodiment, the dynamic frequency divider circuit 1 divides the clock signal CLKI and supplies it to the first stage demultiplexer main body 20, so that the frequency of the clock signal CLKI and the first stage demultiplexer main body 20 are It is possible to match the bit rate of the input signal D1 to be input, and it is also possible to divide the input signal D1 at high speed without degrading the frequency performance of the demargue plexer main body 20. FIG. 11 is a block diagram showing an example of a multiplexer to which the fourth embodiment of the logic circuit according to the present invention is applied. The multiplexer shown in this figure includes a dynamic frequency divider circuit 1 that divides the frequency of the clock signal CLKI into 1/2, and a signal CLK2 output from the dynamic frequency divider circuit 1 that divides the frequency of the clock signal CLKI into 1/2.
A 1/4 frequency divider circuit 25 divides the frequency by 4 to generate a load signal LOAD, and input signals D1 to D1 are generated based on the output of the 174 frequency divider circuit 25 and the output of the dynamic frequency divider circuit 1.
Two 4-bit shift registers 26 and 27 that take in and shift D8, and a multiplexer body 2 that selects and outputs signals sequentially output from each of the 4-bit shift registers 26 and 27 based on the clock signal CLKI.
8, which takes in the human power signals D1 to D8 and sequentially and cyclically selects and outputs these human power signals D1 to D8 in accordance with the clock signal CLKI and the signal CLK2. The dynamic frequency divider circuit 1 has the same configuration as that used in the first embodiment described above, and is
is input manually, it is divided into 172 and the signal CLK
2 is generated and supplied to the 1/4 frequency divider circuit 25 and each of the 4-bit shift registers 26 and 27. The 174 frequency divider circuit 25 has two master/slave flip-flops, 30, which are driven by the signal CLK2 output from the dynamic frequency divider 1, and the outputs of these mask/slave flip-flops 29, 30 are "Lo". The NOR gate 31 generates a load signal LOAD when The 4-bit shift register 26 is composed of four mask-slave flip-flops connected in cascade, and receives the load signal L from the 1/4 frequency divider circuit 25.
Input signals D1 to D4 are taken in when OAD is supplied, and input signals D1 to D4 are taken in in synchronization with signal CLK2 output from the dynamic frequency divider circuit 1.
are sequentially shifted and supplied to the multiplexer main body 28. The 4-bit shift register 27 also includes three mask slave flip-flops connected in cascade, and one
When the load signal LOAD is supplied from the 174 frequency divider circuit 25, the input signals D5 to D8 are taken in and output from the dynamic frequency divider circuit 1. Human input signal D captured in synchronization with signal CLK2
5 to D8 are sequentially shifted and supplied to the multiplexer main body 28. The multiplexer body 28 alternately selects and outputs the outputs of the 4-bit shift registers 26 and 27 in synchronization with the clock signal CLKI. Thus, in this embodiment, the clock signal CLK
I drives the multiplexer main body 28, and the clock signal CLKI is sent to the dynamic frequency divider circuit 1.
The frequency is divided by 4-bit shift registers 26 and 27.
Since the clock signal CLKI is
can match the frequency of the signal output from the multiplexer main body 28 with the bit rate of the signal output from the multiplexer main body 28, and can divide the human input signals D1 to D8 at high speed without deteriorating the frequency performance of the multiplexer main body 28. FIG. 12 is a block diagram showing an example of a demultiplexer to which the fifth embodiment of the logic circuit according to the present invention is applied. The demultiplexer shown in this figure is connected to the clock signal CLKI.
A dynamic frequency divider circuit 1 that divides the frequency of
a 1/4 frequency divider circuit 30 that divides the frequency by 4 to generate the load signal LOAD; a demultiplexer body 31 that divides the input signal D1 based on the clock signal CLKI to generate two signals; When the load signal LOAD is output from the two 4-bit shift registers 32 and 33 that take in and shift each signal output from the demultiplexer main body 31 based on the signal CLKI, and the 1/4 frequency divider circuit 30. It includes 4-bit latch circuits 34 and 35 that latch and output the outputs of the 4-bit shift registers 32 and 33, and receives a clock signal CL.
The human input signal D1 is sequentially divided in synchronization with KI to generate and output eight output signals. The dynamic frequency divider circuit 1 has the same structure as that used in the first embodiment described above, and has a clock signal CLKI.
is input, it is divided into 172 and the signal CLK
2 is generated and supplied to the 174 frequency divider circuit 30. The 1/4 frequency divider circuit 30 includes two mask slave flip-flops 36 and 37 driven by the signal CLK2 output from the dynamic frequency divider circuit 1, and the outputs of these mask slave flip-flops 36 and 37 are " The NOR gate 38 generates the load signal LOAD when the signal becomes Lo, and divides the signal CLK2 outputted from the dynamic frequency divider circuit 1 into 1/4 to generate the load signal LOAD. Each latch circuit 34
, 35. Further, the demultiplexer main body 31 receives the clock signal C.
A mask/slave flip-flop 39 takes in the input signal D1 and outputs it when LKI rises, and a mask/slave flip-flop 39 takes in the human input signal D1 when the clock signal CLKI falls and outputs the input signal D1. A mask that outputs with a half-circle shift.
The slave/master flip-prop 40 generates the human input signal D1 in a time-division manner in synchronization with the clock signal CLKI, and transfers the two signals obtained by this acquisition operation to the 4-bit shift register 32.
, 33, respectively. Each of the 4-bit shift registers 32 and 33 is composed of four mask/slave flip-flops connected in cascade. It takes in signals, shifts them, and supplies them to latch circuits 34 and 35, respectively. Each latch circuit 34, 35 has four independent masters◆
It is composed of slave flip-flops 1.7, and when the load signal LOAD is supplied from the 174 frequency divider circuit 30, the 4-bit shift registers 32, 33
It latches each output signal output from and outputs them. Thus, in this embodiment, the clock signal CLK
I drives the demultiplexer body 31 to divide the input signal D, and the clock signal CLKI is frequency-divided by the dynamic frequency divider circuit 1, and then further divided into 1/4 by the 1/4 frequency divider circuit 30. Latch circuit 3
4 and 35 to latch the output signals of the 4-bit shift registers 32 and 33, so the clock signal C
The frequency of the LKI can be matched with the bit rate of the input signal D input to the demultiplexer main body 31, and the human input signal D1 can be time-divided at high speed without degrading the frequency performance of the demultiplexer main body 31. can. Furthermore, in each of the embodiments described above, a BFL type dynamic frequency divider circuit 1 is used, but instead of such a dynamic frequency divider circuit 1, an SCFL type dynamic frequency divider circuit as shown in FIG. The circuit 1a may also be used. The dynamic frequency divider circuit 1a shown in this figure includes an inverter circuit 40 that inverts an input signal, and two transfer gates 41 and 42 that gate the output of the inverter circuit 30 in accordance with a signal CLKI that is a complementary signal of a clock signal CLKI. and these transfer gates 41
, 42, and two transfer gates that gate the output of the buffer circuit 43 in response to the clock signal CLKI and feed it back to the input side of the inverter circuit 40. 44 and 45, and each time the clock signal C I, K1 and its complementary signal CLKi are supplied, the output signal is inverted and the clock signal CLK is
A signal is generated by dividing I into 1/2 and output. By using the dynamic frequency divider circuit 1a in this way, the frequency of the clock signal CLK1 can be dynamically divided using a single power supply. [Effects of the Invention] As explained above, according to the present invention, the frequency of the clock signal and the frequency of the input/output signal can be matched with each other with a simple structure, thereby facilitating system construction (!
: The next generation of optical communication. It can also cover the transmission rates used in communication technology.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a first embodiment of a logic circuit according to the present invention, FIG. 2 is a detailed circuit diagram of the dynamic frequency divider circuit shown in FIG. 1, and FIG. 3 is a dynamic frequency divider circuit shown in FIG. 2. 4 is a timing diagram showing an example of the operation of the equivalent circuit shown in FIG. 3; FIG. 5 is a timing diagram showing an example of the operation of the logic circuit shown in FIG. 1; FIG. 6 is a timing diagram showing an example of the operation of the logic circuit shown in FIG. FIG. 7 is a block diagram showing a second embodiment of the logic circuit according to
Detailed block diagram of the main body of the multiplexer shown in Figure 8.
9 is a block diagram showing a third embodiment of the logic circuit according to the present invention, FIG. 9 is a detailed block diagram of the demultiplexer shown in FIG. 8, and FIG. 10 is an example of the operation of the logic circuit shown in FIG. 8. 11 is a block diagram showing a fourth embodiment of the logic circuit according to the present invention, FIG. 12 is a block diagram showing a fifth embodiment of the logic circuit according to the present invention, and FIG. 13 is a block diagram showing the fifth embodiment of the logic circuit according to the present invention. Fig. 14 is a block diagram showing an example of a conventionally used multiplexer, and Fig. 15 is a circuit diagram showing another example of a dynamic frequency divider circuit that can be used. 16 is a detailed circuit diagram of the multiplexer gate shown in FIG. 14, and FIG. 17 is a timing diagram showing an example of the operation of the multiplexer shown in FIG. 14. 1...Dynamic frequency divider circuit

Claims (1)

[Claims] (1) In a logic circuit that performs either convergence processing or division processing on multiple signals, a logic circuit body that performs either convergence processing or division processing on multiple signals, and an input clock signal. A logic circuit comprising: a dynamic frequency divider circuit that divides the frequency and drives the logic circuit main body.