JPH0374951A - Synchronizing circuit - Google Patents

Abstract

PURPOSE:To simplify a circuit by giving a synchronizing clock with a period being a half of the internal clock period to a FF group on a shift bus and a synchronizing FF of the pre-stage and switching a shift mode input at every period of the synchronizing clock. CONSTITUTION:An internal clock from a clock generator 2 is inputted to a FF 10. Moreover, a synchronizing clock having a period being a half of the period of the internal clock from the clock generator 2 is inputted to a clock terminal of FFs 13a-13n forming an input register and a synchronizing FF 12 and inputted to the FF 10 while being inverted by an inverter 3. A shift mode signal inverted at every period of the synchronizing clock is inputted to the FF 12, FFs 13a-13n from the FF 10, the inverter 3 and an OR gate 11 not in the scan mode. An asynchronous input signal from input terminals 1a-1n is set to the FF 12, FFs 13a-(13n-1), shifted by one bit and set to the FFs 13a-13n and outputted to terminals 9a-9n as a synchronous signal. Thus, the circuit is simplified.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a synchronization circuit in an input interface for signal transmission between asynchronous devices or modules constituting an information processing system or the like.

[Conventional technology]

FIG. 3 is a block diagram showing a conventional synchronization circuit. In the figure, Im, 1b to 1n are input terminals, 2 is a clock generator that outputs an internal clock, 3 is an inverter, and 4
m, 4b to 4n are flip-flops for synchronization, 5 is a scan terminal, 6 is a scan mode terminal% 7'17b
1 to In are a group of flip-flops (hereinafter referred to as input registers) provided on the shift path by the internal clock, 8 is a scan out terminal, and 9 &.

9b to 9n are output terminals. As shown in the above configuration, this conventional synchronization circuit has an input interface that receives asynchronous signals, and receives each input signal through two stages of flip-flops, that is, synchronization flip-flops 4a to 4n and input registers 1a to In. The output of the receiving L, second stage input register is used as a synchronization output.

[Problem to be solved by the invention]

The conventional synchronization circuit described above has two asynchronous input signals.
Since twice as many flip-flops are required, the disadvantage is that the amount of hardware is large.

[Means to solve the problem]

The synchronization circuit according to the present invention includes a synchronization flip-flop located before a group of seven flip-flops on a shift path, and a synchronization flip-flop that is synchronized with an internal clock and has a half period. and means for switching the shift mode inputs of the flip-flop group and the synchronizing flip-flops every cycle of the synchronizing clock.

[Effect]

The present invention can reduce the amount of hardware by using a shift path of an input register consisting of a group of flip-flops.

〔Example〕

FIG. 1 is a block diagram showing an embodiment of a synchronization circuit according to the present invention. In the same figure, 10 is the second input terminal.
A flip-flop is input with the internal clock shown in the figure (, ), and the inverted synchronized clock (see Figure 2 (b)) is input into the clock terminal. 11 is a logic circuit between the scan mode signal and the output signal of the 7-lip-flop 10. An OR gate that calculates the sum and outputs a shift mode signal; 12 is a synchronization flip-flop provided before the input register shown below; 13a
~13n are input registers. The synchronized clock shown in FIG. 2(b) is a half-synchronized clock that is synchronized with the internal clock shown in FIG. 2(,).

Next, the operation of the synchronization circuit with the above configuration is shown in Figure 2 (
, ) to FIG. 2(j). The internal clock shown in FIG. 2 (-) output from the clock generator 2 is input to the input terminal of the flip-flop 10. Furthermore, the synchronized clock shown in FIG. 2(b) outputted from the clock generator 2 is transmitted via the inverter 3 to the clock terminal of the 7-limp-flop 10, the clock terminal button of the synchronizing flip-flop 12, and the input registers 13&~13n. Input each clock terminal. Here, when not in scan mode, flip-flop 10. Inverter 3. A shift mode signal (see FIG. 2(c)) that is inverted every cycle of the synchronization clock is sent from the OR gate 11 to the synchronization flip-flop 12 and the input registers 13a to 131.
11. That is, Fig. 2 (-) to Fig. 2 (j
) At timing A shown by K, the input terminals 1a to 1nV
The signals shown in FIGS. 2(d) to 2(f) that are input to the synchronizing flip-flop 12 and the input register 13a
~13n-1. Then, at timing B, the signals set in the synchronization flip-flop 12 and the input registers 13a to 13m-1 are shifted by 1 bit and set in the input registers 13& to 13n, and output from the output terminals 9& to 9n (see Fig. 2). ~Figure 2 (j)
The synchronization signal shown in can be output.

〔Effect of the invention〕

J: As described in detail, according to the synchronization circuit according to the present invention, the shift path of the input register is used to time-divisionally synchronize the 7 flip-flops in the first stage and the flip-flops in the second stage. By performing both roles, the amount of hardware can be reduced.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a synchronization circuit according to the present invention, FIG. 2 is a timing chart showing operating waveforms of each part of FIG. 1, and FIG. 3 is a block diagram showing a conventional synchronization circuit. It is. 10...Flip-flop, 11...OR gate, 12...Flip-flop for synchronization, 13&~
13n...Input register.

Claims (1)

[Claims] In an input interface in which a group of flip-flops having a shift path based on an internal clock receives a group of signals that change asynchronously, a synchronizing flip-flop located before the flip-flop group on the shift path, and a synchronizing flip-flop located before the flip-flop group on the shift path; means for providing a synchronization clock having a half period in synchronization with an internal clock to the flip-flop; and means for switching shift mode inputs of the flip-flop group and the synchronization flip-flop every cycle of the synchronization clock. 1. A synchronization circuit comprising: receiving each input signal in a flip-flop at a previous stage on a shift path of a corresponding synchronization output flip-flop, and then synchronizing and outputting an output shifted once.