KR100292993B1 - Initial alignment apparatus of reference clock - Google Patents

Abstract

1. TECHNICAL FIELD OF THE INVENTION

The present invention relates to a start point alignment device of a reference clock used in a CDMA system or the like.

2. The technical problem to be solved by the invention

The present invention seeks to provide a reference clock starting point alignment device having a low complexity using simple logic.

3. Summary of Solution to Invention

The present invention comprises: delayed clock generation means for generating a predetermined number of delayed clocks which are received from a reference clock from outside and delayed by a predetermined period of the reference clock; Selection signal generating means for generating the predetermined number of signals for dividing one period of the reference clock by the predetermined number to maintain a high level in a corresponding section; And an aligned reference clock output means for selecting and outputting one of the predetermined number of delayed clocks input from the delayed clock generation means as a reference point-aligned reference clock using the selection signal transmitted from the selection signal generation means. box.

4. Important uses of the invention

The present invention is used in a code division multiple access (CDMA) system and the like.

Description

Reference clock start point alignment device {INITIAL ALIGNMENT APPARATUS OF REFERENCE CLOCK}

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to an apparatus for aligning a start point of a reference clock used in a code division multiple access (CDMA) system. Prior to this, the present invention relates to a reference clock start point alignment device that is required to perform despreading by adjusting a reference clock of a receiver and synchronizing with a reference clock of a transmitter.

In general, in order to spread and despread the CDMA system, it is necessary to synchronize the reference clock of the transceiver after the start of alignment of the receiver reference clock, and the synchronization of the reference clock of the transceiver is required to establish synchronization of the receiver. Therefore, data demodulation can be performed smoothly.

However, the conventional reference clock start point alignment device has a problem in that power consumption is large and space cannot be used efficiently due to a complicated configuration.

An object of the present invention is to provide a reference clock start point alignment device having a simple configuration using minimal logic elements.

1 is a block diagram of an embodiment of a reference clock start point alignment device according to the present invention;

Figure 2 is a detailed configuration diagram of an embodiment of a delay clock generator according to the present invention.

3 is a detailed configuration diagram of an embodiment of a selection signal generator according to the present invention;

4 is a detailed block diagram of an embodiment of an aligned reference clock output unit according to the present invention;

5 to 8 is an operation timing diagram by the reference clock start point alignment device according to the present invention.

* Explanation of symbols for the main parts of the drawings

101: delay clock generator 102: selection signal generator

103: aligned reference clock output

The present invention for achieving the above object, in the reference clock start point alignment device for aligning the start point of the reference clock, receiving a reference clock from the outside to generate a predetermined number of delayed clocks delayed by a predetermined period of the reference clock Delay clock generating means for; Selection signal generating means for generating the predetermined number of signals for dividing one period of the reference clock by the predetermined number to maintain a high level in a corresponding section; And an aligned reference clock output means for selecting and outputting one of the predetermined number of delayed clocks input from the delayed clock generation means as a reference point-aligned reference clock using the selection signal transmitted from the selection signal generation means. Characterized in that made.

The above objects, features and advantages will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram of an embodiment of a reference clock start point alignment device according to the present invention.

As shown in the figure, the reference clock start point alignment device receives a reference clock from the outside and generates a delayed clock generator 101 for generating four delayed clocks delayed by one quarter, and one period of the reference clock is four. Delay clock using the selection signal generator 102 and the four selection signals transmitted from the selection signal output unit 102 to generate four signals that maintain a high level only in a corresponding section. It is composed of an aligned reference clock output unit 103 for selecting and outputting one of the four delayed clocks input from the generator 101 as a reference point aligned start clock.

In this case, the alignment signal is processed and used as a clock for causing the aligned reference clock output unit 103 to operate one of the four selection signals as a signal for selecting the aligned reference clock. The clock four times faster than the reference clock is used as the clock in the delay clock generator 101 and the selection signal generator 102.

2 to 4 are detailed diagrams of one embodiment of each part of the reference clock start point alignment device according to the present invention.

2 is a detailed configuration diagram of an embodiment of a delay clock generator according to the present invention.

The delay clock generator 101 receives a reference clock from the outside and uses a clock four times faster than the reference clock as a clock to generate a first D flip-flop for generating a 1/4 delayed clock that is 1/4 delayed from the reference clock. 2/4 delayed clock which is 2/4 delayed from the reference clock with a clock received from the flop 201 and the first D flip-flop 201 and clocked 4 times faster than the reference clock. The second D flip-flop (202) and the second D flip-flop (202) to generate a 2/4 delay clock from the clock and the clock four times faster than the reference clock A third D flip-flop 203 and a third quarter delay clock from the third D flip-flop 203 for generating a three quarter delayed clock three quarters from the reference clock. Clocked four times faster than the reference clock, again delayed by one-quarter of the reference clock, and is equal to four-quarter delayed clock 4 includes a first D flip-flop (flip-flop, 204) for generating.

The quarter delayed clock generator 101 sequentially generates four delayed clocks delayed by one quarter of a cycle from the reference clock and transfers the delayed clocks to the aligned reference clock output unit 104.

3 is a detailed configuration diagram of an embodiment of a selection signal generator according to the present invention.

The selection signal generator 102 detects a rising edge of the reference clock and outputs a rise for outputting a rise clock that maintains a high level for one period of a clock four times faster than the reference clock. The clock output circuit 31 detects the falling edge of the reference clock and a pole for outputting a fall clock that maintains a high level for one period of the clock four times faster than the reference clock. The clock output circuit 32 and a portion of the high level region of the reference clock that do not correspond to the high level of the rise clock are detected for one cycle of the clock four times faster than the reference clock. Rise high clock output circuit 33 for outputting the Rise-High clock that maintains the high level, and does not correspond to the fall clock of the low level region of the reference clock 4 times faster than reference clock During one period of the other clocks and a right follower (Fall-Low) Polo right clock output circuit 34 for outputting a clock to maintain a high level (High level).

The rise clock output circuit 31 receives a reference clock from the outside, and uses a fifth D flip-flop 311 for outputting a latched signal using a clock four times faster than the reference clock, and a fifth D. A first inverter 312 for receiving and inverting the latched signal from the flip-flop 311 and an inverted signal from the first inverter 312 and receiving a reference clock from outside It is composed of a first AND gate 313 for receiving and logically multiplying the input signal to output a rise clock.

The pole clock output circuit 32 receives a second clock (Inverter, 321) for receiving and inverting the reference clock from the outside, and receives a reference clock inverted from the second inverter (321), 4 than the reference clock Inverts the latched signal from the sixth D flip-flop 322 and the sixth D flip-flop 322 for outputting the latched signal using the faster clock as the clock. For receiving the inverted signal from the third inverter (Inverter, 323), the third inverter (Inverter, 323) and the inverted reference clock received from the second inverter (Inverter, 321) for outputting a pole clock And a second AND gate 324.

The rise high clock output circuit 33 receives a rise clock from the rise clock output circuit 31 and inverts the fourth inverters 331 and the fourth inverters 331 for inverting and outputting the rise clocks. The third logical AND gate 332 is configured to receive a signal, receive a reference clock from an external source, and multiply it to output a rise-high clock.

The follow clock output circuit 34 receives a fall clock from the fall clock output circuit 32 and inverts from a fifth inverter 341 and a fifth inverter 341 for inverting and outputting the fall clock. Receiving a signal received from the second inverter (321 Inverter 321) of the pole clock output circuit 32 for receiving a signal and inverting and outputting the reference clock from the outside to logically multiply and output a fall-low clock And a fourth AND gate 342.

4 is a detailed configuration diagram of an embodiment of an aligned reference clock output unit according to the present invention.

The aligned reference clock output unit 103 receives a clock four times faster than the reference clock as an input signal, and outputs a sixth inverter 401 for inverting and outputting the clock and an inverted clock from the sixth inverter 401. A seventh D flip-flop 402 and a seventh D flip for outputting a delayed alignment signal (Align Signal_Delay) by taking an input of a clock terminal and an alignment signal as an input of an input terminal. The delayed alignment signal (Align Signal_Delay) is input from the flop 402 as a clock, and the delayed clock generator 101 receives four delayed clocks delayed by a quarter cycle as input signals. Four signals such as a rise clock, a rise-high clock, a fall clock, and a fall-low clock are input from the selection signal generator 102 as a selection signal. Outputs one of the two delayed clocks as an aligned reference clock It consists of a multiplexer 403 for.

Referring to the operation of the aligned reference clock output unit 103, the delayed alignment signal (Align Signal_Delay) used as the clock of the multiplexer 403 first transmits the alignment signal to the sixth inverter 401 and the seventh D flip. Generated using a flop-flop 402.

The multiplexer 403 detects one selection signal having a high level state at the rising edge of the delayed alignment signal (Align Signal_Delay), which is used as a clock, and delays four delays by one detected selection signal. One of the clocks is selected and output as an aligned reference clock.

5 to 8 are operation timing diagrams by the reference clock start point alignment device according to the present invention.

5 is an operation timing diagram of the first embodiment of the apparatus for aligning a reference clock start point according to the present invention.

FIG. 5 illustrates a case in which the rising edge of the alignment signal is located in the high level region of the rise clock, and is after the rising edge of the delayed alignment signal Align signal_delay. The aligned reference clock will follow the 4/4 delayed clock. This has the effect of aligning the reference clock, which was free running when the alignment signal occurs (high active), with the alignment signal.

6 is an operation timing diagram according to a second embodiment of the apparatus for aligning a reference clock start point according to the present invention.

FIG. 6 illustrates a case in which a rising edge of an alignment signal is located in a high level region of a rise-high clock, and thus a rising edge of the delayed alignment signal (ignition signal_delay). After the edge, the aligned reference clock follows the quarter delay clock. This has the effect of aligning the reference clock, which was free running when the alignment signal occurs (high active), with the alignment signal.

7 is an operation timing diagram of a third embodiment of the apparatus for aligning a reference clock start point according to the present invention.

FIG. 7 illustrates a case in which the rising edge of the alignment signal is located in the high level region of the fall clock, and is aligned after the rising edge of the delayed alignment signal Align signal_delay. The clock follows the 2/4 delayed clock. This has the effect of aligning the reference clock, which was free running when the alignment signal occurs (high active), with the alignment signal.

8 is an operation timing diagram according to a fourth embodiment of the reference clock start point alignment device according to the present invention.

FIG. 8 illustrates a case in which a rising edge of an alignment signal is located in a high level region of a fall-low clock, and a rising edge of the delayed alignment signal (ignition signal_delay) is shown in FIG. After the edge, the aligned reference clock follows the 3/4 delayed clock. This has the effect of aligning the reference clock, which was free running when the alignment signal occurs (high active), with the alignment signal.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.

As described above, the present invention provides a very simple configuration of hardware using logic elements such as an inverter, an AND circuit, a flip-flop, and a multiplexer (MUX), thereby enabling code division multiple access. By aligning the starting point of the reference clock in a (CDMA) system or the like, it is possible to remarkably improve the merchandise of the product and the reliability of the system, and free running when an alignment signal indicating alignment of the reference clock is input. The internal clock of the chip is aligned with the alignment signal, and the internal reference of the chip is newly aligned by the aligned reference clock.

Claims (10)

A reference clock start point alignment device for aligning a start point of a reference clock, Delay clock generating means for generating a predetermined number of delayed clocks received from a reference clock from outside and delayed by a predetermined period of the reference clock; Selection signal generating means for generating the predetermined number of signals for dividing one period of the reference clock by the predetermined number to maintain a high level in a corresponding section; And Aligned reference clock output means for selecting and outputting one of the predetermined number of delayed clocks input from the delayed clock generation means as a reference point-aligned reference clock using the selection signal transmitted from the selection signal generation means. The reference clock start point alignment device made, including. The method of claim 1, The delay clock generating means, First latch means for receiving the reference clock and generating a quarter delayed clock delayed by a quarter period of the reference clock; Second latch means for receiving the 1/4 delayed clock and generating a 2/4 delayed clock delayed by 2/4 periods of the reference clock; Third latch means for receiving the 2/4 delayed clock and generating a 3/4 delayed clock delayed by 3/4 periods of the reference clock; And Fourth latch means for receiving the 3/4 delayed clock and generating a 4/4 delayed clock delayed by 4/4 of the reference clock; The reference clock start point alignment device made, including. The method of claim 2, The selection signal generating means, Rise clock output means for detecting a rising edge of the reference clock and outputting a rise clock that maintains a high level for one period of a clock four times faster than the reference clock; Poll clock output means for detecting a falling edge of the reference clock and outputting a fall clock maintaining a high level for one period of a clock four times faster than the reference clock; A portion of the high level region of the reference clock that does not correspond to the high level of the rise clock is detected, and a high level is detected for one period of a clock four times faster than the reference clock. Rise-high clock output means for outputting a rise-high clock to maintain a clock signal; And A part of the low level region of the reference clock that does not correspond to the high level of the fall clock is detected, and a high level is detected for one period of a clock four times faster than the reference clock. Follower clock output means for outputting a fall-low clock that maintains The reference clock start point alignment device made, including. The method of claim 3, wherein The rise clock output means, Fifth latch means for receiving the reference clock and outputting a delayed clock; First inverting means for receiving a delayed clock from the fifth latching means and inverting and outputting the clock; And First logical product calculating means for receiving an inverted clock from the first inverting means, receiving the reference clock from an external device, and performing an AND operation to output a rise clock. The reference clock start point alignment device made, including. The method of claim 4, wherein The rise high clock output means, Second inverting means for receiving and inverting the rise clock; And Second logical product calculating means for receiving an inverted signal from the second inverting means, receiving the reference clock, and performing an AND operation to output a rise-high clock; The reference clock start point alignment device made, including. The method of claim 3, wherein The pole clock output means, First inverting means for receiving the reference clock and inverting and outputting the reference clock; Fifth latch means for receiving the inverted reference clock from the first inverting means and outputting a delayed clock; Second inverting means for receiving the delayed clock from the fifth latching means and inverting and outputting the clock; And First logical product calculating means for receiving an inverted clock from the second inverting means, receiving the inverted reference clock from the first inverting means, and performing an AND operation to output a fall clock. The reference clock start point alignment device made, including. The method of claim 6, The follow clock output means, Third inverting means for receiving and inverting the Fall clock; And A second AND operation means for receiving an inverted fall clock from the third inverting means, receiving the inverted reference clock from the first inverting means, and performing an AND operation to output a fall-low clock; The reference clock start point alignment device made, including. The method according to any one of claims 2 to 7, Each latch means, A reference clock starting point alignment device, characterized in that receiving a clock four times faster than the reference clock as a latch clock. The method according to any one of claims 1 to 7, The aligned reference clock output means, Fourth inverting means for receiving a clock four times faster than the reference clock as an input signal, and inverting and outputting the clock; Sixth latch means for outputting a delayed alignment signal (Align Signal_Delay) by using the clock inverted from the fourth inverting means as a clock and the alignment signal as an input; And The delayed alignment signal (Align Signal_Delay) is input from the sixth latch means as a clock, four delay clocks are input from the delay clock generator, and four selection signals are received from the selection signal generator. Selection means for selecting and outputting one of four delayed clocks as an aligned reference clock The reference clock start point alignment device made, including. The method of claim 9, The selection means, One of the four selection signals is detected by the input clock, and the reference clock start point alignment is used, wherein the delayed clock selected by the detected selection signal is used as an aligned reference clock until the next reference clock start point alignment. Device.