KR200222679Y1 - Apparatus for selective detecting rising edge and falling edge of input signal - Google Patents

Abstract

The present invention is to provide a selective detection device for the rising edge and the falling edge of the input signal, the present invention is a latch unit 11 for receiving and latching the input signal; A falling edge generator 12 which receives an input signal and an output of the latch unit 11 and generates falling edges; A rising edge generating unit (13) (14) for receiving an input signal and the output of the latch unit (11) to generate rising edges; A selection unit 15 which receives the outputs of the falling edge generating unit 12 and the rising edge generating unit 14 and selects and outputs the falling edge and the rising edge; By including a reset unit 16 for resetting the latch unit 11, by generating a pulse at the rising edge and the falling edge of the input signal in accordance with the external clock signal to selectively detect the rising edge and the falling edge Will be.

Description

Apparatus for selective detecting rising edge and falling edge of input signal}

The present invention relates to an edge detection device of an input signal, and in particular, a rising edge of an input signal suitable for selectively detecting rising and falling edges by generating pulses at rising and falling edges of the input signal according to an external clock signal. It relates to a selective detection device of the edge and falling edge.

In general, the rising edge is the time when the waveform rises from 10% to 90%, and the falling edge is the time when the waveform falls from 90% to 10%.

The conventional edge detection apparatus includes a flip-flop latching an input signal, a delay unit for delaying the input signal, a reset unit, and a selection unit for selecting and outputting rising and falling edges.

1 is a block diagram of an edge detection apparatus of a conventional input signal.

As shown therein, first and second delay units (1) (2) for delaying the input signal; A first flip-flop (3) for receiving the delayed signal from the first delay unit (1) and latching the input signal; A second flip-flop (4) for receiving the delayed signal from the second delay unit (2) and latching the input signal; A selector which receives a falling edge from the signal latched by the first flip-flop 3 and receives a rising edge from the signal latched by the second flip-flop 4 to select and output one of a falling edge and a rising edge (5); A reset unit which resets the first and second flip-flops 3 and 4 by outputting a reset pulse to detect the falling and rising edges of the first and second flip-flops 3 and 4, respectively. 6) consists of.

FIG. 2 is a timing diagram at the time of selecting the rising edge in FIG. 1.

Therefore, as shown in FIG. 1, when constant data is input, the first delay unit 1 delays the input data slightly. Then, the first flip-flop 3 latches the input data at the inverted timing by receiving the delayed signal from the first delay unit 1. At this time, the output of the first flip-flop 3 comes from the falling edge of the input data. The reset unit 6 generates a reset pulse to cause the falling edge of the first flip-flop 3. Therefore, the falling edge can be detected by the first flip-flop 3.

In addition, when constant data is input, the second delay unit 2 delays the input data slightly. Then, the second flip-flop 4 latches the input data at the inverted timing by receiving the delayed signal from the second delay unit 4. At this time, the output of the second flip-flop 4 comes from the rising edge of the input data. The reset unit 6 generates a reset pulse to cause the rising edge of the second flip-flop 4. Therefore, the falling edge can be detected by the second flip-flop 4.

Therefore, the rising edge can be detected by inverting the clock and the data input to the second flip-flop 4.

The rising edge and the falling edge generated in this way can be selectively detected by the selection unit 5 composed of a multiplexer.

However, such a conventional edge detection device detects an edge by delaying input data, so that if the characteristics of the delay circuit are bad, the edge detection device may be affected by the edge detection device.

Therefore, the present invention has been proposed to solve the conventional problems as described above, and an object of the present invention is to selectively generate the rising and falling edges by generating pulses on the rising and falling edges of the input signal according to an external clock signal. An object of the present invention is to provide a selective detection device for detecting rising and falling edges of an input signal.

In order to achieve the above object, the selective detection device of the rising edge and falling edge of the input signal according to an embodiment of the present invention,

A latch unit configured to receive an input signal and latch the input signal; A falling edge generation unit configured to receive an input signal and an output of the latch unit and generate a falling edge; A rising edge generation unit receiving an input signal and an output of the latch unit to generate a rising edge; A selection unit which receives the outputs of the falling edge generator and the rising edge generator and selects and outputs the falling edge and the rising edge; It is characterized in that the technical configuration comprises a reset unit for resetting the latch unit.

1 is a block diagram of an edge detection apparatus of a conventional input signal,

2 is a timing diagram at the time of selecting the rising edge in FIG.

3 is a block diagram of a selective detection device of the rising edge and falling edge of the input signal according to the present invention,

FIG. 4 is a timing diagram at the time of selecting the rising edge in FIG. 3.

Explanation of symbols on the main parts of the drawings

11: latch portion 12: falling edge generating portion

13 Inverter 14: rising edge generating unit

15: selector 16: reset unit

Hereinafter, an embodiment according to the present invention, the technical idea of the selective detection device of the rising edge and the falling edge of the input signal as follows.

Figure 3 is a block diagram of a selective detection device of the rising edge and falling edge of the input signal according to the present invention.

As shown therein, a latch unit 11 which receives an input signal and latches it; A falling edge generator 12 which receives an input signal and an output of the latch unit 11 and generates falling edges; A rising edge generating unit (13) (14) for receiving an input signal and the output of the latch unit (11) to generate rising edges; A selection unit 15 which receives the outputs of the falling edge generating unit 12 and the rising edge generating unit 14 and selects and outputs the falling edge and the rising edge; And a reset unit 16 for resetting the latch unit 11.

The falling edge generating unit 12 is configured as a logic sum element that receives the input signal and the output of the latch unit 11 and performs a logical sum operation to generate the falling edge.

The rising edge generator 13 and 14 include an inverter 13 for inverting and outputting a phase of an input signal; The inverter 13 includes a rising edge generator 13 that receives a phase inverted input signal and an output of the latch unit 11 and generates rising edges.

The rising edge generating unit 14 includes a logic sum element that generates a rising edge by receiving an input signal inverted in phase from the inverter 13 and an output of the latch unit 11 and performing a logical sum operation.

The selector 15 includes a multiplexer (Mux) that receives and outputs the outputs of the falling edge generator 12 and the rising edge generator 14 to select and output the falling edge and the rising edge. do.

In this case, the selector 15 receives negative outputs of the falling edge generator 12 and the rising edge generator 14 to perform a negative logic operation to detect and output the falling edge and the rising edge simultaneously. It consists of.

The operation of the selective detection device of the rising edge and the falling edge of the input signal according to the present invention configured as described above will be described in detail with reference to the accompanying drawings.

First, FIG. 4 is a timing diagram at the time of selecting the rising edge in FIG.

Therefore, the latching unit 11 latches the input data at the clock having a faster period than the input data in accordance with the rising edge of the clock, so that Qn of the flip-flop, which is the latching unit 11, and the falling edge composed of the first logical sum element are formed. The generation unit 13 performs an OR operation to detect the falling edge. At this time, the reset unit 16 resets the latch unit 11 configured as a flip-flop.

The rising edge generation unit 14 composed of the second logical sum element detects the rising edge by performing a logical sum operation on the flip flop Q which is the latch unit 11 and the input data inverted by the inverter 13. At this time, the reset unit 16 generates a reset pulse to reset the flip-flop 11.

Then, the selection unit 15 can select whether the rising edge detection or the falling edge detection.

When the selector 15 is configured as a multiplexer, the falling edge and the rising edge may be multiplexed to be selected and output.

In addition, when the selector 15 is configured as a negative logic element, the outputs of the falling edge generator 12 and the rising edge generator 14 are input to perform negative logic multiplication to detect the falling edge and the rising edge at the same time. can do.

As such, the present invention selectively detects the rising and falling edges by generating pulses at the rising and falling edges of the input signal according to an external clock signal.

Therefore, since the edge is detected without delaying the input data, the rising and falling edges can be detected regardless of the characteristics of the delay circuit, and the edge detection can be performed with almost no delay.

While the preferred embodiment of the present invention has been described above, the present invention may use various changes, modifications, and equivalents. It is clear that the present invention can be applied in the same manner by appropriately modifying the above embodiments. Therefore, the above description does not limit the scope of the present invention defined by the limits of the following utility model registration claims.

As described above, the selective detection device for the rising and falling edges of the input signal according to the present invention selectively detects the rising and falling edges by generating pulses at the rising and falling edges of the input signal according to an external clock signal. It will work.

In addition, since the present invention detects the edge using an internal clock without using a delay circuit, it is not necessary to follow the characteristics of the delay circuit, so that the rising edge and the falling edge can be detected regardless of the characteristics of the delay circuit. There is also an effect that can detect the edge with little.

In addition, the present invention can implement the edge detection device by a combination of simple logic gates by not using a delay means, there is an effect that can selectively detect the rising and falling edges.

Claims (2)

A latch unit 11 which receives an input signal and latches it; A falling edge generator 12 which receives an input signal and an output of the latch unit 11 and generates falling edges; A rising edge generating unit (13) (14) for receiving an input signal and the output of the latch unit (11) to generate rising edges; A selection unit 15 which receives the outputs of the falling edge generating unit 12 and the rising edge generating unit 14 and selects and outputs the falling edge and the rising edge; And a reset unit (16) for resetting the latch unit (11). The method of claim 1, wherein the rising edge generating unit 13, 14, An inverter 13 for inverting and outputting a phase of an input signal; The rising edge and falling edge of the input signal, characterized in that it comprises a rising edge generator 13 for receiving the input signal and the output of the latch unit 11 inverted phase from the inverter 13 to generate the rising edge Selective detection of edges.