KR930004087B1 - Digital signal transition detection circuit - Google Patents

Abstract

The circuit for detecting the variation point of potential level of the digital signal to easily set the edge detection pulse width by using a counter comprises a transition point detector (10) for a digital input signal (Pi), a pulse width controller (20) for receiving the detector (10) output signal to generate a control signal (RE2), and a flip-flop (FF2) for receiving the detector (10) output signal as a clock pulse (CK2) to output a constant width of pulse from the transition point of the digital input signal (Pi).

Description

Digital Signal Transition Detection Circuit

1 is a general detection circuit diagram for digital signal transition.

2 is a detection circuit diagram of the present invention for digital signal transition.

3A to 3D are waveform diagrams of respective parts of FIG. 2.

* Explanation of symbols for main parts of the drawings

1: Counter XOR1: Exclusive Oagate

I1-In: Inverter FF1, FF2: Flip-flop

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to means for detecting a potential level change point of a digital signal used in a system having a control signal. Particularly, the present invention relates to detecting a point of time when a potential level transitions from "high" to "low". The present invention relates to a digital signal transition detection circuit suitable for generating a control signal.

In general, the edge detection circuit of the input pulse is configured such that the inverters I1-In gates are connected in series to one input terminal of the exclusive oar gate XOR1 as shown in FIG.

In the circuit configured as described above, the high potential is output to the output terminal of the exclusive oragate XOR at the moment when the high potential input pulse Pi is applied, and the pulse width is determined by the number of inverters I1-In. It is determined by the delay time, and the high potential pulse by the inverters I1-In is also outputted in the falling edge of the input pulse Pi as described above.

However, in such a general edge detection circuit, the pulse width of the transition detection signal is determined according to the delay time of the gate. The delay time of the gate is unstable due to the change of the processor, which makes it difficult to accurately predict the transition detection output. In addition to the difficulty, when a large pulse width is required, a large number of gates is required, resulting in a larger error.

The present invention has been made to accurately detect the transition time of the digital signal in order to solve this problem, so that the user can generate a desired pulse width, which will be described in detail with reference to the accompanying drawings.

를 출력하는 펄스폭 제어부(20)와, 상기 펄스폭 제어부(20)로부터 리세트 신호

를 공급받고, 상기 천이시점 검출부(10)의 출력신호를 클럭신호(CK2)로 공급받아 디지탈 입력신호(Pi)의 천이시점으로 부터 일정폭의 펄스를 출력하는 플립플롭(FF2)으로 구성한 것으로, 이와같이 구성된 본 발명의 작용 및 효과를 제2도 각부의 파형을 보인 제3도를 참조하여 상세히 설명하면 다음과 같다.2 is a digital signal transition detection circuit diagram of the present invention, which is composed of an inverter (I1-In) and an exclusive oar gate (X6R1) to detect a transition time point of a digital input signal Pi. And a counter 1 and a flip-flop FF1 to receive the output signal of the transition point detection unit 10 to generate a constant pulse width from the transition point.

A pulse width control section 20 for outputting a signal and a reset signal from the pulse width control section 20;

And a flip-flop (FF2) which receives the output signal of the transition point detection unit 10 as the clock signal CK2 and outputs a pulse of a predetermined width from the transition point of the digital input signal Pi. The operation and effect of the present invention configured as described above will be described in detail with reference to FIG. 3 showing the waveform of FIG. 2.

When a pulse, such as the third (b) diagram, is input to the pulse input terminal Pi, it is directly applied to one input terminal of the exclusive oragate XOR1 and at the same time through the inverters I1-In for a predetermined time. Since the delay time is equal to the number of inverters I1-In, it is applied to the other input terminal of the exclusive orifice XOR1. As in, pulses having a pulse width corresponding to the delayed time by the n inverters I1 -In are output.

에 공급되고, 이에따라 의해 제3(a)도와 같은 기본 클럭신호를 입력하는 카운터(1)의 리세트가 해제되어 그 카운터(1)가 기 설정된 값을 카운트하기 시작하며, 이때부터 그의 출력단자(Q)에 고전위가 출력된다.The output pulse shown in FIG. 3 (c) output from the exclusive orifice XOR1 is the same as that of the flip-flops FF1 and FF2 having the input terminals D1 and D2 connected to the power terminal VDD, respectively. Since it is provided as the clock signals CK1 and CK2, the output terminal Q1 of the flip-flop FF1 at the rising edge of the output pulse as shown in FIG. A high potential is output to the reset terminal of the counter (1).

The counter 1 is then reset to reset the counter 1 for inputting the basic clock signal as shown in FIG. 3 (a), and the counter 1 starts to count the preset value. The high potential is output to Q).

Thereafter, when the counter 1 counts all of the preset values, a low potential is output to the output terminal Q thereof, which is provided as a reset signal of the flip-flops FF1 and FF2, and the flip-flop FF1. The low potential starts to be output to the output terminals Q1 and Q2 of the FF2 and FF2.

As time elapses, a falling edge of the pulse input to the pulse input terminal Pi as shown in FIG. 3 (b) is applied to one input terminal of the exclusive oragate XOR1. The low potential is applied but the other input terminal is continuously supplied with the high potential for the time delayed by the inverters I1-In, so as shown in FIG. 3 (c), the output of the exclusive oar gate XOR1 during the delay time. A second high potential pulse is output at the terminal.

Accordingly, the flip-flops FF1 and FF2 and the counter 1 repeat the above-described operation, and the second pulse of FIG. 3d is output to the output terminal Q2 of the flip-flop FF2.

As described in detail above, the present invention has an advantage of providing confidence to the user by enabling the user to easily and accurately set the edge detection pulse width of the pulse using a counter.

Claims (1)

Transition time detection unit 10 for detecting the transition time point of the digital input signal Pi and the output signal of the transition time detection unit 10 is supplied with a control signal to generate a constant pulse width from the transition time point

A pulse width control section 20 for outputting a signal and a reset signal from the pulse width control section 20;

And a flip-flop (FF2) that receives the output signal of the transition point detection unit 10 as the clock signal CK2 and outputs a pulse of a predetermined width from the transition point of the digital input signal Pi. A digital signal transition detection circuit for an input pulse.

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