KR100198417B1 - Frame sync. clock generating circuit for receiving in dcs sync. system - Google Patents

Abstract

The present invention relates to a DCS (Digital Cross-connect System) synchronous system having a switching function, comprising: a plurality of synchronous signal-specific matching function modules for matching STM-n input signals; a switch module for distributing the matched signals; And a system clock generating module for supplying a common reference frame synchronizing clock to the modules, and arranging data frames according to one reference frame synchronizing clock. The synchronous transmitting system includes a DCS synchronous transmission system It is possible to easily align the delay difference of the data frame arbitrarily generated by the matching function module in the data connection between the matching function module and the switch function module by the same reference frame synchronizing clock of the system clock generating module with a simple configuration.

According to the present invention, there is an advantage that it is not necessary to supply the frame synchronous clock for transmission / reception for each function module in the system clock generating module. Therefore, it is possible to easily manufacture the system clock generating module, It is possible to reduce the number of connection signal lines between the first and second transistors, thereby facilitating the design of the entire system and reducing the fabrication cost.

Description

Frame Synchronous Clock Generation Circuit for Reception in DCS Synchronous System

The present invention is characterized in that a frame synchronization clock for reception in consideration of a time delay difference is generated for data frame alignment by one reference frame synchronization clock in a DCS (Digital Cross-connect System) synchronous system requiring a switching function To a frame synchronization clock generation circuit for reception in a DCS synchronous system.

As the signal processing of the synchronous transmission system becomes larger or faster, signal processing between modules is required to be performed at a higher speed, and the number of the connection signal lines is limited by the size of the module and the connector.

Therefore, in order to improve the performance of the transmission system, it is necessary to reduce the number of connection signal lines between the modules as much as possible. In a system requiring the aggregation function such as the circuit distribution system, alignment of data frames between functional modules is essential for the switching function.

Generally, a synchronous transmission system performs frame alignment and synchronization between modules according to a reference data clock and a reference frame clock supplied from a system clock generating module.

However, when the reference frame synchronizing clock of the system supplied from the system clock generating module is transmitted to each of the function-specific modules, different signal delays are generated for each of the functional modules for the reference frame synchronizing clock. In this case, The module for each function requests a frame sync clock for transmission / reception of different phases for frame synchronization of a signal upon reception. The operation of such a conventional synchronous transmission system will be described with reference to FIG.

FIG. 1 is a block diagram of a conventional synchronous transmission system for inter-module data frame alignment. Referring to FIG. 1, a conventional synchronous transmission system module includes a first function module 10 performing a different STM-n signal matching function, a second function module 20 performing a switching function, And a system clock generation module 30 for generating a frame synchronization clock for transmission / reception of the function-specific modules 10 and 20.

The most common connection signals between the functional modules 10 and 20 that perform different functions include input data 11 and 21 which are input to the respective functional modules 10 and 20 and input data 11 and 21, A first reference frame synchronizing clock 31 which is generated by the system clock generating module 30 and is transmitted to the first function module, and a second reference frame synchronizing clock 31, which is input frame synchronizing clocks 13 and 23, A second reference data clock 33 generated by the system clock generation module 30 and transmitted to the second functional module and a second reference frame synchronous clock 34. [ The signals output from the modules 10 and 20 include data 14 and 24, data clocks 15 and 25, and frame synchronous clocks 16 and 26.

In this case, the general function of each frame synchronizing clock is to display the start position of the data frame and to frame synchronize the signal data based on the start position of the data frame.

In the synchronous transmission system, the synchronization of the data frames between the functional modules 10 and 20 is performed by using the reference frame synchronous clocks of 2 kHz or 8 kHz generated by the system clock generating module 30, 10, and 20, respectively.

In each functional module, data frames are aligned on the basis of the reference frame synchronous clocks 31 and 34 supplied from the system clock generating module 30, and a new starting point of a data frame is displayed on the basis of the sorted data frame, send.

At this time, due to the internal operation of the modules 10 and 20 for each function, the input data frames of the modules 10 and 20 for each function have different delay differences with respect to the frame synchronous clock transmitted from the system clock generating module 30 In each of the functional modules 10 and 20 for inputting data and interconnecting the data, the frame synchronous clocks 16 and 26 in the function module for transmission and reception are generated according to the delay difference by grasping the delay time from the frame synchronous clock Obtain synchronization between modules.

There are two conventional methods for implementing this function.

A conventional clock synchronizing method 1 for inter-module data frame alignment is a method for synchronizing data frames between modules by compensating a clock corresponding to a delay time in the system clock generating module 30 of FIG. 1, 20 to the reference frame synchronizing clocks 31, 34 for different transmission / reception.

A second frame synchronizing method, that is, a conventional clock synchronizing method 2 for inter-module data frame alignment, includes a first reference frame synchronizing clock 31 provided to each module in the system clock generating module 30 of FIG. 1, The first functional module 10 and the second functional module 20 transmit and receive frame synchronous clocks to the reference frame synchronous clock 34 in accordance with the delay time, A method of extracting from the conversion points of the clocks 31 and 34 is used.

The conventional clock synchronization method for data frame alignment will be described with reference to FIGS. 1, 2 and 3.

FIG. 2 is a clock configuration diagram of a conventional clock synchronization method 1 for inter-module data frame alignment, and FIG. 3 is a clock configuration diagram of a clock synchronization method 2 for inter-module data frame alignment. 1 and 2, the system clock generating module 30 of FIG. 1 includes reference frame synchronizing clocks 31 and 34 connected to the first function module 10 and the second function module 20, ) Are supplied with two frame synchronous clocks for transmission and reception in consideration of the signal delay difference.

2 (a) shows the input data clocks 12 and 22 of the first stage connected to the functional modules in synchronism with the data frame, and the first clock generator module 30 generated by the first-stage system clock generator module 30 10 and the first reference data clock 32 and the second reference data clock 33 of the first diagram supplied to the second function module 20 of FIG.

FIG. 2 (b) shows the first reference frame synchronizing clock 31 and the second reference frame synchronizing clock 34 generated in the same phase in the system clock generating module 30 of FIG. 1, Is a frame synchronous clock for transmission generated by the first functional module 10 and the second functional module 20. [

FIG. 2 (c) shows a reception frame synchronization clock for frame alignment upon reception of data in the first functional module 10 of FIG. 1, and a delay time delay based on the transmission frame synchronization clock (a) It exists at the point of consideration.

2 (d) is a received frame synchronous clock for frame synchronization when receiving a data frame in the second functional module 20 of FIG. 1, and the clock (b) Considering the time exists.

FIG. 3 shows a similarity to the signal structure of FIG. 2, but a frame synchronous clock is supplied to each functional module without supplying a frame synchronous clock for transmission and reception.

(A) of FIG. 3 shows input data clocks 12 and 22 of FIG. 1 connected to a functional module in synchronism with a data frame and a system clock generating module 30 of FIG. 1, The first and second reference data clocks 32 and 33 are generated.

3 (b) is a first reference frame synchronizing clock 31 provided to the first functional module 10 of the first diagram in the system clock generating module 30 of FIG. 1, and FIG. 3 (c) And the second reference frame synchronizing clock 34 provided by the second function module 20 of 1 degree is displayed.

The frame synchronization clock for transmission / reception is shifted from the transition point (rising and falling) of the signal cycle of the supplied reference frame synchronization clocks (b) and (c) Therefore, two frame synchronous clocks are generated during one period, one for transmission and the other for reception.

3 (d) is a frame synchronization clock for transmission / reception of the first functional module generated as described above, and the clock on the left side is the first reference frame synchronizing clock 31 ), That is, a transmission frame synchronous clock generated by receiving the frame (b) of FIG. 3, which is generated at a polling point of the reference frame synchronous clock (b) Is generated at the rising point of the reference frame synchronous clock (b) in consideration of the delay difference time in the second functional module (20) of FIG. 1 as the receiving frame synchronous clock of the frame synchronous clock (10). In this case, the up-conversion point of the reference frame synchronous clock provided in the first functional module 10 of FIG. 1 should take into account the delay difference time in the second functional module 20.

3 (e) is a frame synchronization clock for transmission / reception of the second function-specific module, and the clock on the left side corresponds to the second reference frame synchronous clock 34 in the second functional module 20 of the first diagram, (c), and the clock signal is generated at a down-conversion point of the reference frame synchronous clock (c), and the right clock is generated at the polling point of the reference frame synchronous clock (c) Is generated at the rising point of the reference frame synchronous clock (b) in consideration of the delay difference time in the first functional module (20) of FIG. 1 as the frame synchronous clock.

A conventional method for synchronizing a frame synchronous clock for data frame alignment as described above is as follows. In the synchronous method 1 of a conventional frame synchronous clock, a system clock generating module generates two frame (B) is requested as the frame synchronous clock for transmission, the second frame (c) is requested as the reception frame synchronous clock, and the synchronous clock is requested for the second function (B) of Fig. 2 is required as a frame synchronization clock for transmission, and (d) of Fig. 2 is required as a reception frame synchronization clock). In each of the functional modules performing other functions, The starting point of the reception frame synchronization clock supplied from the system clock generation module must be provided differently for each function module There is a disadvantage.

A conventional frame synchronization clock synchronization method 2, which is an advanced frame alignment method, is a method for extracting a frame clock for transmission / reception using a conversion point of a data clock in a receiving module. The method includes a system clock generation module, (D) of FIG. 3 is requested as the transmission / reception frame clock in the case of the first function module, and in the case of the second function module, the transmission / reception frame (E) of Figure 3 is required as clock.

However, in order to compensate for the delay difference of the signal depending on the function module by the processing of the signal, the system clock generating module generates the frame synchronous clock (Fig. 3 (b) and Fig. 3 (c) It is necessary to supply the light emitting diode.

Such a problem complicates the configuration of the system clock generation module and increases the number of connection signals between functional modules, which results in degrading the performance of the transmission system.

Therefore, the present invention solves the above-mentioned disadvantage in a DCS (Digitial Cross-connect System) synchronous system in which data frames are required to be aligned for switching, It is possible to easily construct the system clock generation module without supplying the frame synchronization clock for transmission / reception for each functional module in the system clock generation module, and by reducing the number of connection signal lines between the functional modules The objective is to facilitate the design of the whole system and reduce the manufacturing cost.

FIG. 1 is a block diagram of a conventional synchronous transmission system for inter-module data frame alignment,

FIG. 2 is a clock configuration diagram of a conventional clock synchronization method 1 for inter-module data frame alignment,

FIG. 3 is a clock configuration diagram of a conventional clock synchronization method 2 for inter-module data frame alignment,

FIG. 4 is a module diagram of a synchronous transmission system for inter-module data frame alignment according to an embodiment of the present invention,

FIG. 5 is a clock configuration diagram of a clock synchronization method for inter-module data frame alignment according to an embodiment of the present invention,

FIG. 6 is a circuit diagram of a frame synchronization clock for reception in the DCS synchronous system according to the embodiment of the present invention.

In order to achieve the above object, a frame synchronization clock generation circuit for reception in a DCS synchronous system provided in the present invention comprises a hexadecimal counter for operating a reference frame synchronous clock generated by a system clock generation module as a load signal, A second NOR gate for receiving the output signals Q4 through Q7 of the hexadecimal counter as inputs and a third NOR gate receiving the output signals Q8 through Q11 of the hexadecimal counter as inputs; A fourth NOR gate for receiving the output signals Q12 to Q15 of the hexadecimal counter as inputs, an AND gate for receiving the outputs of the first, second, third, and fourth NOR gates, And a D flip-flop for receiving the reference frame synchronous clock generated by the system clock generating module, and for receiving the frame synchronous clock It characterized in that it occurs.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

4 is a block diagram of a synchronous transmission system for inter-module data frame alignment according to an embodiment of the present invention. FIG. 5 is a block diagram of a clock synchronizing method for inter-module data frame alignment according to an embodiment of the present invention. to be.

Referring to FIG. 4, the DCS synchronous system including the receiving frame synchronizing clock generating circuit of the present invention includes a receiving frame synchronizing clock generating circuit 400, 500 for generating a receiving frame synchronizing clock in consideration of the time delay difference, And a system clock generation module 300 for supplying a common reference frame synchronization clock to the functional modules 100 and 200.

The frame clock synchronization method between the modules provided by the present invention will be described with reference to FIGS. 4 and 5. FIG.

5 (a) shows the data clocks 120 and 220 connected to the respective function modules 100 and 200 of FIG. 4 in synchronism with the data frame in the same manner as the conventional method, and the reference clocks generated by the system clock generating module 300 5 shows the data clocks 320 and 330 and the system clock generating module 300 of FIG. 5 shows the reference frame synchronizing clocks 310), the same clock is transmitted to different functional modules.

5 (c) is a timing chart showing the transmission frame synchronization of each functional module generated by receiving the reference frame synchronous clock 310 of FIG. 4, that is, FIG. 5 (b) Clock.

5 (d) is a reception frame synchronous clock of the first functional module 100 of FIG. 4 generated by the reception frame synchronous clock generation furnace 400 for generating the reception frame synchronous clock of FIG. 4 (E) of FIG. 5 is a receiving frame synchronizing clock of the second function-specific module 200 of FIG. 4 generated by the receiving frame synchronizing clock generating circuit 500 of the receiving frame synchronizing clock of FIG. In this case, (d) and (e) of FIG. 5 are generated by the receiving frame synchronous clock generating circuits 400 and 500 with the time delay difference in the function-specific modules 100 and 200 of FIG.

FIG. 6 is a circuit diagram of a frame synchronization clock for reception in the DCS synchronous system according to the embodiment of the present invention.

FIG. 6 is a circuit configured when the reference frame synchronous clock of each of the functional modules 100 and 200 of FIG. 4 is 2 kHz, and the input data clock for generating the reception frame synchronous clock and the reference data clock are 20 kHz.

Referring to FIG. 6, the receiving frame synchronizing clock generating circuit 400, 500 of FIG. 4 includes a reference frame synchronizing clock generated by the system clock generating module 300 of FIG. 4 as a hexadecimal counter A first NOR gate 62 for receiving the output signals Q0 to Q3 of the hexadecimal counter 61 and a second NOR gate 62 for receiving the output signals Q4 to Q7 of the hexadecimal counter 61, A third NOR gate 64 for receiving the output signals Q8 to Q11 of the hexadecimal counter 61 and a fourth NOR gate 64 for receiving the output signals Q12 to Q15 of the hexadecimal counter 61, An AND gate 66 for receiving the outputs of the first, second, third and fourth NOR gates 62, 63, 64 and 65, And a D flip-flop 67 which operates based on the reference frame synchronous clock generated by the system clock generating module 300, And generates a credit frame synchronous clock.

Referring to FIG. 6, when the time delay difference between the reference frame synchronizing clock and the input frame synchronizing clock of the system clock generating unit is nine cycles in total, for example, the frame counter synchronizing clock, which operates as a load signal, 61) is reset, the counter is sequentially counted by the reference data clock.

At this time, since the first NOR gate 62 receives Q0 to Q3, the counter frequency dividing period is 24-1 = 15 so that the gate output signal becomes 1 when a time difference up to 15 cycles occurs do. Since the second NOR gate 63 receives Q4 through Q7, the counter division period becomes 27-1 = 255, and the gate output signal becomes 1 when a time difference up to 255 cycles occurs. The other third and fourth NOR gates 64 and 65 also have the same concept that the NOR gate output signal becomes 1 when a time difference occurs.

Accordingly, when the delay difference of 8 periods occurs, 2 ³ = 8, so that the value of the Q 3 signal of the output of the hexadecimal counter 61 is 1, so that the first NOR gate 1 62 inputs the Q 3 signal You can invert it. In this case, the period during which the Q3 signal is inverted in the first NOR gate 62 and a signal of 0 is generated at the input of the first NOR gate 62 may be for a number of periods of the reference data clock, Q1, Q2, and Q3 are 0, 0, 0, and 1, respectively, since the other input signals (Q0, Q1, Q2) do.

The outputs of the AND gates 66 and 66 are in a state of 1 because the states of the output signals Q4 to Q15 of all the counters of the second, third and fourth NOR gates 63, 64 and 65 are 0, Only when the delay difference of 8 cycles occurs when the output of the first NOR gate 62 becomes 1.

After the hexadecimal counter 61 is reset by the frame synchronous clock of 2 kHz generated in the system clock generating module 300 of FIG. 4, the frame synchronous clock is counted by the reference data clock and the frame synchronous clock of 2 kHz is generated again. The counter 61 is reset.

At this time, if a frame synchronous clock of 2 kHz occurs during the counting of 2 ¹⁶ magnitudes, each counting condition exists uniquely by one period of the reference data clock.

In the circuit of FIG. 6, the D-flip flop 67 is used to eliminate the delay of the operation of the AND gate 66 and latches the output of the AND gate 66 by the reference data clock, The signal of one cycle is further delayed with respect to the reference data clock.

Accordingly, in the circuit operation of FIG. 6, when receiving a signal having a signal delay difference of 9 cycles between the reference frame synchronizing clock and the input data frame, the receiving module generates a frame synchronizing clock for frame alignment in a form synchronized with the reference data clock .

If the delay difference occurs for 18 cycles, the input of the NOR gate in the circuit of FIG. 6 is inverted to 17 cycles in order to generate the reception frame synchronous clock.

Therefore, if the Q4 signal of 2 ⁴ = 16 and the Q0 signal of 2 ⁰ = 1 are inverted, the frame sync clock can be synchronized.

In this case, in the circuit according to the embodiment of the present invention, generation of a frame synchronous clock for frame alignment is performed in the same manner as that in the case of generating the delay difference of 9 cycles, and a randomly generated delay The output signals Q0 to Q15 of the hexadecimal counter are inverted before the NOR gate input in consideration of the difference so that the synchronized reception frame synchronous clock can be generated.

In this case, the first, second, third, and fourth NOR gates in the configuration of the reception frame synchronous clock generation circuit of FIG. 6 may be replaced with a combination of other logical operators performing the same function.

As described above, by using the frame synchronization clock generation circuit for reception in the DCS synchronous system of the present invention, in the data connection between functional modules of the synchronous transmission system in which different STM-n signals are matched and data frame alignment is required The delay difference of the data frame arbitrarily generated for each matching module can be easily modified with a simple configuration and the system clock generating module does not need to supply the frame synchronous clock for transmission / reception for each functional module.

In addition, the configuration of the system clock generation module can be simplified, and the number of connection signal lines between the functional modules can be reduced, thereby facilitating the design of the entire system and reducing the manufacturing cost.

Claims (2)

A DCS synchronous system for performing a switching function, the system comprising: a hex counter for operating a reference frame synchronous clock generated by a system clock generating module as a load signal; A first NOR gate receiving the output signals Q0 through Q3 of the hexadecimal counter as inputs; A second NOR gate receiving the output signals Q4 through Q7 of the hexadecimal counter as inputs; A third NOR gate receiving the output signals Q8 through Q11 of the hexadecimal counter as inputs; A fourth NOR gate receiving the output signals Q12 through Q15 of the hexadecimal counter as inputs; An AND gate having inputs of the outputs of the first, second, third, and fourth NOR gates; And a D flip-flop for receiving an output of the AND gate and a reference frame synchronous clock generated by the system clock generating module, and generating a reception frame synchronous clock in consideration of a time delay difference. A frame synchronous clock generation circuit for receiving in a system. 2. The DCS synchronous system according to claim 1, wherein the first, second, third, and fourth NOR gates can be replaced by a combination of other logical operators performing the same function as the first, second, third and fourth NOR gates. Circuit.