CN118573187A - Frequency dividing circuit and digital signal processing circuit - Google Patents

Abstract

The present application discloses a frequency division circuit and a digital signal processing circuit, wherein the frequency division circuit includes: a phase-locked loop, for generating a first frequency division signal and a second frequency division signal according to an input clock signal; a first delay module, the input end of the first delay module is connected to the output end of the phase-locked loop, for generating a first delay signal corresponding to the first frequency division signal according to the asynchronous clock signal corresponding to the first frequency division signal and the input clock signal; a gating module, the input end of the gating module is respectively connected to the output end of the first delay module and the output end of the phase-locked loop, for generating a fractional frequency division signal according to the first frequency division signal, the second frequency division signal and the first delay signal. The present application realizes the fractional frequency division function by cooperating with the phase-locked loop through the structural setting of the first delay module and the gating module, thereby reducing the influence of the complex circuit structure of multiple gating gates in the frequency division circuit on the signal transmission rate.

Description

A frequency division circuit and a digital signal processing circuit

Technical Field

The present application relates to the technical field of digital circuit design, and in particular to a frequency division circuit and a digital signal processing circuit.

Background Art

Frequency divider circuit is a circuit widely used in the field of electronics. Its main function is to distribute the frequency of the input signal to the output port according to a specific ratio. This circuit plays an important role in many electronic devices, such as electronic clocks, frequency synthesizers, audio systems, digital systems and communication systems.

Fractional frequency division is often required in optical communications and interfaces with transmission rates of 16Gbps and above. Since the transmission rate of 16Gbps and above is a high transmission rate, the signal frequency division must be completed by the cooperation of modules such as gates and triggers. However, in existing fractional frequency division circuits, multiple gates are often required to work together to achieve fractional frequency division, which leads to a complex circuit structure. At the same time, more gates will also affect the signal transmission rate of the circuit.

Therefore, there is an urgent need for a relatively simple circuit that can implement fractional frequency division to solve the above technical problems.

Summary of the invention

In order to solve the above technical problems, the embodiments of the present application provide a frequency division circuit and a digital signal processing circuit.

According to one aspect of an embodiment of the present application, a frequency division circuit is provided, including: a phase-locked loop, for generating a first frequency division signal and a second frequency division signal according to an input clock signal; a first delay module, the input end of the first delay module is respectively connected to the output end of the phase-locked loop, and is used to generate a first delay signal corresponding to the first frequency division signal according to the first frequency division signal and an asynchronous clock signal corresponding to the input clock signal; a gating module, the input end of the gating module is respectively connected to the output end of the first delay module and the output end of the phase-locked loop, and is used to generate a fractional frequency division signal according to the first frequency division signal, the second frequency division signal and the first delay signal.

In some embodiments of the present application, the phase-locked loop includes: a frequency modulation module, which is used to generate a first frequency-divided signal and a second frequency-divided signal according to an input target signal; a pulse module, wherein the input end of the pulse module is connected to the output end of the frequency modulation module, and the output end of the pulse module is connected to the input end of the frequency modulation module, and is used to generate a pulse signal according to the first frequency-divided signal, the second frequency-divided signal and an input clock signal, and generate the target signal according to the pulse signal and the clock signal, and input the target signal to the frequency modulation module.

In some embodiments of the present application, the frequency modulation module includes a first frequency divider, a second frequency divider and a third frequency divider connected in sequence; the first frequency divider is used to divide the input target signal to obtain an initial frequency divided signal; the second frequency divider is used to divide the initial frequency divided signal to obtain the first frequency divided signal; the third frequency divider is used to divide the first frequency divided signal to obtain the second frequency divided signal.

In some embodiments of the present application, the first frequency divider has the same frequency division multiple as the second frequency divider, and the third frequency divider has a different frequency division multiple than the second frequency divider.

In some embodiments of the present application, the pulse module includes a second delay module, which is used to generate a second delay signal based on the first frequency division signal and the clock signal, so that the pulse module generates the pulse signal based on the second delay signal, the first frequency division signal and the second frequency division signal.

In some embodiments of the present application, the pulse module also includes an OR-NOT operation module and an AND-NOT operation module; the OR-NOT operation module is used to perform an OR-NOT operation on the second delayed signal and the second frequency-divided signal input into the OR-NOT operation module to obtain a supplementary frequency-divided signal; the AND-operation module is used to perform an AND-operation on the supplementary frequency-divided signal and the first frequency-divided signal input into the AND-operation module to obtain the pulse signal.

In some embodiments of the present application, the frequency division circuit includes a negation module for performing a negation operation on an input clock signal to obtain the asynchronous clock signal, and outputting the asynchronous clock signal to the first delay module.

In some embodiments of the present application, the frequency division circuit includes an OR operation module, which is used to perform an OR operation on a pulse signal and a clock signal input to the OR operation module to obtain a target signal.

In some embodiments of the present application, the gating module includes a multiplexer for outputting the fractional frequency-divided signal based on the control of the second frequency-divided signal among the first frequency-divided signal and the first delayed signal.

According to another aspect of an embodiment of the present application, a digital signal processing circuit is provided, comprising the frequency division circuit as described above.

In the above embodiment, based on the initialized belt tension, the correction effect of the corresponding correction frequency when calibrating the transmission component is improved.

In the technical solution of the embodiment of the present application, the above invention content can at least bring the following beneficial effects: the first frequency division signal and the second frequency division signal generated by the phase-locked loop are combined with the first delay signal generated by the first delay module as the input of the gating module, and the corresponding fractional frequency division signal is obtained based on the gating module; by setting the digital circuit structure of the first delay module and the gating module, and coordinating it with the phase-locked loop, the fractional frequency division signal can be generated, thereby reducing the influence of the complex digital circuit structure in the frequency division circuit on the signal transmission rate.

BRIEF DESCRIPTION OF THE DRAWINGS

The drawings herein are incorporated into the specification and constitute a part of the specification, showing embodiments consistent with the present application, and together with the specification, are used to explain the principles of the present application. Obviously, the drawings described below are only some embodiments of the present application, and for those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative work. In the drawings:

FIG. 1 is a schematic diagram of an overall circuit framework of a frequency division circuit shown in an exemplary embodiment of the present application.

FIG. 2 is a schematic diagram of the circuit structure of a first delay module shown in an exemplary embodiment of the present application.

FIG. 3 is a schematic diagram of a circuit structure of a gating module according to an exemplary embodiment of the present application.

FIG. 4 is a schematic diagram of a circuit structure of a phase-locked loop according to an exemplary embodiment of the present application.

FIG. 5 is a schematic diagram of a circuit structure of a frequency modulation module according to an exemplary embodiment of the present application.

FIG6 is a schematic diagram of a circuit structure of a frequency modulation module according to another exemplary embodiment of the present application.

FIG. 7 is a schematic diagram of a circuit structure of a pulse module according to an exemplary embodiment of the present application.

FIG8 is a schematic diagram of a circuit structure of a pulse module according to another exemplary embodiment of the present application.

FIG. 9 is a schematic diagram of a circuit structure of a phase-locked loop according to another exemplary embodiment of the present application.

FIG. 10 is a schematic diagram of the overall circuit structure of a frequency division circuit shown in an exemplary embodiment of the present application.

DETAILED DESCRIPTION

In order to make the purpose and implementation method of the present application clearer, the exemplary implementation method of the present application will be clearly and completely described below in conjunction with the drawings in the exemplary embodiments of the present application. Obviously, the described exemplary embodiments are only part of the embodiments of the present application, rather than all the embodiments.

It should be noted that the brief description of terms in this application is only for the convenience of understanding the embodiments described below, and is not intended to limit the embodiments of this application. Unless otherwise specified, these terms should be understood according to their ordinary and common meanings.

The terms "first", "second", "third", etc. in the specification and claims of this application and the above drawings are used to distinguish similar or similar objects or entities, and do not necessarily mean to limit a specific order or sequence, unless otherwise noted. It should be understood that the terms used in this way can be interchangeable under appropriate circumstances.

The terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover but not exclude inclusion, for example, a product or device comprising a list of components is not necessarily limited to all the components expressly listed but may include other components not expressly listed or inherent to such product or device.

It should be noted that the "multiple" mentioned in this article refers to two or more. "And/or" describes the association relationship of the associated objects, indicating that there can be three relationships. For example, A and/or B can mean: A exists alone, A and B exist at the same time, and B exists alone. The character "/" generally indicates that the associated objects before and after are in an "or" relationship.

Fig. 1 is a schematic diagram of the overall circuit framework of a frequency division circuit shown in an exemplary embodiment of the present application. As shown in Fig. 1, the frequency division circuit 100 of the present application includes a phase-locked loop 110, a first delay module 120 and a gating module 130, and each part is introduced in detail one by one through the following embodiments.

The phase-locked loop 110 is used to generate a first frequency-divided signal and a second frequency-divided signal according to an input clock signal.

It should be noted that the input clock signal can be generated by a preset clock generator, which uses an oscillator that can provide a square wave output to generate the clock signal. The oscillator circuit always uses feedback to make the oscillator oscillate. By feeding back the corresponding parameters, the oscillator works at a specific frequency to ensure that the related electronic components can operate synchronously.

The phase-locked loop 110 can generate a first frequency-divided signal and a second frequency-divided signal according to the input clock signal. It can be regarded that a digital frequency-dividing circuit 100 for realizing signal frequency division is provided in the corresponding circuit structure of the phase-locked loop 110. For example, the digital frequency-dividing circuit 100 is an electronic clock, and the frequency-dividing circuit 100 is used to divide a high-frequency crystal oscillator signal into a low-frequency clock signal.

By setting the phase-locked loop 110, it is possible to ensure that the clock signals between different modules or devices remain consistent, thereby avoiding data drift and communication errors.

The first delay module 120 has an input end connected to the output end of the phase-locked loop 110 and is used to generate a first delay signal corresponding to the first frequency-divided signal according to the first frequency-divided signal and an asynchronous clock signal corresponding to the input clock signal.

It should be noted that in the frequency division circuit 100 of the present application, due to the consistency of the clock signal, the input end of the first delay module 120 can not only be connected to the output end of the phase-locked loop 110, but also can be connected to the input end of the phase-locked loop 110, so that the clock signal corresponding to the asynchronous clock signal at the input end of the phase-locked loop 110 is consistent with the clock signal at the input end of the first delay module 120.

The first delay module 120 may be a D flip-flop, and generates a first delay signal based on the delay function of the D flip-flop, which is mainly reflected in the sampling of the input signal and the retention of the output signal by the D flip-flop. Specifically, the D flip-flop samples the input signal at the rising edge (or falling edge, depending on the type and design of the flip-flop) of the clock signal, and keeps the sampled data unchanged in the next cycle of the clock signal, thereby achieving a delay of one clock cycle.

For example, FIG2 is a schematic diagram of the circuit structure of the first delay module shown in the exemplary embodiment of the present application. As shown in FIG2, when the rising edge (or falling edge) of the clock signal CLK arrives, the D flip-flop samples the data at the D input terminal. The sampled data will be stored inside the flip-flop and remain unchanged in the next cycle of the clock signal. Therefore, from the D input terminal to the Q output terminal (or There will be a delay of one clock cycle in the signal transmission of the output end.

Of course, the delay function of the first delay module 120 can also be implemented through other circuit structures.

For example, a latch can store input data and keep the data for a certain period of time under the control of an enable signal or a clock signal, which is similar to the function of a D flip-flop updating data at the clock edge and keeping the new state. Therefore, the D flip-flop in the above example can be replaced accordingly based on a latch and an adaptation circuit.

Another example is a register. The register uses its internal trigger (such as a D trigger) to achieve data storage and delay. Under the control of the clock signal, the register can receive input data and store it in the internal trigger at the clock edge, thereby achieving data delay processing. Similarly, the D trigger in the above example can be replaced accordingly based on the register and the adaptation circuit.

Another example is a shift register. The shift register realizes data storage and transmission through its internal trigger. Driven by the clock signal, data can be transmitted in sequence between the triggers, thereby realizing data delay and shift processing. This delay characteristic is essentially similar to the delay function of the D trigger, both of which are based on the synchronization of the clock signal and the storage and transmission of data. Similarly, the D trigger in the above example can be replaced accordingly based on the shift register and the adaptation circuit.

In addition, a circuit having a certain similarity in function and effect to the delay characteristics of a D flip-flop can also be used as a replacement, which is only an exemplary description and is not specifically limited. In addition, this application mainly uses a D flip-flop to implement the above delay function. In other embodiments, if there is no specific description, the delay module used therein can also use a D flip-flop to implement the corresponding function.

When in use, based on the implementation principle of the D flip-flop, the first frequency-divided signal and the asynchronous clock signal corresponding to the input clock signal are used as inputs of the D flip-flop to generate a first delayed signal corresponding to the first frequency-divided signal.

The gating module 130 has an input end connected to the output end of the first delay module 120 and the output end of the phase-locked loop 110 respectively, and is used to generate a fractional frequency-divided signal according to the first frequency-divided signal, the second frequency-divided signal and the first delay signal.

Specifically, the gating module 130 may be a multiplexer configured to output a fractional frequency-divided signal based on the control of the second frequency-divided signal among the first frequency-divided signal and the first delayed signal.

Taking the multiplexer in FPGA (Field Programmable Gate Array) as an example, FPGA devices contain basic resources such as programmable logic blocks CLB (Configurable Logic Blocks), wiring resources and programmable input/output modules. Among them, the programmable logic block is the basic unit for realizing user functions, which includes an interconnected switch matrix and multiple components. Each component unit also includes components such as look-up table LUT (Look-Up-Table), trigger and multiplexer. In FPGA, the multiplexer serves as a bridge connecting various wiring tracks and programmable logic blocks, and has a great impact on the performance and power consumption of FPGA.

Explanation is made exemplarily, FIG3 is a schematic diagram of the circuit structure of the gating module shown in the exemplary embodiment of the present application. As shown in FIG3, the multiplexer of the present application can be a 2-to-1 multiplexer, and the 2-to-1 multiplexer has two input terminals and an output terminal, and is controlled by a selection signal line to select one of the input signals to be transmitted to the output terminal. This multiplexer is suitable for simple data selection and signal switching. Among them, the signals input by the two input terminals can be a first frequency division signal and a first delay signal, and the signal input by the selection signal line is a second frequency division signal. The output terminal is used to output a fractional frequency division signal.

Through the above-mentioned implementation mode, the technical solution of the present application combines the first frequency division signal and the second frequency division signal generated by the phase-locked loop 110 with the first delay signal generated by the first delay module 120 as the input of the selection module 130, and obtains the corresponding fractional frequency division signal based on the selection module 130; through the structural setting of the first delay module 120 and the selection module 130, it can cooperate with the phase-locked loop 110 to realize the fractional frequency division function, thereby reducing the influence of the complex circuit structure of multiple selection gates in the circuit on the signal transmission rate.

In some embodiments of the present application, an asynchronous clock signal corresponding to the clock signal may be obtained by setting a non-operation module in the frequency division circuit 100 for calculation.

Specifically, the frequency division circuit 100 may further include a non-operation module, the output end of the non-operation module is connected to the input end of the first clock module, and is used to perform a non-operation on the input clock signal to obtain an asynchronous clock signal, and output the asynchronous clock signal to the first delay module 120.

In order to ensure the consistency of the clock signal, the input end of the non-operation module is connected to the input port of the phase-locked loop 110 for inputting the clock signal.

In some embodiments of the present application, Fig. 4 is a schematic diagram of a circuit structure of a phase-locked loop shown in an exemplary embodiment of the present application. As shown in Fig. 4, the phase-locked loop 110 may include a frequency modulation module 140 and a pulse module 150, and the frequency modulation module 140 and the pulse module 150 are connected end to end to form a loop.

Specifically, the frequency modulation module 140 is used to generate a first frequency-divided signal and a second frequency-divided signal according to an input target signal.

The pulse module 150, the input end of the pulse module 150 is connected to the output end of the frequency modulation module 140, and the output end of the pulse module 150 is connected to the input end of the frequency modulation module 140, and is used to generate a pulse signal according to the first frequency division signal, the second frequency division signal and the input clock signal, and generate a target signal according to the pulse signal and the clock signal, and input the target signal to the frequency modulation module 140.

The frequency modulation module 140 is a circuit structure that can realize the frequency division function, and its main function is to transform the frequency of the input signal to generate an output signal with a specific frequency. The frequency of these output signals can be an integer multiple or fraction of the frequency of the input signal. For example, the frequency division circuit 100 is used in multiple usage scenarios such as clock signal generation, wireless communication, digital signal processing, audio system, video processing, etc.

In some usage scenarios, the output frequency of the frequency modulation module 140 is an integer fraction of the input frequency, for example, 2-division, 4-division, etc. In other usage scenarios, the output frequency of the frequency modulation module 140 can also be a non-integer fraction of the input frequency, for example, 3/4-division, 5/9-division, etc. For specific usage scenarios, whether integer division or fractional division is selected needs to be adaptively adjusted according to the actual needs of the fractional division signal. At the same time, adaptive adjustments can also be made in combination with hardware costs.

For example, in a digital circuit, a common method for implementing frequency division is to use a D flip-flop or a counter. For example, even frequency division can be implemented by cascading D flip-flops; for odd frequency division, it can be implemented by a state machine or a counter combined with a logic gate circuit. In addition, a programmable logic device (such as an FPGA) can also be used to implement a more complex frequency division circuit 100. The frequency modulation module 140 of the present application can use a cascade of D flip-flops to implement even frequency division.

Since the frequency modulation module 140 and the pulse module 150 cooperate with each other to form a loop, during use, the pulse module 150 generates a pulse signal according to the input first frequency division signal, the second frequency division signal and the clock signal, wherein the first frequency division signal and the second frequency division signal are generated by the frequency modulation module 140. At the same time, the generated pulse signal and the clock signal are combined with the specified logic gate for calculation to obtain the target signal, and the generated target signal is input into the frequency modulation module 140, that is, the phase-locked loop 110 is formed.

Through the above-mentioned implementation, the phase-locked loop 110 formed based on the frequency modulation module 140 and the pulse module 150 can automatically adjust the frequency and phase of the output signal so as to keep it synchronized or locked with the frequency and phase of the input signal, so that the pulse signal of the present application can ensure the stability and consistency of the signal by automatically adjusting the frequency and phase of the output signal.

In some embodiments of the present application, Fig. 5 is a schematic diagram of the circuit structure of the frequency modulation module shown in an exemplary embodiment of the present application. As shown in Fig. 5, the frequency modulation module 140 is further exemplarily described, and the frequency modulation module 140 may include a first frequency divider, a second frequency divider, and a third frequency divider connected in sequence.

Among them, the first frequency divider is used to divide the input target signal to obtain an initial frequency divided signal; the second frequency divider is used to divide the initial frequency divided signal to obtain a first frequency divided signal; the third frequency divider is used to divide the first frequency divided signal to obtain a second frequency divided signal.

In detail, FIG6 is a schematic diagram of the circuit structure of the frequency modulation module shown in another exemplary embodiment of the present application. As shown in FIG6, the first frequency divider, the second frequency divider and the third frequency divider can all be D flip-flops. Since the D flip-flop is a digital circuit element with a memory function, its output state Q will be updated according to the value of the input signal D when the rising edge (or falling edge, depending on the specific flip-flop type) of the clock signal CLK (Clock) arrives. That is, if D is high when the rising edge of CLK arrives, Q becomes high; if D is low, Q becomes low.

Based on the basic principle of the D flip-flop mentioned above, when the D flip-flop is used as a frequency divider, the frequency of the input signal is reduced to an integer fraction of the original frequency. The frequency division function can be easily realized by utilizing the memory function and clock sensitivity of the D flip-flop.

Specifically, a basic divider can be formed by feeding back the output Q of the D flip-flop to its input D. This is because whenever the rising edge of CLK arrives, the value of Q is reversed, thus achieving the effect of halving the frequency.

For example, the basic divide-by-two frequency divider described above requires only the Q terminal of a D flip-flop to be connected to the D terminal.

For another example, for a higher frequency division, it can be achieved by cascading multiple D flip-flops. For example, to achieve a frequency division of four, two frequency dividers can be connected in series; to achieve a frequency division of eight, another frequency divider can be connected in series. And so on, no further elaboration is given.

Of course, when setting a relatively complex divider through a D flip-flop, for example, for a frequency division that is not a power of 2, such as three-way frequency division, five-way frequency division, etc., it can also be implemented in combination with a counter or more complex combinational logic.

Through the above implementation, the frequency modulation module 140 is composed of multiple sub-dividers in a cascade manner, so that the implementation principle of the frequency modulation module 140 is simpler than the frequency modulation module 140 set up by a complex circuit structure. At the same time, the flexibility of combining different sub-dividers is improved, and it is easy to expand, so as to facilitate adaptive adjustment when the frequency modulation module 140 is required to achieve different division multiples.

In some embodiments of the present application, the first frequency divider and the second frequency divider have the same frequency division multiple, and the third frequency divider and the second frequency divider have a different frequency division multiple.

For example, a cascade of D flip-flops is used to achieve frequency division of a target multiple, wherein the target multiple can be determined according to the number of cascaded D flip-flops and the corresponding frequency division multiple. As shown in FIG6 , since the purpose of the frequency modulation module 140 of the present application is to generate a first frequency division signal and a second frequency division signal, the first frequency divider of the present application can be a four-frequency divider, the second frequency divider can also be a four-frequency divider, and the third frequency divider can be a two-frequency divider. Among them, the four-frequency divider can be obtained by connecting two two-frequency dividers in series, or it can be composed of electronic components such as D flip-flops and logic gates in the form of other digital circuits.

Of course, the frequency modulation module 140 of the present application may also be composed of a sixteen-frequency divider and a two-frequency divider.

Based on this, in actual use, frequency dividers with different multiples can be packaged. For example, based on a two-frequency divider, a two-frequency divider, a four-frequency divider, an eight-frequency divider, etc. can be set respectively. In use, if the frequency division multiple of the frequency divider to be used is eight times, an eight-frequency divider can be directly used, or a two-frequency divider and a four-frequency divider can be cascaded, or three two-frequency dividers can be cascaded. For example, in a use scenario of the frequency modulation module 140 of the present application, when using the frequency division circuit 100 of the present application, if it is necessary to set a switch circuit to switch the frequency division multiple of the frequency modulation module 140, it can be combined based on different frequency division multiples.

Through the above implementation, the frequency divider inside the frequency modulation module 140 can be adaptively packaged according to needs, which can improve the reliability and design quality of the product, realize the distribution and isolation of product functions, and make it easier to discover problems and improve designs.

In some embodiments of the present application, FIG7 is a schematic diagram of the circuit structure of the pulse module shown in an exemplary embodiment of the present application. As shown in FIG7, the pulse module 150 is further exemplarily described, and the pulse module 150 includes a second delay module, and the second delay module is used to generate a second delay signal according to the first frequency division signal and the clock signal, so that the pulse module 150 generates a pulse signal according to the second delay signal, the first frequency division signal and the second frequency division signal.

Specifically, the second delay module may use the same D flip-flop as the first delay module 120 , or a delay circuit different from the first delay module 120 .

For example, a delay module is set in the pulse module 150 to delay DIV16 by one original input clock cycle, and then the delayed DIV16 signal is OR-NON operated with the DIV32 signal. Based on the output of the OR-NON operation, an AND operation is performed with the original DIV16, and finally a cycle of 33Tclk is generated.

Among them, DIV16 represents the first frequency-divided signal, which can be regarded as a sixteen-frequency-divided signal; DIV32 represents the second frequency-divided signal, which can be regarded as a thirty-two-frequency-divided signal; 33Tclk represents the pulse signal generated according to the first frequency-divided signal, the second frequency-divided signal and the input clock signal, which can also be regarded as a thirty-three-frequency-divided signal through delay processing.

Through the above implementation, when processing the signal entering the frequency modulation module 140, an additional cycle length is inserted into the normal input signal cycle time through the second delay module, thereby adding an additional frequency division to the input frequency division signal of the frequency modulation module 140 to facilitate the generation of a fractional frequency division signal.

In some embodiments of the present application, FIG8 is a schematic diagram of the circuit structure of a pulse module shown in another exemplary embodiment of the present application. As shown in FIG8, the pulse module 150 generates a pulse signal according to the second delay signal, the first frequency division signal and the second frequency division signal. In order to implement the digital operation process exemplified in the above-mentioned pulse module 150, the pulse module 150 is further described, and the pulse module 150 also includes an NOR operation module and an AND operation module.

Among them, the NOR operation module is used to perform an NOR operation on the second delayed signal and the second frequency-divided signal input to the NOR operation module to obtain a supplementary frequency-divided signal; the AND operation module is used to perform an AND operation on the supplementary frequency-divided signal and the first frequency-divided signal input to the AND operation module to obtain a pulse signal.

Specifically, the input end of the OR operation module is connected to the output end of the second delay module, and the output end of the OR operation module is connected to the input end of the AND operation module.

In some embodiments of the present application, Fig. 9 is a schematic diagram of a circuit structure of a phase-locked loop shown in another exemplary embodiment of the present application. As shown in Fig. 9, in combination with the phase-locked loop 110 in the above embodiment, a target signal is generated according to a pulse signal and a clock signal, and the target signal is input to the frequency modulation module 140, which may at least include the following contents.

Specifically, the phase-locked loop 110 also includes an OR operation module, the input end of the OR operation module is connected to the output end of the pulse module 150, and the output end of the OR operation module is connected to the input end of the frequency modulation module 140, which is used to perform an OR operation on the pulse signal and the clock signal input to the OR operation module to obtain the target signal.

Similarly, in order to ensure the consistency of the clock signal, the input end of the OR operation module is connected to the port of the phase-locked loop 110 for inputting the clock signal.

Fig. 10 is a schematic diagram of the overall circuit structure of a frequency division circuit shown in an exemplary embodiment of the present application. As shown in Fig. 10, in order to more clearly disclose the technical solution of the present application, combined with multiple embodiments in the above content, further exemplary description is given through the following content.

As shown in FIG10 , the symbols in the figure are described as follows:

First, the Pulse block shown in the figure represents the pulse module 150; the DIV block shown in the figure represents the frequency modulation module 140; the D flip-flop shown in the figure represents the first delay module 120; and the MUX gating module 130 shown in the figure.

Second: CLK shown in the figure represents the clock signal; ln1 and a0 shown in the figure both represent the first frequency-divided signal, corresponding to the sixteen-frequency-divided signal; ln2 shown in the figure represents the second frequency-divided signal, corresponding to the 32-frequency-divided signal; Pulse shown in the figure represents the pulse signal; In shown in the figure represents the target signal; a1 shown in the figure represents the first delay signal.

Before the clock signal enters the frequency modulation module 140, an extra cycle length is inserted into the 32 normal input signal cycle times based on the second delay module set in the pulse module 150, thereby achieving 32-frequency division of the input of the frequency modulation module 140, that is, 33-frequency division of the original signal.

Specifically, the technical solution of the present application can be divided into three parts for explanation. In the first part, the original input signal is processed so that an additional original input signal cycle can be inserted when the processed signal is divided by 32; in the second part, a divider chain is formed based on multiple cascaded dividers in the frequency modulation module 140, including 4/16/32 division. In the third part, the 16-division signal with different delays is selected by the 32-division signal to obtain 16.5 division to achieve the acquisition of the fractional division signal.

Further, an exemplary description is given in conjunction with the internal digital operation circuit;

First, for the pulse module 150, DIV16 is delayed by one original input clock cycle, and then the delayed DIV16 signal is OR-not operated with the DIV32 signal, and the OR-not output is then AND-operated with the original DIV16, ultimately generating a pulse signal with a cycle of 33Tclk but a high-level pulse width of only one cycle. This pulse signal, when OR-operated with the original clock, can generate the required target signal with an additional cycle length inserted within 32 cycles.

Secondly, the target signal is input to the frequency modulation module 140 for frequency division by 4, 16, and 32. Due to the delay processing in the pulse module 150, the 32-frequency divided signal is actually a 33-frequency divided signal, and the frequency of the 16-frequency divided signal is changing, not a true 16.5-frequency divided signal.

Finally, the 16-frequency-divided signal and the 16-frequency-divided signal delayed by half a clock cycle are gated by the gating module 130 and DIV32, so that a real 16.5-frequency-divided signal can be generated.

In some embodiments of the present application, the present application further discloses a digital signal processing circuit, which includes the frequency division circuit 100 disclosed in any of the above embodiments.

Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

For the convenience of explanation, the above description has been made in conjunction with specific embodiments. However, the above exemplary discussion is not intended to be exhaustive or limit the embodiments to the specific forms disclosed above. Based on the above teachings, various modifications and variations can be obtained. The selection and description of the above embodiments are to better explain the principles and practical applications, so that those skilled in the art can better use the embodiments and various different variations of the embodiments suitable for specific use considerations.

Claims (10)

1. A frequency dividing circuit, comprising:

a phase-locked loop for generating a first frequency-divided signal and a second frequency-divided signal according to an input clock signal;

The input end of the first delay module is connected with the output end of the phase-locked loop and is used for generating a first delay signal corresponding to the first frequency-dividing signal according to the asynchronous clock signal corresponding to the first frequency-dividing signal and the input clock signal;

and the input end of the gating module is respectively connected with the output end of the first delay module and the output end of the phase-locked loop and is used for generating a decimal frequency division signal according to the first frequency division signal, the second frequency division signal and the first delay signal.

2. The frequency divider circuit of claim 1, wherein the phase-locked loop comprises:

the frequency modulation module is used for generating a first frequency division signal and a second frequency division signal according to an input target signal;

The input end of the pulse module is connected with the output end of the frequency modulation module, and the output end of the pulse module is connected with the input end of the frequency modulation module and is used for generating a pulse signal according to the first frequency division signal, the second frequency division signal and the input clock signal, generating the target signal according to the pulse signal and the clock signal and inputting the target signal to the frequency modulation module.

3. The frequency divider circuit of claim 2, wherein the frequency modulation module comprises a first frequency divider, a second frequency divider, and a third frequency divider connected in sequence;

The first frequency divider is used for dividing the frequency of the input target signal to obtain an initial frequency-divided signal;

the second frequency divider is used for dividing the frequency of the initial frequency division signal to obtain the first frequency division signal;

the third frequency divider is configured to divide the first frequency division signal to obtain the second frequency division signal.

4. The frequency dividing circuit of claim 3, wherein the first frequency divider is the same frequency division multiple as the second frequency divider, and wherein the third frequency divider is different from the second frequency divider.

5. The frequency divider circuit of claim 2, wherein the pulse module comprises a second delay module configured to generate a second delay signal based on the first frequency divided signal and the clock signal, such that the pulse module generates the pulse signal based on the second delay signal, the first frequency divided signal, and the second frequency divided signal.

6. The frequency divider circuit of claim 5, wherein the pulse module further comprises a nor operation module and an and operation module; the nor operation module is used for performing nor operation on the second delay signal and the second frequency division signal input into the nor operation module so as to obtain a supplementary frequency division signal; the AND operation module is used for performing AND operation on the complementary frequency division signal and the first frequency division signal which are input to the AND operation module so as to obtain the pulse signal.

7. The frequency divider circuit of claim 2, comprising a non-operation module for performing a non-operation on an input clock signal to obtain the asynchronous clock signal, and outputting the asynchronous clock signal to the first delay module.

8. The frequency dividing circuit according to claim 2, comprising an or operation module for performing an or operation on the pulse signal and the clock signal input to the or operation module to obtain the target signal.

9. The frequency dividing circuit according to any one of claims 1 to 8, wherein the gating module includes a multiplexer for outputting the fractional frequency division signal based on control of the second frequency division signal among the first frequency division signal and the first delay signal.

10. A digital signal processing circuit comprising a frequency dividing circuit as claimed in any one of claims 1 to 9.