CN118573187A - Frequency dividing circuit and digital signal processing circuit - Google Patents

Abstract

The application discloses a frequency dividing circuit and a digital signal processing circuit, wherein the frequency dividing circuit comprises: a phase-locked loop for generating a first frequency-divided signal and a second frequency-divided signal according to an input clock signal; the input end of the first delay module is connected with the output end of the phase-locked loop and is used for generating a first delay signal corresponding to the first frequency-dividing signal according to the asynchronous clock signal corresponding to the first frequency-dividing signal and the input clock signal; and the input end of the gating module is respectively connected with the output end of the first delay module and the output end of the phase-locked loop and is used for generating a decimal frequency division signal according to the first frequency division signal, the second frequency division signal and the first delay signal. The application realizes the decimal frequency division function by the structural arrangement of the first delay module and the gating module and the coordination of the phase-locked loop, thereby reducing the influence of the complex circuit structure of a plurality of gating gates in the frequency division circuit on the signal transmission rate.

Description

Frequency dividing circuit and digital signal processing circuit

Technical Field

The present application relates to digital circuit design, and more particularly, to a frequency dividing circuit and a digital signal processing circuit.

Background

A frequency dividing circuit is a circuit widely used in the electronic field, and its main function is to divide the frequency of an input signal to an output port in a specific ratio. Such circuits play an important role in a variety of electronic devices, such as electronic clocks, frequency synthesizers, audio systems, digital systems, and communication systems.

In optical communication and interfaces with transmission rates of 16Gbps and above, fractional frequency division is often needed, and since the transmission rate of 16Gbps and above is a high transmission rate, the frequency division of signals must be completed by cooperation of a gate, a flip-flop and other modules. However, in the existing fractional frequency division circuit, a plurality of gates are often required to cooperate to realize fractional frequency division, so that the circuit has a complex structure, and meanwhile, more gates can influence the signal transmission rate of the circuit.

Therefore, a circuit that is relatively simple and capable of implementing fractional division is needed to solve the above technical problems.

Disclosure of Invention

In order to solve the above technical problems, embodiments of the present application provide a frequency dividing circuit and a digital signal processing circuit.

According to an aspect of an embodiment of the present application, there is provided a frequency dividing circuit including: a phase-locked loop for generating a first frequency-divided signal and a second frequency-divided signal according to an input clock signal; the input end of the first delay module is respectively connected with the output end of the phase-locked loop and is used for generating a first delay signal corresponding to the first frequency-dividing signal according to the asynchronous clock signal corresponding to the first frequency-dividing signal and the input clock signal; and the input end of the gating module is respectively connected with the output end of the first delay module and the output end of the phase-locked loop and is used for generating a decimal frequency division signal according to the first frequency division signal, the second frequency division signal and the first delay signal.

In some embodiments of the application, the phase locked loop comprises: the frequency modulation module is used for generating a first frequency division signal and a second frequency division signal according to an input target signal; the input end of the pulse module is connected with the output end of the frequency modulation module, and the output end of the pulse module is connected with the input end of the frequency modulation module and is used for generating a pulse signal according to the first frequency division signal, the second frequency division signal and the input clock signal, generating the target signal according to the pulse signal and the clock signal and inputting the target signal to the frequency modulation module.

In some embodiments of the present application, the frequency modulation module includes a first frequency divider, a second frequency divider, and a third frequency divider connected in sequence; the first frequency divider is used for dividing the frequency of the input target signal to obtain an initial frequency-divided signal; the second frequency divider is used for dividing the frequency of the initial frequency division signal to obtain the first frequency division signal; the third frequency divider is configured to divide the first frequency division signal to obtain the second frequency division signal.

In some embodiments of the application, the first frequency divider is the same as the second frequency divider in frequency division, and the third frequency divider is different from the second frequency divider in frequency division.

In some embodiments of the present application, the pulse module includes a second delay module configured to generate a second delay signal according to the first frequency-divided signal and the clock signal, so that the pulse module generates the pulse signal according to the second delay signal, the first frequency-divided signal, and the second frequency-divided signal.

In some embodiments of the present application, the pulse module further includes a nor operation module and an and operation module; the nor operation module is used for performing nor operation on the second delay signal and the second frequency division signal input into the nor operation module so as to obtain a supplementary frequency division signal; the AND operation module is used for performing AND operation on the complementary frequency division signal and the first frequency division signal which are input to the AND operation module so as to obtain the pulse signal.

In some embodiments of the present application, the frequency dividing circuit includes a non-operation module, configured to perform a non-operation on an input clock signal to obtain the asynchronous clock signal, and output the asynchronous clock signal to the first delay module.

In some embodiments of the present application, the frequency dividing circuit includes an or operation module for performing an or operation on the pulse signal and the clock signal input to the or operation module to obtain the target signal.

In some embodiments of the present application, the gating module includes a multiplexer for outputting the fractional frequency division signal based on control of the second frequency division signal among the first frequency division signal and the first delay signal.

According to another aspect of an embodiment of the present application, there is provided a digital signal processing circuit including a frequency dividing circuit as described above.

In the above embodiment, the correction effect of the corresponding correction frequency in correcting the transmission assembly is improved based on the initialized belt tension.

In the technical scheme of the embodiment of the application, the following beneficial effects can be brought by the application content: combining the first frequency division signal and the second frequency division signal generated by the phase-locked loop with the first delay signal generated by the first delay module to serve as the input of the gating module, and obtaining the corresponding decimal frequency division signal based on the gating module; the digital circuit structures of the first delay module and the gating module are arranged and matched with the phase-locked loop, so that the generation of the fractional frequency division signal can be realized, and the influence of the complex digital circuit structure in the frequency division circuit on the signal transmission rate is reduced.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the application and together with the description, serve to explain the principles of the application. It is evident that the drawings in the following description are only some embodiments of the present application and that other drawings may be obtained from these drawings without inventive effort for a person of ordinary skill in the art. In the drawings:

Fig. 1 is a schematic diagram of an overall circuit framework of a frequency divider circuit according to an exemplary embodiment of the present application.

Fig. 2 is a schematic circuit diagram of a first delay module according to an exemplary embodiment of the present application.

Fig. 3 is a circuit configuration diagram of a gating module according to an exemplary embodiment of the present application.

Fig. 4 is a schematic circuit diagram of a phase locked loop according to an exemplary embodiment of the present application.

Fig. 5 is a schematic circuit diagram of a frequency modulation module according to an exemplary embodiment of the present application.

Fig. 6 is a schematic circuit diagram of a frequency modulation module according to another exemplary embodiment of the present application.

Fig. 7 is a schematic circuit configuration diagram of a pulse module according to an exemplary embodiment of the present application.

Fig. 8 is a schematic circuit diagram of a pulse module according to another exemplary embodiment of the present application.

Fig. 9 is a schematic circuit diagram of a phase locked loop according to another exemplary embodiment of the present application.

Fig. 10 is a schematic diagram of an overall circuit configuration of a frequency dividing circuit according to an exemplary embodiment of the present application.

Detailed Description

For the purposes of making the objects and embodiments of the present application more apparent, an exemplary embodiment of the present application will be described in detail below with reference to the accompanying drawings in which exemplary embodiments of the present application are illustrated, it being apparent that the exemplary embodiments described are only some, but not all, of the embodiments of the present application.

It should be noted that the brief description of the terminology in the present application is for the purpose of facilitating understanding of the embodiments described below only and is not intended to limit the embodiments of the present application. Unless otherwise indicated, these terms should be construed in their ordinary and customary meaning.

The terms first, second, third and the like in the description and in the claims and in the above-described figures are used for distinguishing between similar or similar objects or entities and not necessarily for describing a particular sequential or chronological order, unless otherwise indicated. It is to be understood that the terms so used are interchangeable under appropriate circumstances.

The terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a product or apparatus that comprises a list of elements is not necessarily limited to all elements explicitly listed, but may include other elements not expressly listed or inherent to such product or apparatus.

It should be noted that: references herein to "a plurality" means two or more. "and/or" describes an association relationship of an association object, meaning that there may be three relationships, e.g., a and/or B may represent: a exists alone, A and B exist together, and B exists alone. The character "/" generally indicates that the context-dependent object is an "or" relationship.

Fig. 1 is a schematic diagram of an overall circuit framework of a frequency divider circuit according to an exemplary embodiment of the present application. As shown in fig. 1, the frequency dividing circuit 100 of the present application includes a phase locked loop 110, a first delay module 120, and a gating module 130, and each of the parts will be described in detail one by a following embodiment.

The phase-locked loop 110 is configured to generate a first frequency-divided signal and a second frequency-divided signal according to an input clock signal.

It should be noted that, for the input clock signal, the clock signal may be generated by a predetermined clock generator, and the clock generator may generate the clock signal by using an oscillator that may provide a square wave output. The oscillator circuit always uses feedback to oscillate the oscillator. The oscillator is made to operate at a specific frequency by feeding back the corresponding parameters. To ensure that the associated electronic components are operated in synchronization.

The pll 110 may generate the first frequency-divided signal and the second frequency-divided signal according to the input clock signal, which may be regarded as that the pll 110 is provided with a digital frequency-dividing circuit 100 for implementing signal frequency division in a corresponding circuit structure, for example, the digital frequency-dividing circuit 100 is an electronic clock, and the frequency-dividing circuit 100 is utilized to divide the high-frequency crystal oscillator signal into the low-frequency clock signal.

By the arrangement of the phase-locked loop 110, the clock signals among different modules or devices can be ensured to be consistent, and data drift and communication errors are avoided.

The input end of the first delay module 120 is connected to the output end of the phase-locked loop 110, and is configured to generate a first delay signal corresponding to the first frequency-divided signal according to the first frequency-divided signal and an asynchronous clock signal corresponding to the input clock signal.

It should be noted that, in the frequency dividing circuit 100 of the present application, due to consistency of clock signals, the input end of the first delay module 120 may be connected to not only the output end of the phase-locked loop 110, but also the input end of the phase-locked loop 110, so that a clock signal corresponding to an asynchronous clock signal at the input end of the phase-locked loop 110 is consistent with the clock signal at the input end of the first delay module 120.

The first delay module 120 may be a D flip-flop, and generates the first delay signal based on a delay function of the D flip-flop, mainly in sampling an input signal and maintaining an output signal of the D flip-flop. Specifically, the D flip-flop samples the input signal on the rising edge (or falling edge, depending on the type and design of the flip-flop) of the clock signal and holds the sampled data unchanged for the next cycle of the clock signal, thereby achieving a one clock cycle delay.

For exemplary illustration, fig. 2 is a schematic circuit diagram of a first delay module according to an exemplary embodiment of the present application. As shown in fig. 2, the D flip-flop samples the data at the D input when the rising (or falling) edge of the clock signal CLK comes. The sampled data will be stored inside the flip-flop and will remain unchanged for the next period of the clock signal. Thus, from the D input to the Q output (orThe output) may have a delay of one clock cycle.

Of course, the delay function of the first delay module 120 may also be implemented by other circuit structures.

For example, a latch, under control of an enable signal or clock signal, is capable of storing input data and holding the data for a period of time, similar to the function of a D flip-flop updating data and holding a new state at a clock edge. Accordingly, the D flip-flop in the above example may be replaced accordingly based on the latch and the adaptation circuit.

As another example, a register, which implements storage and delay of data through its internal flip-flops (e.g., D flip-flops). Under control of the clock signal, the register may receive the input data and store it in an internal flip-flop at the clock edge, thereby implementing delay processing of the data. Similarly, the D flip-flop in the above example can be replaced correspondingly based on the register and the adaptation circuit.

Also, for example, a shift register, which realizes storage and transmission of data through its internal flip-flops. Under the drive of clock signals, data can be sequentially transferred between the triggers, so that the delay and shift processing of the data are realized. This delay characteristic is essentially similar to the delay function of the D flip-flop, both based on the synchronization of the clock signal and the storage and transmission of the data. Similarly, the D flip-flop in the above example can be replaced correspondingly based on the shift register and the adaptation circuit.

In addition, a circuit having a certain similarity in function and action with the delay characteristics of the D flip-flop may be used instead, and is merely illustrative and not particularly limited. In addition, the application mainly uses the D trigger to realize the delay function, and in other embodiments, if not specifically described, the delay module used by the D trigger can also realize the corresponding function.

When the digital clock signal processing circuit is used, based on the D trigger implementation principle, the asynchronous clock signal corresponding to the first frequency division signal and the input clock signal is used as the input of the D trigger, so that a first delay signal corresponding to the first frequency division signal is generated.

The input end of the gating module 130 is connected to the output end of the first delay module 120 and the output end of the phase-locked loop 110, respectively, and is used for generating a fractional frequency division signal according to the first frequency division signal, the second frequency division signal and the first delay signal.

Specifically, the gating module 130 may be a multiplexer for outputting the fractional frequency division signal based on the control of the second frequency division signal among the first frequency division signal and the first delay signal.

Taking a multiplexer in the FPGA (Field Programmable GATE ARRAY) as an example, the FPGA device includes basic resources such as a programmable logic block CLB (Configurable Logic Blocks), wiring resources, and a programmable input/output module. The programmable logic block is a basic unit for realizing user functions, and comprises an interconnection switch matrix and a plurality of component units. Each component unit further comprises a Look-Up Table LUT (Look-Up Table), a trigger, a multiplexer and the like. In the FPGA, the multiplexer is used as a bridge for connecting each wiring track and the programmable logic block, and has great influence on the performance and the power consumption of the FPGA.

Illustratively, fig. 3 is a schematic circuit diagram of a gating module according to an exemplary embodiment of the present application. As shown in fig. 3, the multiplexer of the present application may be a 2-to-1 multiplexer, and the 2-to-1 multiplexer has two input terminals and one output terminal, and selects one of the input signals to be transmitted to the output terminal through a selection signal line control. Such a multiplexer is suitable for simple data selection and signal switching. The signals input by the two input ends can be a first frequency division signal and a first delay signal, and the signal input by the signal line is selected as a second frequency division signal. The output end is used for outputting the decimal frequency division signal.

Through the above embodiment, the technical solution of the present application combines the first frequency-divided signal and the second frequency-divided signal generated by the phase-locked loop 110 with the first delay signal generated by the first delay module 120, so as to be used as the input of the gating module 130, and obtains the corresponding fractional frequency-divided signal based on the gating module 130; through the structural arrangement of the first delay module 120 and the gating module 130, the fractional frequency division function can be realized by matching with the phase-locked loop 110, so that the influence of complex circuit structures of a plurality of gating gates in a circuit on the signal transmission rate is reduced.

In some embodiments of the present application, for the asynchronous clock signal corresponding to the clock signal, the calculation may be performed by setting a non-operation module in the frequency dividing circuit 100.

Specifically, the frequency dividing circuit 100 may further include a non-operation module, where an output end of the non-operation module is connected to an input end of the first clock module, and is configured to perform non-operation on an input clock signal to obtain an asynchronous clock signal, and output the asynchronous clock signal to the first delay module 120.

To ensure the consistency of the clock signals, the input end of the non-operation module is connected with the port for inputting the clock signals at the input end of the phase-locked loop 110.

In some embodiments of the present application, fig. 4 is a schematic circuit diagram of a phase locked loop according to an exemplary embodiment of the present application. As shown in fig. 4, the phase locked loop 110 may include a frequency modulation module 140 and a pulse module 150, and the frequency modulation module 140 and the pulse module 150 are connected end to form a loop.

Specifically, the frequency modulation module 140 is configured to generate a first frequency division signal and a second frequency division signal according to an input target signal.

The input end of the pulse module 150 is connected with the output end of the frequency modulation module 140, and the output end of the pulse module 150 is connected with the input end of the frequency modulation module 140, and is used for generating a pulse signal according to the first frequency division signal, the second frequency division signal and the input clock signal, generating a target signal according to the pulse signal and the clock signal, and inputting the target signal to the frequency modulation module 140.

The frequency modulation module 140 is a circuit structure capable of implementing a frequency division function, and has a main function of transforming the frequency of an input signal to generate an output signal with a specific frequency. The frequencies of these output signals may be integer multiples or fractions of the frequency of the input signal. Such as divider circuit 100 applied in a plurality of usage scenarios of clock signal generation, wireless communication, digital signal processing, audio system, video processing, etc.

In some usage scenarios, the output frequency of the frequency modulation module 140 is an integer fraction of the input frequency, e.g., divide-by-2, divide-by-4, etc. In other usage scenarios, the output frequency of the frequency modulation module 140 may also be a non-integer fraction of the input frequency, e.g., divide-by-3/4, divide-by-5/9, etc. For a specific use scenario, whether integer frequency division or fractional frequency division is selected, and adaptive adjustment is required according to the actual requirement of the fractional frequency division signal. Meanwhile, the hardware cost can be combined for adaptive adjustment.

Illustratively, in digital circuits, one common way to achieve frequency division is to use a D flip-flop or counter. For example, even-numbered frequency division may be achieved by a cascade of D flip-flops; for odd division, this may be implemented by a state machine or a counter in combination with logic gates. Furthermore, a programmable logic device (e.g., FPGA) may also be used to implement the more complex frequency divider circuit 100. The frequency modulation module 140 of the present application may implement even frequency division using a cascade of D flip-flops.

Because the frequency modulation module 140 and the pulse module 150 cooperate to form a loop, in the use process, for the pulse module 150, a pulse signal is generated according to the input first frequency division signal, second frequency division signal and clock signal, wherein the first frequency division signal and the second frequency division signal are generated by the frequency modulation module 140. Meanwhile, the generated pulse signal and the clock signal are combined with a designated logic gate to calculate to obtain a target signal, and the generated target signal is input into the frequency modulation module 140 to form the phase-locked loop 110.

Through the above embodiment, based on the phase-locked loop 110 formed by the frequency modulation module 140 and the pulse module 150, the frequency and the phase of the output signal can be automatically adjusted to keep synchronous or locked state with the frequency and the phase of the input signal, so that the pulse signal of the present application can ensure the stability and consistency of the signal by automatically adjusting the frequency and the phase of the output signal.

In some embodiments of the present application, fig. 5 is a schematic circuit diagram of a frequency modulation module according to an exemplary embodiment of the present application. As shown in fig. 5, further illustratively describing the frequency modulation module 140, the frequency modulation module 140 may include a first frequency divider, a second frequency divider, and a third frequency divider connected in sequence.

The first frequency divider is used for dividing the frequency of the input target signal to obtain an initial frequency-divided signal; the second frequency divider is used for dividing the frequency of the initial frequency division signal to obtain a first frequency division signal; the third frequency divider is used for dividing the frequency of the first frequency division signal to obtain a second frequency division signal.

In detail, fig. 6 is a schematic circuit diagram of a frequency modulation module according to another exemplary embodiment of the present application. As shown in fig. 6, the first frequency divider, the second frequency divider and the third frequency divider may be D flip-flops, and since the D flip-flops are digital circuit elements with memory function, the output state Q thereof is updated according to the value of the input signal D when the rising edge (or falling edge, depending on the specific flip-flop type) of the Clock signal CLK (Clock) arrives. That is, if D is high at the arrival of the rising edge of CLK, Q becomes high; if D is low, Q goes low.

Based on the basic principle of the D flip-flop, when the D flip-flop is used as a frequency divider, the frequency of the input signal is reduced to an integer fraction of the original frequency. The frequency dividing function can be conveniently realized by utilizing the memory function and the clock sensitivity of the D trigger.

Specifically, the output Q of the D flip-flop is fed back to its input D, thus forming a basic frequency divider. Since the value of Q is inverted every time the rising edge of CLK comes, the effect of halving the frequency is achieved.

For example, the basic divide-by-two divider is described above, and the Q terminal of the D flip-flop is simply connected to the D terminal.

For another example, for higher multiples of the frequency division, this can be achieved by cascading multiple D flip-flops. For example, to achieve four frequency division, two frequency dividers may be connected in series; to achieve the divide-by-eight, a divide-by-two is connected in series. And so on, will not be described in detail.

Of course, for setting relatively complex frequency dividers by D flip-flops, e.g., for frequency division that is not a power of 2 multiple, such as divide-by-three, divide-by-five, etc., may also be implemented in combination with counters or more complex combinational logic.

Through the above embodiment, the frequency modulation module 140 is formed by a plurality of sub-frequency dividers in a cascading manner, so that the implementation principle of the frequency modulation module 140 is simpler than that of the frequency modulation module 140 set by a complex circuit structure, meanwhile, the combination flexibility of different sub-frequency dividers is improved, the expansion is easy, and the adaptive adjustment is convenient when the frequency modulation module 140 is required to realize different frequency division multiples.

In some embodiments of the application, the first frequency divider is the same as the second frequency divider in frequency division multiple, and the third frequency divider is different from the second frequency divider in frequency division multiple.

Illustratively, the frequency division of the target multiple is implemented in a cascade manner of D flip-flops, where the target multiple may be determined according to the number of cascaded D flip-flops and the corresponding frequency division multiple. As shown in fig. 6, since the frequency modulation module 140 of the present application is configured to generate the first frequency-divided signal and the second frequency-divided signal, the first frequency divider of the present application may be a four-frequency divider, the second frequency divider may be a four-frequency divider, and the third frequency divider may be a two-frequency divider. The four frequency dividers can be obtained by connecting two frequency dividers in series, and can also be formed by electronic components such as a D trigger, a logic gate and the like in the form of other digital circuits.

Of course, the frequency modulation module 140 of the present application may also be composed of a sixteen frequency divider and a two frequency divider.

Based on this, in the actual use process, the frequency dividers with different multiples can be packaged, for example, the frequency dividers are respectively set based on the frequency dividers, the frequency dividers are four, the frequency divider is eight times, and in the use process, if the frequency division multiple of the frequency divider to be used is eight times, the frequency divider can be directly adopted, or one frequency divider and one frequency divider are cascaded, and then three frequency dividers are cascaded. For example, in one use scenario of the frequency modulation module 140 of the present application, when the frequency division circuit 100 of the present application is used, if the frequency division multiple of the frequency modulation module 140 needs to be switched by the switch circuit, the frequency division multiple may be combined based on different frequency division multiple.

Through the above embodiment, the frequency divider inside the frequency adjusting module 140 can be adaptively packaged according to the requirement, so that the reliability and the design quality of the product can be improved, the distribution and isolation of the product functions are realized, and the problem discovery and the design improvement are easier due to ‌.

In some embodiments of the present application, fig. 7 is a schematic circuit diagram of a pulse module according to an exemplary embodiment of the present application. As shown in fig. 7, further exemplary explanation is provided for the pulse module 150, where the pulse module 150 includes a second delay module for generating a second delay signal according to the first frequency-divided signal and the clock signal, so that the pulse module 150 generates the pulse signal according to the second delay signal, the first frequency-divided signal and the second frequency-divided signal.

Specifically, the second delay module may employ the same D flip-flop as the first delay module 120. A different delay circuit than the first delay module 120 may also be employed.

Illustratively, a delay module is provided in pulse module 150 to delay DIV16 by one cycle of the original input clock, then to nor the delayed DIV16 signal with the DIV32 signal, and then to and with the original DIV16 based on the nor output, resulting in a cycle of 33Tclk.

Where DIV16 represents the first divided signal and may be considered a divide-by-sixteen signal; DIV32 represents a second frequency division signal, which may be considered a thirty-two frequency division signal; 33Tclk denotes a pulse signal generated from the first divided signal, the second divided signal, and the input clock signal, and can also be regarded as a thirty-three divided signal by delay processing.

Through the above embodiment, when the signal entering the frequency modulation module 140 is processed, an additional period duration is inserted into the period time of the normal input signal through the second delay module, so that an additional frequency division is added to the input frequency division signal of the frequency modulation module 140, so as to facilitate the generation of the fractional frequency division signal.

In some embodiments of the present application, fig. 8 is a schematic circuit structure of a pulse module according to another exemplary embodiment of the present application. As shown in fig. 8, the pulse-based module 150 generates a pulse signal from the second delay signal, the first frequency-divided signal, and the second frequency-divided signal. To implement the digital operation process illustrated in the pulse module 150, the pulse module 150 is further described, and the pulse module 150 further includes a nor operation module and an and operation module.

The nor operation module is used for performing nor operation on the second delay signal and the second frequency division signal input into the nor operation module so as to obtain a supplementary frequency division signal; the AND operation module is used for performing AND operation on the complementary frequency division signal and the first frequency division signal which are input to the AND operation module so as to obtain a pulse signal.

Specifically, the input end of the nor operation module is connected with the output end of the second delay module, and the output end of the nor operation module is connected with the input end of the and operation module.

In some embodiments of the present application, fig. 9 is a schematic circuit diagram of a phase locked loop according to another exemplary embodiment of the present application. As shown in fig. 9, in combination with the phase-locked loop 110 in the above embodiment, a target signal is generated according to a pulse signal and a clock signal, and the target signal is input to the frequency modulation module 140, which may at least include the following.

Specifically, the pll 110 further includes an or operation module, where an input end of the or operation module is connected to an output end of the pulse module 150, or an output end of the operation module is connected to an input end of the fm module 140, and is configured to perform an or operation on the pulse signal and the clock signal input to the or operation module to obtain the target signal.

Similarly, to ensure the consistency of the clock signal, the input end of the OR operation module is connected with the port for inputting the clock signal at the input end of the phase-locked loop 110.

Fig. 10 is a schematic diagram of an overall circuit configuration of a frequency dividing circuit according to an exemplary embodiment of the present application. As shown in fig. 10, in order to more clearly disclose the technical solution of the present application, the following is further exemplary described by combining a plurality of embodiments in the above.

As shown in fig. 10, the following exemplary description is made of the identifications in the drawings:

The method comprises the following steps: the Pulse block illustrated in the figure represents the Pulse module 150; the DIV block illustrated in the figure represents the frequency modulation module 140; the D flip-flop illustrated in the figure represents the first delay block 120; the MUX gating block 130 is illustrated.

And two,: CLK schematically shown in the figure represents a clock signal; ln1 and a0 shown in the figure each represent a first divided signal, corresponding to a divide-by-sixteen signal; ln2 schematically in the figure represents a second divided signal, corresponding to a divided-by-32 signal; pulse illustrated in the figure represents a Pulse signal; in is schematically shown In the figure to indicate a target signal; a1 schematically shown in the figure represents a first delay signal.

Before the clock signal enters the frequency modulation module 140, an additional period duration is inserted into the 32 normal input signal period times based on the second delay module arranged in the pulse module 150, so that the input 32 of the frequency modulation module 140 is divided, that is, the original signal is divided by 33.

Specifically, the technical scheme of the application can be explained by dividing the technical scheme into three parts. A first section for processing the original input signal so that an additional original input signal period can be inserted when the processed signal is divided by 32; the second part forms a divider chain based on a plurality of cascaded dividers within the frequency modulation module 140, including divide by 4/16/32. And the third part performs gating processing on the 16 frequency division signals with different delays through the 32 frequency division signals, so as to obtain 16.5 frequency division, and obtain the decimal frequency division signals.

Further, the exemplary description is made in connection with an internal digital arithmetic circuit;

Firstly, for the pulse module 150, the operation of delaying the DIV16 by one original input clock period is performed, then the delayed DIV16 signal and the DIV32 signal are subjected to nor operation, or the output is further subjected to and operation with the original DIV16, finally a pulse signal with a period of 33Tclk is generated, but the high level pulse width is only one period, and the pulse signal is subjected to or operation with the original clock, so that the required target signal with one period duration additionally inserted in 32 periods can be generated.

Next, the target signal is input to the frequency modulation module 140, and divided by 4, 16, and 32. The frequency of the divided-by-16 signal is changed at this time, and is not actually divided by 16.5, because the delay processing is performed in the pulse module 150, and the signal divided by 32 at this time is actually a divided-by-33 signal.

Finally, the divide by 16 signal and the divide by 16 signal delayed by half a clock cycle are gated by the gating module 130 and the DIV32 to generate the true divide by 16.5 signal.

In some embodiments of the present application, a digital signal processing circuit is also disclosed, where the digital signal processing circuit includes the frequency dividing circuit 100 disclosed in any of the above embodiments.

Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present application, and not for limiting the same; although the application has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the application.

The foregoing description, for purposes of explanation, has been presented in conjunction with specific embodiments. The illustrative discussions above are not intended to be exhaustive or to limit the embodiments to the precise forms disclosed above. Many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles and the practical application, to thereby enable others skilled in the art to best utilize the embodiments and various embodiments with various modifications as are suited to the particular use contemplated.

Claims (10)

1. A frequency dividing circuit, comprising:

a phase-locked loop for generating a first frequency-divided signal and a second frequency-divided signal according to an input clock signal;

The input end of the first delay module is connected with the output end of the phase-locked loop and is used for generating a first delay signal corresponding to the first frequency-dividing signal according to the asynchronous clock signal corresponding to the first frequency-dividing signal and the input clock signal;

and the input end of the gating module is respectively connected with the output end of the first delay module and the output end of the phase-locked loop and is used for generating a decimal frequency division signal according to the first frequency division signal, the second frequency division signal and the first delay signal.

2. The frequency divider circuit of claim 1, wherein the phase-locked loop comprises:

the frequency modulation module is used for generating a first frequency division signal and a second frequency division signal according to an input target signal;

The input end of the pulse module is connected with the output end of the frequency modulation module, and the output end of the pulse module is connected with the input end of the frequency modulation module and is used for generating a pulse signal according to the first frequency division signal, the second frequency division signal and the input clock signal, generating the target signal according to the pulse signal and the clock signal and inputting the target signal to the frequency modulation module.

3. The frequency divider circuit of claim 2, wherein the frequency modulation module comprises a first frequency divider, a second frequency divider, and a third frequency divider connected in sequence;

The first frequency divider is used for dividing the frequency of the input target signal to obtain an initial frequency-divided signal;

the second frequency divider is used for dividing the frequency of the initial frequency division signal to obtain the first frequency division signal;

the third frequency divider is configured to divide the first frequency division signal to obtain the second frequency division signal.

4. The frequency dividing circuit of claim 3, wherein the first frequency divider is the same frequency division multiple as the second frequency divider, and wherein the third frequency divider is different from the second frequency divider.

5. The frequency divider circuit of claim 2, wherein the pulse module comprises a second delay module configured to generate a second delay signal based on the first frequency divided signal and the clock signal, such that the pulse module generates the pulse signal based on the second delay signal, the first frequency divided signal, and the second frequency divided signal.

6. The frequency divider circuit of claim 5, wherein the pulse module further comprises a nor operation module and an and operation module; the nor operation module is used for performing nor operation on the second delay signal and the second frequency division signal input into the nor operation module so as to obtain a supplementary frequency division signal; the AND operation module is used for performing AND operation on the complementary frequency division signal and the first frequency division signal which are input to the AND operation module so as to obtain the pulse signal.

7. The frequency divider circuit of claim 2, comprising a non-operation module for performing a non-operation on an input clock signal to obtain the asynchronous clock signal, and outputting the asynchronous clock signal to the first delay module.

8. The frequency dividing circuit according to claim 2, comprising an or operation module for performing an or operation on the pulse signal and the clock signal input to the or operation module to obtain the target signal.

9. The frequency dividing circuit according to any one of claims 1 to 8, wherein the gating module includes a multiplexer for outputting the fractional frequency division signal based on control of the second frequency division signal among the first frequency division signal and the first delay signal.

10. A digital signal processing circuit comprising a frequency dividing circuit as claimed in any one of claims 1 to 9.