CN100381968C - System clock pulse switching device and method for switching its frequency - Google Patents
System clock pulse switching device and method for switching its frequency Download PDFInfo
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- CN100381968C CN100381968C CNB2005100732320A CN200510073232A CN100381968C CN 100381968 C CN100381968 C CN 100381968C CN B2005100732320 A CNB2005100732320 A CN B2005100732320A CN 200510073232 A CN200510073232 A CN 200510073232A CN 100381968 C CN100381968 C CN 100381968C
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Abstract
The present invention provides a system clock pulse switching device and method for switching the frequency. The system clock pulse switching device comprises a clock pulse signal source, a frequency eliminating circuit and an enable signal generating device, wherein the clock pulse signal source is used for providing a reference clock pulse; the frequency eliminating circuit is electrically connected with a signal source of the clock pulse, and is used for eliminating frequency of the reference clock pulse to generate a frequency eliminating signal and a system clock pulse; the enable signal generating device is electrically connected the frequency eliminating circuit, and is used for eliminating frequency of the frequency eliminating signal to generate at least one enable signal. The frequency eliminating circuit can switch the frequency of the system clock pulse corresponding to the edge time point of the frequency eliminating signal.
Description
Technical field
The relevant system clock pulse handoff technique of the present invention refers to especially when switching the frequency of the system clock pulse that is produced, and can avoid corresponding enable signal to produce the system clock pulse switching device and the correlation technique of drift.
Background technology
In the middle of a synchronizing circuit (synchronous circuit), individual modules or element all are to carry out synchronous operation according to a system clock pulse (system clock).The frequency that synchronizing circuit can change or switch this system clock pulse satisfies different running demands.For example, the electrical power consumed that can utilize the mode of the frequency that reduces system clock pulse to save circuit.In present correlative technology field, generally be utilize the phase-locked loop (phase-locked loop, PLL) or digital frequency eliminating circuit changes or the frequency of switched system time clock.
Except system clock pulse, usually also can utilize the enable signal (enable signal) of one or more fixed frequencies to keep the normal operation of systematic function in the synchronizing circuit.For example, the GSM communication device needs an enable signal (QBIT_EN) to decide the opportunity of its transmission and received signal.In case the situation of this enable signal generation drift (drift) will badly influence the communication quality of GSM communication device.
As mentioned above, in present correlative technology field, the phase-locked loop is one of means that are commonly used to the switched system clock frequency.As everyone knows, the phase-locked loop needs the one steady period of becoming (settling time) to make the frequency of its output time clock reach new steady state (SS) in the process of the frequency of switching its output time clock.In this section becomes the steady time, because the clock frequency that the phase-locked loop produced is unfixed, so regular meeting causes enable signal to produce the situation of drift.
Please refer to Fig. 1, its illustrate changes the calcspar of one of system clock pulse frequency existing systems time clock generation device 100 for utilizing the phase-locked loop.System clock pulse generation device 100 is to utilize a phase-locked loop 110 to produce a time clock PCLK, with the system clock pulse SCLK as circuit system 130.As previously mentioned, 110 change in the process of its frequency of exporting time clock PCLK in the phase-locked loop, need the one steady period of becoming make the frequency of time clock PCLK reach new steady state (SS).In the middle of this section becomes the steady time, for fear of the unsettled time clock PCLK of frequency the running of circuit system 130 is caused bad influence, multiplexer 120 can bypass (bypass) fall the time clock PCLK that phase-locked loop 110 is exported, and reelects and select the external clock pulse XCLK with fixed frequency and be used as system clock pulse SCLK.When phase-locked loop 110 reached new steady state (SS), multiplexer 120 just can switch back the time clock PCLK that phase-locked loop 110 is exported by external clock pulse XCLK with system clock pulse SCLK.
Is example with the time clock PCLK that is exported from the process that frequency 52MHz switches to frequency 26MHz with phase-locked loop 110, and existing systems time clock SCLK switching flow is as follows:
At first, utilize multiplexer 120 bypass to fall the time clock PCLK (52MHz) that is exported phase-locked loop 110, and system clock pulse SCLK is switched to external clock pulse XCLK.Then, 26MHz can be adjusted to the frequency of its output time clock PCLK in phase-locked loop 110.Deng phase-locked loop 110 stable after, utilize multiplexer 120 that system clock pulse SCLK is switched to the time clock PCLK (26MHz) that is exported phase-locked loop 110 by external clock pulse XCLK again.
Yet, the aforementioned multiplexer 120 that utilizes switches to external clock pulse XCLK with the time clock PCLK that system clock pulse SCLK is exported by phase-locked loop 110, or switch to the process of time clock PCLK by external clock pulse XCLK, be the time clock change action of asynchronous (asynchronous).Therefore, the time clock PCLK of phase-locked loop 110 outputs and external clock pulse XCLK are also inequality probably in phase place and the frequency switched at that time.This can make that in the frequency handoff procedure of system clock pulse SCLK the very difficult cycle with enable signal is maintained and immobilizes, and therefore causes enable signal to produce the problem of drift easily.
As mentioned above, in present correlative technology field, also can utilize digital frequency eliminating circuit to produce the system clock pulse of different frequency, but still can cause enable signal to produce the problem of drift.Generally speaking, enable signal utilizes counter to produce.For example, Figure 2 shows that the calcspar that utilizes digital frequency eliminating circuit to change one of system clock pulse frequency existing system time clock generation device 200.Digital frequency eliminating circuit 210 in the system clock pulse generation device 200 can carry out frequency elimination to having one of fixed frequency pulse reference clock RCLK, to produce a system clock pulse SCLK.220 in counter can produce an activation signal according to this system clock pulse SCLK.The enable signal QBIT_EN that with the frequency is 13/12MHz is an example, and when the frequency of the system clock pulse SCLK that is produced when digital frequency eliminating circuit 210 was 52MHz, then 220 per 48 system clock pulse cycles of counter will produce an enable signal QBIT_EN.And when the frequency of system clock pulse SCLK was 13MHz, then 220 per 12 system clock pulse cycles of counter will produce an enable signal QBIT_EN.Yet, because the time point of the frequency of digital frequency eliminating circuit 210 switched system time clock SCLK may take place at any time, so still may cause the cyclomorphosis of the enable signal QBIT_EN that counter 220 produced.
Please refer to Fig. 3 and Fig. 4.Fig. 3 is an elongated sequential chart of enable signal QBIT_EN cycle.The sequential chart that Fig. 4 shortened for the enable signal QBIT_EN cycle.As shown in Figure 3, when digital frequency eliminating circuit 210 switched to 13MHz with the frequency of system clock pulse SCLK by 52MHz, the cycle of system clock pulse SCLK can be elongated.As mentioned above, when the system clock pulse frequency is 52MHz, 220 per 48 system clock pulse cycles of counter can produce an enable signal QBIT_EN, that is when the count value QBIT_CNT of counter 220 when 47 count to 0, will produce an enable signal QBIT_EN.If digital frequency eliminating circuit 210 does not have the frequency of switched system time clock SCLK, then the count value sequence of counter 220 should be QBIT_CNT (expected), and counter 220 should equal 0 o'clock generation enable signal at count value QBIT_CNT (expected), shown in the QBIT_EN among Fig. 3 (expected).Yet the frequency of system clock pulse SCLK switches to 13MHz by 52MHz can make that the system clock pulse cycle is elongated, and then causes the count cycle of counter 220 to be elongated, so the actual count value sequence of counter 220 can be QBIT_CNT.Such result can cause the generation time point of enable signal QBIT_EN delay and the cycle elongated, and the phenomenon of drift takes place.
As shown in Figure 4, when the frequency of system clock pulse SCLK switched to 52MHz by 13MHz, the system clock pulse cycle can shorten.As mentioned above, when the system clock pulse frequency is 13MHz, 220 per 12 system clock pulse cycles of counter can produce an enable signal QBIT_EN, that is when the count value QBIT_CNT of counter 220 when 11 count to 0, will produce an enable signal QBIT_EN.If digital frequency eliminating circuit 210 does not have the frequency of switched system time clock SCLK, then the time point of counter 220 generation enable signals can be shown in the QBIT_EN among Fig. 4 (expected).Yet, the frequency of system clock pulse SCLK switches to 52MHz by 13MHz can make the system clock pulse cycle shorten, therefore and the count cycle of counter 220 also can shorten, so the generation time point that can cause enable signal QBIT_EN in advance and the cycle shorten, and the phenomenon of drift takes place.
Summary of the invention
Therefore the method that the object of the present invention is to provide a kind of system clock pulse switching device and switch its frequency causes enable signal generation drift phenomenon in the time of can avoiding the frequency in the switched system time clock.
Disclosed a kind of system clock pulse switching device in an embodiment of the present invention, it includes: a time clock signal source is used to provide a pulse reference clock; One frequency eliminating circuit is electrically connected on this clock pulse signal source, is used for this pulse reference clock is carried out frequency elimination to produce a frequency elimination signal and a system clock pulse; And an activation signal generation device, be electrically connected on this frequency eliminating circuit, be used for this frequency elimination signal is carried out frequency elimination to produce at least one enable signal; Wherein this frequency eliminating circuit can switch the frequency of this system clock pulse in the time point to a edge that should the frequency elimination signal.
Disclose a kind of system clock pulse switching device in the embodiments of the invention in addition, it includes: a time clock signal source is used to provide a pulse reference clock; One activation signal generation device is electrically connected on this clock pulse signal source, is used for producing at least one enable signal; And a frequency eliminating circuit, be electrically connected on this clock pulse signal source, be used for this pulse reference clock is carried out frequency elimination producing a system clock pulse, and in to one of should enable signal the time point at edge, switch the frequency of this system clock pulse.
Embodiments of the invention also disclose a kind of method of switched system clock frequency, and it includes: a pulse reference clock is provided; This pulse reference clock is carried out frequency elimination to produce a frequency elimination signal; Produce a system clock pulse according to this pulse reference clock; This frequency elimination signal is carried out frequency elimination to produce at least one enable signal; And in to one of should the frequency elimination signal time point at edge, switch the frequency of this system clock pulse.
In addition, embodiments of the invention disclose a kind of method of switched system clock frequency in addition, and it includes: a pulse reference clock (a) is provided; (b) produce at least one enable signal; (c) this pulse reference clock is carried out frequency elimination to produce a system clock pulse; And (d) in to one of should enable signal the time point at edge, switch the frequency of this system clock pulse.
Description of drawings
Fig. 1 is the existing calcspar that utilizes the phase-locked loop to change one of system clock pulse frequency system clock pulse generation device.
Fig. 2 changes the calcspar of one of system clock pulse frequency system clock pulse generation device for the digital frequency eliminating circuit of existing utilization.
Fig. 3 is an elongated sequential chart of enable signal cycle.
The sequential chart that Fig. 4 shortened for the enable signal cycle.
Fig. 5 is the calcspar of the system clock pulse switching device of the present invention one first embodiment.
Fig. 6 is a sequential chart of the system clock pulse switching device of Fig. 5.
Fig. 7 is the calcspar of one second embodiment of system clock pulse switching device of the present invention.
Fig. 8 is the calcspar of one first embodiment of the frequency eliminating circuit among Fig. 7 of the present invention.
Fig. 9 to Figure 12 is the different sequential charts of the frequency eliminating circuit switched system clock frequency of Fig. 8.
Figure 13 is the calcspar of one second embodiment of the frequency eliminating circuit among Fig. 7 of the present invention.
Figure 14 is the calcspar of one the 3rd embodiment of system clock pulse switching device of the present invention.
Figure 15 is the calcspar of one the 4th embodiment of system clock pulse switching device of the present invention.
Figure 16 and Figure 17 are the calcspar of the different embodiment of the frequency eliminating circuit among Figure 15 of the present invention.
Symbol description
100,200 system clock pulse generation devices
110 phase-locked loops
120 multiplexers
130 circuit systems
220,520,810,1610 counters
530 toggle count devices
300,400,600,900,1000,1100,1200 sequential charts
500,700,1400,1500 system clock pulse switching devices
540 switching signal generators
550,1630 control modules
902,1002,1102,1202 times
710 clock pulse signal sources
210,510,720,800,1300,1520, frequency eliminating circuit
1600、1700
730,1430,1530 enable signal generation devices
820 decision unit
830,1340,1620,1730 time clock lock control unit
1330,1720 bolt lock devices
Embodiment
Please refer to Fig. 5, its illustrate is the calcspar of the system clock pulse switching device 500 of the present invention one first embodiment.System clock pulse switching device 500 comprises one and switches signal generator 540, is used for producing one and switches signal; One switches counter 530, is electrically connected on switching signal generator 540, is used for counting to 0 from a predetermined number; And a control module 550, be electrically connected on switching signal generator 540, be used for controlling the switching of the system clock pulse frequency that a digital frequency eliminating circuit 510 exported.When toggle count device 530 when a predetermined number counts to 0, it can trigger switching signal generator 540 and produce one and switch signal.Then, switching signal generator 540 can export switching signal to control module 550.When system clock pulse switching device 500 was desired to carry out the frequency switching of system clock pulse SCLK, control module 550 can be waited for the generation of switching signals.Have only when control module 550 to receive switching signal from switching signal generator 540, control module 550 just can allow digital frequency eliminating circuit 510 to switch the frequency of the system clock pulse SCLK of its outputs.
Suppose that digital frequency eliminating circuit 510 can switch the frequency of system clock pulse SCLK between 52MHz, 26MHz and these three different frequencies of 13MHz.As mentioned above, the frequency of enable signal QBIT_EN is 13/12MHz, so when the frequency of system clock pulse SCLK was 52MHz, 520 per 48 system clock pulse cycles of counter can produce an enable signal QBIT_EN.When the frequency of system clock pulse SCLK was 26MHz, then 520 per 24 system clock pulse cycles of counter can produce an enable signal QBIT_EN.And when the frequency of system clock pulse SCLK was 13MHz, 520 in counter was per 12 system clock pulse cycles can produce an enable signal QBIT_EN.When counting to 0 (being generation time point or the pulse wave edge of enable signal QBIT_EN) in order to allow the frequency of system clock pulse SCLK switch count value QBIT_CNT that time point always occurs in counter 520, predetermined number in the toggle count device 530 can be set at 47, promptly 540 per 48 system clock pulse cycles of switching signal generator can produce a switching signal.Because 48 is lowest common multiples of 48,24,12, when therefore producing a switching signal, also can produce an enable signal QBIT_EN.
In other words, system clock pulse switching device 500 of the present invention is that the frequency of system clock pulse SCLK is switched the generation time point (that is edge of corresponding enable signal QBIT_EN) that time point is set in enable signal QBIT_EN, to avoid enable signal QBIT_EN drift takes place.Because digital frequency eliminating circuit 510 is only just understood the frequency of switched system time clock SCLK when switching signal produces, and when producing switching signal, the count value QBIT_CNT of counter 520 also can count to 0, so when can guarantee that the frequency of system clock pulse SCLK is switched time point and always can be occurred in counter 520 and produce enable signal QBIT_EN.Thus, the enable signal QBIT_EN that counter 520 is produced does not just have the phenomenon of cyclomorphosis, promptly drift can not take place.
Fig. 6 is sequential Figure 60 0 of system clock pulse switching device 500.As shown in Figure 6, because it just is that the count value QBIT_CNT that occurs in counter 520 counts at 0 o'clock that the frequency of system clock pulse SCLK is switched time point, therefore the generation time point of enable signal QBIT_EN can be identical with the enable signal QBIT_EN (expected) in the ideal, and can generating period do not change and produce time point in advance or situation about delaying, promptly do not have the drift phenomenon.
If system clock pulse switching device 500 can produce a plurality of enable signals, then the predetermined number in the toggle count device 530 can be set at the corresponding value of lowest common multiple with pulse wave cycle of these a plurality of enable signals.For example, in another embodiment, system clock pulse switching device 500 produces the aforesaid enable signal QBIT_EN (frequency is 13/12MHz) except utilizing counter 520, also can utilize another counter (not shown) to produce another enable signal X_EN (not shown) of frequency for 13/5MHz.In this embodiment, when the frequency of system clock pulse SCLK is 13MHz, 520 per 12 system clock pulse cycles of counter just can produce an enable signal QBIT_EN, and another counter then is enable signal X_EN of cycle generation in per 5 system clock arteries and veins.Therefore, the predetermined number in the toggle count device 530 can be set at 59, so that 540 per 60 system clock pulse cycles of switching signal generator produce a switching signal.Because 60 is lowest common multiples of 5 and 12, so switching signal of generation the time, also can produce an enable signal QBIT_EN and an enable signal X_EN.
In the present embodiment, when the frequency of digital frequency eliminating circuit 510 switched system time clock SCLK, also can adjust the predetermined number in the toggle count device 530 accordingly.For example, when the frequency of system clock pulse SCLK switches to 26MHz, the predetermined number in the toggle count device 530 can be adjusted into 119, and when the frequency of system clock pulse SCLK switches to 52MHz, then the predetermined number in the toggle count device 530 can be adjusted into 239, the rest may be inferred.Thus, the time point of numeral frequency eliminating circuit 510 switched system time clock SCLK frequencies, will be corresponding to a common edge of these a plurality of enable signals, so can avoid these a plurality of enable signals when the frequency of system clock pulse SCLK is switched, to produce the situation of drift.
Please refer to Fig. 7, it is according to the calcspar of the system clock pulse switching device 700 that the second embodiment of the present invention illustrated.The activation signal generation device 730 that system clock pulse switching device 700 includes a time clock signal source 710, is electrically connected on a frequency eliminating circuit 720 in clock pulse signal source 710 and is electrically connected on frequency eliminating circuit 720.Clock pulse signal source 710 is used to provide a pulse reference clock (reference clock signal) RCLK.On real the work, clock pulse signal source 710 can but be not limited to a phase-locked loop (PLL) and realize.In the present embodiment, the frequency of the pulse reference clock RCLK that exported of clock pulse signal source 710 system immobilizes.In addition, in Fig. 7, enable signal generation device 730 utilizes pulse reference clock RCLK to be used as its work clock pulse.Below will further specify both function modes of frequency eliminating circuit 720 and enable signal generation device 730.
730 of enable signal generation devices can carry out frequency elimination to the frequency elimination signal FD_1 that frequency eliminating circuit 720 is exported, to produce at least one enable signal ES.Because respectively this enable signal ES carries out the frequency elimination gained to frequency elimination signal FD_1, thus can know by inference respectively this enable signal ES also can with the justified margin of system clock pulse SCLK.On real the work, enable signal generation device 730 can utilize one or more counters to realize.
In the present embodiment, frequency eliminating circuit 720 changes or opportunity of the frequency of switched system time clock SCLK, can be selected in the time point at the edge of corresponding frequency elimination signal FD_1, that is corresponding to the pulse wave border (boundary) of frequency elimination signal FD_1.As previously mentioned, the frequency of frequency elimination signal FD_1 and the frequency of pulse reference clock RCLK can be a fixing multiplying power relation, so the frequency of switched system time clock SCLK can't have influence on the frequency of frequency elimination signal FD_1.In other words, change or during the frequency of switched system time clock SCLK, frequency or the pulse wave cycle of respectively this enable signal ES that enable signal generation device 730 is produced can't be interfered when frequency eliminating circuit 720.In addition, because the time point of system clock pulse SCLK frequency shift is corresponding to the edge (or pulse wave border) of frequency elimination signal FD_1, so respectively this enable signal ES that is produced according to frequency elimination signal FD_1 can be aligned in the system clock pulse SCLK after the frequency shift equally.Thus, can guarantee that just this enable signal ES respectively can not produce the situation of drift (drift) when system clock pulse SCLK frequency is switched.
Please refer to Fig. 8 and Fig. 9.Fig. 8 is the calcspar of one first embodiment 800 of frequency eliminating circuit 720 of the present invention, and Fig. 9 is the sequential chart 900 of an embodiment of frequency eliminating circuit 800 switched system time clock SCLK frequencies.As shown in Figure 8, frequency eliminating circuit 800 includes a counter 810, is electrically connected on clock pulse signal source 710; One decision unit 820 is electrically connected on counter 810; And a time clock lock control unit (clock-gating unit) 830, be electrically connected on decision unit 820 and clock pulse signal source 710.For ease of explanation, frequency of the pulse reference clock RCLK that is exported in this hypothesis clock pulse signal source 710 is 52MHz, and the fixed-frequency of the frequency elimination signal FD_1 that produced of frequency eliminating circuit 800 be pulse reference clock RCLK frequency 1/4.In the present embodiment, counter 810 can repeat from 3 to count to 0 counting action according to pulse reference clock RCLK, and constantly count value CNT is exported to the decision unit 820 of back level.Whenever count value CNT equals at 0 o'clock, counter 810 just can pulse wave of triggering for generating, so the frequency of the frequency elimination signal FD_1 that counter 810 is exported can fixedly be 1/4 of pulse reference clock RCLK, that is 13MHz.
In sequential chart 900, the ES signal is represented one of them of enable signal that enable signal generation device 730 produced, and ES_CNT then counts a count value sequence of gained to the pulse wave of frequency elimination signal FD_1 for a counter (not shown) that is used for producing this enable signal ES in the enable signal generation device 730.In the present embodiment, when this counter arrives n in its count value ES_CNT, the pulse wave of an enable signal ES of triggering for generating.For example, if the frequency of this enable signal ES is 13/12MHz (enable signal QBIT_EN as the aforementioned), then n can be set at 11; If the frequency of this enable signal ES is 13/5MHz (enable signal X_EN as the aforementioned), then n can be set at 4, and the rest may be inferred.
On the other hand, decision unit 820 can produce an output signal CLK_EN according to the count value CNT that a controlling value CV and counter 810 are exported.In the present embodiment, the count value CNT that is received whenever decision unit 820 equals at 0 o'clock (that is the time point on the pulse wave border of corresponding frequency elimination signal FD_1), and decision unit 820 just can be written into controlling value CV and decide its mode of operation.If do not have new controlling value CV at that time, then determine unit 820 to continue running according to the controlling value CV that last time was written into.Change another angle, only have the opportunity that decision unit 820 switches or change its mode of operation at count value CNT to equal just can take place in 0 o'clock.For ease of the running of explanation decision unit 820, CV has four kinds of effective values (valid value) in this hypothesis controlling value: " 00 ", " 01 ", " 10 " reach " 11 ", respectively the frequency setting of corresponding 52MHz, 39MHz, 26MHz and 13MHz.In sequential chart shown in Figure 9 900, decision unit 820 original loaded controlling value CV are " 00 " (that is frequency setting of corresponding 52MHz).When the time 902 (that is count value CNT is 0), decision unit 820 can be written into new controlling value " 10 " (that is frequency setting of corresponding 26MHz).
In the present embodiment, if decision unit 820 loaded controlling value CV equal " 00 " (before the time 902 as sequential chart 900), no matter the count value CNT that is received is 0,1,2 or 3 o'clock, decision unit 820 all can be made as output signal CLK_EN one first logic level (being logical one in the present embodiment).If controlling value CV is " 10 " (after the time 902 as sequential chart 900), then determine unit 820 to be 0 or output signal CLK_EN to be made as logical one at 2 o'clock, and be 1 or output signal CLK_EN be made as logical zero at 3 o'clock in count value CNT in the count value CNT that is received.In addition, if decision unit 820 loaded controlling value CV are " 11 " (that is frequency setting of corresponding 13MHz), determine that then unit 820 can be output signal CLK_EN to be made as one first logic level (for example logical one) at 0 o'clock in the count value CNT that is received, and be 1,2 or output signal CLK_EN be made as one second logic level (for example logical zero) at 3 o'clock in count value CNT.If controlling value CV is " 01 " (that is frequency setting of corresponding 39MHz), then determines unit 820 to be 0,1 or output signal CLK_EN to be made as logical one at 2 o'clock, and be output signal CLK_EN to be made as logical zero at 3 o'clock in count value CNT in count value CNT.
Then, time clock lock control unit 830 can produce system clock pulse SCLK according to output signal CLK_EN and pulse reference clock RCLK.In the present embodiment, time clock lock control unit 830 be one with door (an AND gate), be used for to pulse reference clock RCLK and output signal CLK_EN carry out one with (AND) computing with generation system clock pulse SCLK.Know as those who familiarize themselves with the technology and to know, time clock lock control unit 830 is also being played the part of the role of balance time clock tree (clock tree) usually.On real the work, time clock lock control unit 830 also can use instead one or door (an OR gate) realize that only this moment, output signal CLK_EN needed earlier to handle through oppositely (invert) before input clock pulse lock control unit.
As previously mentioned, the fixed-frequency of the frequency elimination signal FD_1 that the counter 810 of present embodiment is exported is 13MHz, after so frequency eliminating circuit 800 switches to 26MHz with the frequency of system clock pulse SCLK by 52MHz in the time 902, the count cycle that is used for producing the counter of this enable signal ES in the enable signal generation device 730 can't change.Therefore, the cycle of this enable signal ES can not change to some extent yet.Again, because the time point (being the time 902) of system clock pulse SCLK frequency shift is the edge corresponding to this frequency elimination signal FD_1, so this enable signal ES that is produced according to frequency elimination signal FD_1 can be aligned in the system clock pulse SCLK after the frequency shift.In other words, this enable signal ES can not produce the situation of drift (drift) when the frequency of system clock pulse SCLK is switched.Same reason, other enable signals that enable signal generation device 730 is produced do not have drift yet when the frequency of system clock pulse SCLK is switched problem takes place.
Please refer to Figure 10 to Figure 12.Figure 10 is switched to the frequency of system clock pulse SCLK the sequential chart 1000 of 13MHz by 52MHz for frequency eliminating circuit 800.Figure 11 is switched to the frequency of system clock pulse SCLK the sequential chart 1100 of 13MHz by 26MHz for frequency eliminating circuit 800.Figure 12 is then switched to the frequency of system clock pulse SCLK the sequential chart 1200 of 52MHz by 13MHz for frequency eliminating circuit 800.In sequential chart shown in Figure 10 1000, decision unit 820 original loaded controlling value CV are " 00 " (that is frequency setting of corresponding 52MHz).When the time 1002 (that is count value CNT is 0), decision unit 820 can be written into new controlling value " 11 " (that is frequency setting of corresponding 13MHz).Shown in sequential chart 1000, after frequency eliminating circuit 800 switched to 13MHz with the frequency of system clock pulse SCLK by 52MHz in the time 1002, the enable signal ES that enable signal generation device 730 is exported can't produce the situation of drift.In sequential chart 1100, after frequency eliminating circuit 800 switched to 13MHz with the frequency of system clock pulse SCLK by 26MHz in the time 1102, the enable signal ES that enable signal generation device 730 is exported also can not produce the situation of drift.In addition, shown in sequential chart 1200, after frequency eliminating circuit 800 switched to 52MHz with the frequency of system clock pulse SCLK by 26MHz in the time 1202, enable signal ES also can not produce the situation of drift.
By can finding in the above stated specification, the running of counter 810 can't be subjected to the influence that determines that unit 820 loaded controlling value CV change, so the fixed-frequency of frequency elimination signal FD_1 is 1/4 (that is 13MHz) of pulse reference clock RCLK.Therefore, the counter in the enable signal generation device 730 is according to the count value ES_CNT of frequency elimination signal FD_1 counting gained, the influence that also uncontrolled value CV changes.In other words, when the frequency eliminating circuit 800 of present embodiment came the frequency of switched system time clock SCLK according to controlling value CV, the enable signal ES that enable signal generation device 730 is exported produced the situation of drift.
Please refer to Figure 13, its illustrate is the calcspar of one second embodiment 1300 of frequency eliminating circuit 720 of the present invention.As shown in the figure, frequency eliminating circuit 1300 includes a counter 810, a decision unit 820 and a time clock lock control unit 1340, and wherein counter 810 and decision unit 820 are identical in fact with previous embodiment, so no longer add to give unnecessary details.The place different with aforementioned frequency eliminating circuit 800, being that frequency eliminating circuit 1300 includes in addition fastens lock device (latch) 1330, be electrically connected between decision unit 820 and the time clock lock control unit 1340, be used for according to this output signal of pulse reference clock RCLK bolt-lock (latching) CLK_EN to produce a delayed clock pulse LCLK_1.In the present embodiment, time clock lock control unit 1340 produces system clock pulse SCLK according to delayed clock pulse LCLK_1 and pulse reference clock RCLK.By the setting of fastening lock device 1330, frequency eliminating circuit 1300 can further reduce the disturbance situation (glitch) among the system clock pulse SCLK, with the quality of elevator system time clock SCLK.Similarly, time clock lock control unit 1340 can with one with the door or one or the door realize.
In the foregoing embodiments, enable signal generation device 730 utilizes pulse reference clock RCLK to be used as its work clock pulse, but practical application of the present invention is not limited thereto.For example, Figure 14 is according to the calcspar of the system clock pulse switching device 1400 that the third embodiment of the present invention illustrated.System clock pulse switching device 1400 includes a time clock signal source 710, a frequency eliminating circuit 720 and an activation signal generation device 1430, and wherein the running of clock pulse signal source 710 and frequency eliminating circuit 720 is all identical in fact with previous embodiment with embodiment.With the different place of aforementioned all embodiment, be the enable signal generation device 1430 in the system clock pulse switching device 1400, the system clock pulse SCLK that utilizes frequency eliminating circuit 720 to be exported is used as its work clock pulse.On real the work, enable signal generation device 1430 also can utilize the signal of other self-reference time clock RCLK or system clock pulse SCLK frequency elimination gained to be used as the work clock pulse.Similarly, enable signal generation device 1430 can utilize one or more counters to realize.
Figure 15 one of illustrates the calcspar of system clock pulse switching device 1500 according to the fourth embodiment of the present invention.As shown in figure 15, system clock pulse switching device 1500 includes a time clock signal source 710, is electrically connected on a frequency eliminating circuit 1520 and an activation signal generation device 1530 in clock pulse signal source 710.In the present embodiment, the pulse reference clock RCLK that enable signal generation device 1530 can be exported clock pulse signal source 710 carries out frequency elimination, to produce at least one enable signal ES, frequency eliminating circuit 1520 then can carry out frequency elimination to produce a system clock pulse SCLK to this pulse reference clock RCLK according to a controlling value CV.When running, system clock pulse switching device 1500 can utilize a reset signal RST to come synchronous replacement enable signal generation device 1530 and frequency eliminating circuit 1520, makes both begin synchronously pulse reference clock RCLK is carried out the frequency elimination running.By this mode, can make the justified margin (edge-aligned) of the system clock pulse that this at least one enable signal that enable signal generation device 1530 produced all produced with frequency eliminating circuit 1520.
In addition, if enable signal generation device 1530 only is used for producing single enable signal ES, then frequency eliminating circuit 1520 can be selected in the time point to a edge that should enable signal ES, is written into whether controlling value CV adjusts this system clock pulse SCLK with decision frequency.In the present embodiment, if the loaded at that time controlling value CV of frequency eliminating circuit 1520 differs from the controlling value that last time was written into, then frequency eliminating circuit 1520 is understood the frequency of coming Adjustment System time clock SCLK according to new controlling value CV; If controlling value CV did not change or do not have new controlling value at that time, then determine unit 820 to continue running according to the controlling value CV that last time was written into.If enable signal generation device 1530 is used for producing a plurality of enable signals, then frequency eliminating circuit 1520 can be selected in to one of should a plurality of enable signals the time point of common edge be written into controlling value CV.In other words, frequency eliminating circuit 1520 only can be chosen in the common edge switching of this enable signal or change its frequency elimination operating mode.Thus, when the frequency of frequency eliminating circuit 1520 switched system time clock SCLK, the situation that the enable signal ES that enable signal generation device 1530 is produced does not just have drift takes place.From then on an angle, both carry out independently frequency elimination running to pulse reference clock RCLK synchronously frequency eliminating circuit 1520 and enable signal generation device 1530.
Please refer to Figure 16 and Figure 17.Figure 16 illustrate is the calcspar of one first embodiment 1600 of frequency eliminating circuit 1520 of the present invention.Frequency eliminating circuit 1600 comprises a counter 1610, is electrically connected on clock pulse signal source 710, is used for producing a frequency elimination signal FD_2 according to pulse reference clock RCLK and controlling value CV; One time clock lock control unit 1620 is electrically connected on counter 1610 and clock pulse signal source 710, is used for producing system clock pulse SCLK according to this frequency elimination signal FD_2 and pulse reference clock RCLK; And a control module 1630, with deciding counter 1610 to be written into the opportunity of this controlling value CV.Figure 17 is the calcspar of one second embodiment 1700 of frequency eliminating circuit 1520 of the present invention.Frequency eliminating circuit 1700 utilizes counter 1610 to receive controlling value CV via control module 1630 equally, and produces frequency elimination signal FD_2 according to this controlling value CV.Frequency eliminating circuit 1700 also can utilize a bolt lock device 1720 that is electrically connected on counter 1610, according to this frequency elimination signal of pulse reference clock RCLK bolt-lock (latching) FD_2 to produce a delayed clock pulse LCLK_2.Afterwards, frequency eliminating circuit 1700 can utilize a time clock lock control unit 1730 to produce this system clock pulse SCLK according to this delayed clock pulse LCLK_2 and pulse reference clock RCLK.No matter be frequency eliminating circuit 1600 or 1700, all can be chosen in the time point at the common edge of this enable signal ES that corresponding enable signal generation device 1530 produced, upgrade the controlling value CV of enter counter 1610, to change the frequency of frequency elimination signal FD_2.In addition, identical with previous embodiment, time clock lock control unit 1620 and time clock lock control unit 1730 all can utilize one with door or one or door realize its function.
Note that the counter among aforementioned each embodiment can be designed to upwards counting or counting downwards on real the work, and be not limited to specific count mode.
The above only is preferred embodiment of the present invention, and all equalizations of being done according to the present patent application claim change and modify, and all should belong to covering scope of the present invention.
Claims (45)
1. a system clock pulse switching device is characterized in that, includes:
One time clock signal source is used to provide a pulse reference clock;
One frequency eliminating circuit is electrically connected on this clock pulse signal source, is used for this pulse reference clock is carried out frequency elimination to produce a frequency elimination signal and a system clock pulse; And
One activation signal generation device is electrically connected on this frequency eliminating circuit, is used for this frequency elimination signal is carried out frequency elimination to produce at least one enable signal;
Wherein this frequency eliminating circuit can switch the frequency of this system clock pulse in the time point to a edge that should the frequency elimination signal.
2. the system as claimed in claim 1 time clock switching device shifter is characterized in that, this clock pulse signal source is a phase-locked loop.
3. the system as claimed in claim 1 time clock switching device shifter is characterized in that, this enable signal generation device is to utilize this pulse reference clock and this system clock pulse one of them is used as its work clock pulse.
4. the system as claimed in claim 1 time clock switching device shifter is characterized in that, this enable signal generation device includes one or more counters.
5. the system as claimed in claim 1 time clock switching device shifter is characterized in that, the frequency of this pulse reference clock is the multiple of the frequency of this system clock pulse.
6. the system as claimed in claim 1 time clock switching device shifter is characterized in that, the frequency of this pulse reference clock is the multiple of the frequency of this frequency elimination signal.
7. the system as claimed in claim 1 time clock switching device shifter is characterized in that, the frequency of this system clock pulse is the multiple of the frequency of this frequency elimination signal.
8. the system as claimed in claim 1 time clock switching device shifter is characterized in that, this frequency eliminating circuit includes:
One counter is electrically connected on this clock pulse signal source, is used for producing this frequency elimination signal and exporting a count value according to this pulse reference clock;
One decision unit is electrically connected on this counter, in order to produce an output signal according to a controlling value and this count value; And
One time clock lock control unit is electrically connected on this decision unit and this clock pulse signal source, is used for producing this system clock pulse according to this output signal and this pulse reference clock.
9. system clock pulse switching device as claimed in claim 8 is characterized in that, this time clock lock control unit be one with the door or one or the door.
10. the system as claimed in claim 1 time clock switching device shifter is characterized in that, this frequency eliminating circuit includes:
One counter is electrically connected on this clock pulse signal source, is used for producing this frequency elimination signal and exporting a count value according to this pulse reference clock;
One decision unit is electrically connected on this counter, in order to produce an output signal according to a controlling value and this count value;
One fastens the lock device, is electrically connected on this decision unit, is used for according to this this output signal of pulse reference clock bolt-lock to produce a delayed clock pulse; And
One time clock lock control unit is electrically connected on this bolt lock device and this clock pulse signal source, is used for producing this system clock pulse according to this delayed clock pulse and this pulse reference clock.
11. system clock pulse switching device as claimed in claim 10 is characterized in that, this time clock lock control unit be one with the door or one or the door.
12. a system clock pulse switching device is characterized in that, includes:
One time clock signal source is used to provide a pulse reference clock;
One activation signal generation device is electrically connected on this clock pulse signal source, is used for producing at least one enable signal; And
One frequency eliminating circuit is electrically connected on this clock pulse signal source, be used for this pulse reference clock is carried out frequency elimination producing a system clock pulse, and in to one of should enable signal the time point at edge, switch the frequency of this system clock pulse.
13. system clock pulse switching device as claimed in claim 12 is characterized in that, this clock pulse signal source is a phase-locked loop.
14. system clock pulse switching device as claimed in claim 12, it is characterized in that, this enable signal generation device can produce the enable signal of a plurality of different frequencies, and this frequency eliminating circuit switches the frequency of this system clock pulse in the time point to a common edge that should a plurality of enable signals.
15. system clock pulse switching device as claimed in claim 12 is characterized in that, the frequency of this pulse reference clock is the multiple of the frequency of this system clock pulse.
16. system clock pulse switching device as claimed in claim 12 is characterized in that, the frequency of this pulse reference clock is the multiple of the frequency of this enable signal.
17. system clock pulse switching device as claimed in claim 12 is characterized in that, the frequency of this system clock pulse is the multiple of the frequency of this enable signal.
18. system clock pulse switching device as claimed in claim 12 is characterized in that, this frequency eliminating circuit includes:
One counter is electrically connected on this clock pulse signal source, is used for producing a frequency elimination signal according to this pulse reference clock and a controlling value;
One control module is electrically connected on this counter, is used for controlling the opportunity that this controlling value is written into this counter; And
One time clock lock control unit is electrically connected on this counter and this clock pulse signal source, is used for producing this system clock pulse according to this frequency elimination signal and this pulse reference clock.
19. system clock pulse switching device as claimed in claim 18 is characterized in that, this time clock lock control unit be one with the door or one or the door.
20. system clock pulse switching device as claimed in claim 12 is characterized in that, this frequency eliminating circuit includes:
One counter is electrically connected on this clock pulse signal source, is used for producing a frequency elimination signal according to this pulse reference clock and a controlling value;
One control module is electrically connected on this counter, is used for controlling the opportunity that this controlling value is written into this counter;
One fastens the lock device, is electrically connected on this counter, is used for according to this frequency elimination signal of this pulse reference clock bolt-lock to produce a delayed clock pulse; And
One time clock lock control unit is electrically connected on this bolt lock device and this clock pulse signal source, is used for producing this system clock pulse according to this delayed clock pulse and this pulse reference clock.
21. system clock pulse switching device as claimed in claim 20 is characterized in that, this time clock lock control unit be one with the door or one or the door.
22. system clock pulse switching device as claimed in claim 12 is characterized in that, this enable signal generation device and this frequency eliminating circuit can be reset synchronously according to a reset signal.
23. system clock pulse switching device as claimed in claim 12 is characterized in that, other includes:
One switches counter, is used for counting this system clock pulse, to produce a count value;
One switches signal generator, is electrically connected on this toggle count device, is used for when this count value reaches a preset value, produces one and switches signal; And
One control module is electrically connected on this switching signal generator and this frequency eliminating circuit, is used for controlling the frequency that this frequency eliminating circuit switches this system clock pulse when this switching signal produces;
Wherein this preset value is corresponding with the time point at an edge of this enable signal.
24. system clock pulse switching device as claimed in claim 12, it is characterized in that, this enable signal generation device further is electrically connected on this frequency eliminating circuit, and this enable signal generation device carries out frequency elimination to produce this enable signal to one of them of this system clock pulse and this pulse reference clock.
25. the method for a switched system clock frequency is characterized in that, includes:
(a) provide a pulse reference clock;
(b) this pulse reference clock is carried out frequency elimination to produce a frequency elimination signal;
(c) produce a system clock pulse according to this pulse reference clock;
(d) this frequency elimination signal is carried out frequency elimination to produce at least one enable signal; And
(e) in to one of should the frequency elimination signal time point at edge, switch the frequency of this system clock pulse.
26. method as claimed in claim 25 is characterized in that, described step (d) further includes: this frequency elimination signal is carried out frequency elimination to produce the enable signal of a plurality of different frequencies; And described step (e) further includes: in the time point to a common edge that should a plurality of enable signals, switch the frequency of this system clock pulse.
27. method as claimed in claim 25 is characterized in that, the frequency of this pulse reference clock is the multiple of the frequency of this system clock pulse.
28. method as claimed in claim 25 is characterized in that, the frequency of this pulse reference clock is the multiple of the frequency of this frequency elimination signal.
29. method as claimed in claim 25 is characterized in that, the frequency of this system clock pulse is the multiple of the frequency of this frequency elimination signal.
30. method as claimed in claim 25 is characterized in that, step (c) includes in addition:
Produce a count value according to this pulse reference clock;
Produce an output signal according to a controlling value and this count value; And
According to this pulse reference clock this output signal is carried out the control of time clock lock to produce this system clock pulse.
31. method as claimed in claim 30 is characterized in that, this time clock lock control step includes:
To this pulse reference clock and this output signal carry out one with a computing or an exclusive disjunction.
32. method as claimed in claim 25 is characterized in that, step (c) includes in addition:
Produce a count value according to this pulse reference clock;
Produce an output signal according to a controlling value and this count value;
According to this this output signal of pulse reference clock bolt-lock to produce a delayed clock pulse; And
According to this pulse reference clock this delayed clock pulse is carried out the control of time clock lock to produce this system clock pulse.
33. method as claimed in claim 32 is characterized in that, this time clock lock control step includes:
To this pulse reference clock and this delayed clock pulse carry out one with a computing or an exclusive disjunction.
34. the method for a switched system clock frequency is characterized in that, includes:
(a) provide a pulse reference clock;
(b) produce at least one enable signal according to this pulse reference clock;
(c) this pulse reference clock is carried out frequency elimination to produce a system clock pulse; And
(d) in to one of should enable signal point in the edge, switch the frequency of this system clock pulse.
35. method as claimed in claim 34, it is characterized in that, step (b) includes: this pulse reference clock is carried out frequency elimination to produce the enable signal of a plurality of different frequencies, and step (d) includes: in to one of should a plurality of enable signals the time point of common edge, switch the frequency of this system clock pulse.
36. method as claimed in claim 34 is characterized in that, the frequency of this pulse reference clock is the multiple of the frequency of this system clock pulse.
37. method as claimed in claim 34 is characterized in that, the frequency of this pulse reference clock is the multiple of the frequency of this enable signal.
38. method as claimed in claim 34 is characterized in that, the frequency of this system clock pulse is the multiple of the frequency of this enable signal.
39. method as claimed in claim 34 is characterized in that, step (c) includes:
Produce a frequency elimination signal according to this pulse reference clock and a controlling value; And
According to this pulse reference clock to this frequency elimination signal with carry out the control of time clock lock to produce this system clock pulse.
40. method as claimed in claim 39 is characterized in that, this time clock lock control step includes:
To this pulse reference clock and this delayed clock pulse carry out one with a computing or an exclusive disjunction.
41. method as claimed in claim 34 is characterized in that, step (c) includes:
Produce a frequency elimination signal according to this pulse reference clock and a controlling value;
According to this frequency elimination signal of this pulse reference clock bolt-lock to produce a delayed clock pulse; And
According to this pulse reference clock this delayed clock pulse is carried out the control of time clock lock to produce this system clock pulse.
42. method as claimed in claim 41 is characterized in that, this time clock lock control step includes:
To this pulse reference clock and this delayed clock pulse carry out one with a computing or an exclusive disjunction.
43. method as claimed in claim 34 is characterized in that, step (b) and step (c) begin to carry out synchronously.
44. method as claimed in claim 34 is characterized in that, this enable signal is that one of them of this system clock pulse and this pulse reference clock carried out frequency elimination and produced.
45. method as claimed in claim 34 is characterized in that, step (d) includes in addition:
Count this system clock pulse to produce a count value; And
When this count value reaches a preset value, switch the frequency of this system clock pulse;
Wherein this preset value is corresponding with the time point at an edge of this enable signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005100732320A CN100381968C (en) | 2004-11-01 | 2005-06-01 | System clock pulse switching device and method for switching its frequency |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200410088770.2 | 2004-11-01 | ||
| CN200410088770 | 2004-11-01 | ||
| CNB2005100732320A CN100381968C (en) | 2004-11-01 | 2005-06-01 | System clock pulse switching device and method for switching its frequency |
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| CN1770056A CN1770056A (en) | 2006-05-10 |
| CN100381968C true CN100381968C (en) | 2008-04-16 |
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| CNB2005100732320A Expired - Fee Related CN100381968C (en) | 2004-11-01 | 2005-06-01 | System clock pulse switching device and method for switching its frequency |
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| CN100511089C (en) * | 2007-04-20 | 2009-07-08 | 威盛电子股份有限公司 | Clock switching circuit and method for switching clock signal |
| CN113268104B (en) * | 2021-05-27 | 2023-09-26 | 瑞芯微电子股份有限公司 | Clock counting synchronization method and device |
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| WO2002013201A2 (en) * | 2000-08-03 | 2002-02-14 | Broadcom Corporation | Circuit and method for multi-phase alignment |
| CN1090779C (en) * | 1995-03-29 | 2002-09-11 | 艾利森电话股份有限公司 | Clock control system and method |
| US20030074595A1 (en) * | 2001-10-16 | 2003-04-17 | International Business Machines Corporation | Dynamic clock generator with rising edge alignment enable signal |
| US6653867B1 (en) * | 2001-06-04 | 2003-11-25 | Advanced Micro Devices, Inc. | Apparatus and method for providing a smooth transition between two clock signals |
| CN1475887A (en) * | 2002-08-15 | 2004-02-18 | 联发科技股份有限公司 | Clock pulse switchover structure and its clock pulse switchover method |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1090779C (en) * | 1995-03-29 | 2002-09-11 | 艾利森电话股份有限公司 | Clock control system and method |
| WO2002013201A2 (en) * | 2000-08-03 | 2002-02-14 | Broadcom Corporation | Circuit and method for multi-phase alignment |
| US6653867B1 (en) * | 2001-06-04 | 2003-11-25 | Advanced Micro Devices, Inc. | Apparatus and method for providing a smooth transition between two clock signals |
| US20030074595A1 (en) * | 2001-10-16 | 2003-04-17 | International Business Machines Corporation | Dynamic clock generator with rising edge alignment enable signal |
| CN1475887A (en) * | 2002-08-15 | 2004-02-18 | 联发科技股份有限公司 | Clock pulse switchover structure and its clock pulse switchover method |
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