CN205407784U - Pre divider - Google Patents
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- CN205407784U CN205407784U CN201520835032.3U CN201520835032U CN205407784U CN 205407784 U CN205407784 U CN 205407784U CN 201520835032 U CN201520835032 U CN 201520835032U CN 205407784 U CN205407784 U CN 205407784U
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- outfan
- lock
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- frequency
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Abstract
The utility model provides a pre divider contains: the receiving element who contains input, feedback end and output, a plurality of frequency division unit that connect step by step, wherein, preceding one -level output links to each other with back one -level control end among every frequency division unit, at least one frequency division unit's output passes through feedback end with the receiving terminal links to each other, and wherein, first frequency division unit's input is connected receiving element's output, first frequency division unit's control end connected system clock output end, subsequent frequency division unit carries out frequency division processing according to the signal of receiving. The utility model discloses only be in the clock signal control of high frequency by first frequency division unit, other frequency division unit all are in low frequency clock signal, and consumption that can greatly reduced pre divider reaches 10GHz with improvement signal processing speed.
Description
Technical field
This utility model relates to frequency splitting technology, particularly to HIgh speed predcaler.
Background technology
Pre-divider is mainly used in including in GNSS/GSM/TD/WCDMA/LTE/BLE rf frequency synthesizer.HIgh speed predcaler is the nucleus module of PLL, and speed determines whole PLL operating frequency, and at present, common pre-divider adopts structure as shown in Figure 1 to carry out scaling down processing.The more high power consumption of the frequency of this kind of pre-divider is more big.This is owing to all of latch is all operated in highest frequency, which results in too high power consumption.
Accordingly, it would be desirable to prior art is improved.
Utility model content
The purpose of this utility model is in that to provide a kind of pre-divider, the problem that power consumption for solving pre-divider of the prior art is too high.
For solving above-mentioned technical problem, embodiment of the present utility model provides a kind of pre-divider, comprises: the reception unit comprising input, feedback end and outfan；The multiple frequency units connected step by step, wherein, in each frequency unit, previous stage outfan is connected with rear stage control end, the outfan of at least one described frequency unit is connected with described receiving terminal by described feedback end, wherein, the input of first frequency unit connects the outfan of described reception unit, and the control end connection system output terminal of clock of described first frequency unit, follow-up frequency unit divides according to received signal.
This utility model embodiment is in terms of existing technologies, the clock signal control of high frequency only it is in by first frequency unit, other frequency units are in low-frequency clock signal, it is possible to the power consumption and the raising conversion speed that are substantially reduced pre-divider reach 10GHz.
It addition, the feedback end in described reception unit receives the output signal of each frequency unit, it is possible to realize except 8 remove the frequency dividing designing requirement of 9.
It addition, described first frequency unit adopts lock and has the lock circuit of feedback function, it is possible to effective being carried out by clock signal of system removes 2 except 3 frequency dividings, in order to follow-up frequency unit carries out removing the scaling down processing that 8 except 9 based on this.
Accompanying drawing explanation
Fig. 1 is the structural representation of pre-divider in prior art；
Fig. 2 is the structural representation of a kind of embodiment of pre-divider of the present utility model；
Fig. 3 is the structural representation of the preferred implementation in pre-divider of the present utility model；
Fig. 4 is the sequential chart of the pre-divider shown in Fig. 3.
Detailed description of the invention
For making the purpose of this utility model, technical scheme and advantage clearly, below in conjunction with accompanying drawing, each embodiment of the present utility model is explained in detail.But, it will be understood by those skilled in the art that in each embodiment of this utility model, propose many ins and outs in order to make reader be more fully understood that the application.But, even without these ins and outs with based on the many variations of following embodiment and amendment, it is also possible to realize the application each claim technical scheme required for protection.
As in figure 2 it is shown, this utility model relates to a kind of pre-divider 1, comprising: receive unit 11 and multiple frequency unit 12.
Described reception unit 11 comprises input, feedback end and outfan.In figure 3, described input is MC end.
In the present embodiment, described reception unit 11 includes: the NAND Logic device of multi input pin and the phase inverter being connected with the outfan of described NAND Logic device；Wherein, an input pin in described NAND Logic device is arranged in the input of described reception unit, multiple input pins of described NAND Logic device are arranged in the feedback end of described reception unit, and wherein, each input pin in described feedback end is connected with the outfan of a frequency unit respectively.
Each described frequency unit 12 connects step by step, wherein, in each frequency unit 12, previous stage outfan is connected with rear stage control end, the outfan of at least one described frequency unit 12 is connected with described receiving terminal by described feedback end, wherein, the input of first frequency unit connects the outfan of described reception unit, and the control end connection system output terminal of clock of described first frequency unit, follow-up frequency unit divides according to received signal.
At this, each frequency unit is not all connected to each input pin in the feedback end of described reception unit.The feedback end received signal of described reception unit is relevant with frequency dividing.As it is shown on figure 3, in the present embodiment, be all connected with the feedback end of described reception unit 11 from the outfan of second frequency unit B2 each frequency unit started.Wherein, comprising lock in each frequency unit, each lock can be same model.
In the present embodiment, described first frequency unit B1 includes: two lock A1 and A2, and the control end of these two locks is all connected with described system clock outfan, and wherein A1 is in clock processing unit the most at a high speed.As shown in Figure 3.The outfan of the outfan of described lock A1 and another lock A2 feeds back to the input of described lock A1；The reversed-phase output of described lock A1 and the outfan of described reception unit are connected to the input of described lock A2 by NAND Logic device；The outfan of lock A1 is additionally coupled to the control end of rear stage frequency unit.
Follow-up each frequency unit can be identical structure, namely all includes: lock A3.Described lock A3 includes: input, control end, outfan and reversed-phase output；Wherein, the reversed-phase output of described lock A3 is connected with the input of self, and the end that controls of described lock A3 is connected with the outfan of previous stage and described feedback end.
Comprising three frequency units in pre-divider as shown in Figure 3, wherein, second identical with the 3rd frequency unit (B2, B3) structure.
Preset in the lock in each frequency unit all without temporary signal.The level signal that each lock receives along signal detection each input according to the upper jumping received, and currently received level signal is preserved, the level signal that output preserves before this.Each described lock has certain time-delay.Wherein, the time delay of the reversed-phase output of lock A1 is less than 1/2 clock signal of system.
When the input of described reception unit 11 receives high level, the work process of pre-divider as shown in Figure 3 is exemplified below:
Sequential chart shown in Figure 4, jump on first systematic clock signal becomes along time, time delay due to frequency unit B2 and B3, the level signal of the input feeding back to described reception unit is low level signal, then the outfan of MC end and frequency unit B2, B3 is via the NAND Logic device in described reception unit and phase inverter output low level (i.e. G end output low level).The outfan (i.e. B end) of the lock A1 in first frequency unit B1 exports the low level signal preserved, and the reversed-phase output (i.e. Bb end) of lock A1 exports high level signal, and preserves current low level signal；As the feedback circuit of described lock A1, the level signal that the input of lock A2 receives is that the level signal jointly exported by G end and Bb end obtains after NAND Logic device processes；Further, the outfan (i.e. D end) of described lock A2 and the B end of lock A1 feed back to the NAND Logic device in described first frequency unit B1.Now, the low level signal that the B end of described lock A1 exports transports to the control end (i.e. CLK end) of second frequency unit B2；Owing to the CLK end of the lock A3 in described second frequency unit B2 being jumped along effective, therefore, now lock A3 does not change the low level signal preserved.Described second frequency unit B2 output low level signal delivers to the feedback end of described reception unit and the control end of the 3rd frequency unit B3 respectively.Similar with second frequency unit B2, described 3rd frequency unit B3 also output low level signal.The like, identifying according to the sequential in Fig. 3, the 3rd frequency unit B3 finally exports except 8 remove the fractional frequency signal of 9.
It is worth mentioning that, each module involved in present embodiment and unit are logic module and logical block, and in actual applications, a logical block can be a physical location, can also be a part for a physical location, it is also possible to realize with the combination of multiple physical locations.Additionally, in order to highlight innovative part of the present utility model, unit less close for the technical problem relation proposed with solving this utility model is not introduced by present embodiment, but this is not intended that in present embodiment to be absent from other unit.
It will be understood by those skilled in the art that the respective embodiments described above are to realize specific embodiment of the utility model, and in actual applications, it is possible in the form and details it is done various change, without departing from spirit and scope of the present utility model.
Claims (5)
1. a pre-divider, it is characterised in that comprise:
Comprise the reception unit of input, feedback end and outfan；
The multiple frequency units connected step by step, wherein, in each frequency unit, previous stage outfan is connected with rear stage control end, the outfan of at least one described frequency unit is connected with described receiving terminal by described feedback end, wherein, the input of first frequency unit connects the outfan of described reception unit, and the control end connection system output terminal of clock of described first frequency unit, follow-up frequency unit divides according to received signal.
2. pre-divider according to claim 1, it is characterised in that described reception unit includes: the NAND Logic device of multi input pin and the phase inverter being connected with the outfan of described NAND Logic device；Wherein, an input pin in described NAND Logic device is arranged in the input of described reception unit, multiple input pins of described NAND Logic device are arranged in the feedback end of described reception unit, and wherein, each input pin in described feedback end is connected with the outfan of a frequency unit respectively.
3. pre-divider according to claim 1, it is characterised in that described first frequency unit includes: two lock A1 and A2, and the control end of these two locks is all connected with described system clock outfan；
The outfan of the outfan of one of them lock A1 and another lock A2 feeds back to the input of described lock A1；The reversed-phase output of described lock A1 and the outfan of described reception unit are connected to the input of described lock A2 by NAND Logic device；The outfan of lock A1 is additionally coupled to the control end of rear stage frequency unit.
4. the pre-divider according to claim 1 or 3, it is characterised in that follow-up frequency unit includes:
Lock A3, including: input, control end, outfan and reversed-phase output, wherein, the reversed-phase output of described lock A3 is connected with the input of self, and the end that controls of described lock A3 is connected with the outfan of previous stage and described feedback end.
5. the pre-divider according to claim 1 or 3, it is characterised in that the outfan of each frequency unit started from second frequency unit is all connected with the feedback end of described reception unit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520835032.3U CN205407784U (en) | 2015-10-26 | 2015-10-26 | Pre divider |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520835032.3U CN205407784U (en) | 2015-10-26 | 2015-10-26 | Pre divider |
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| Publication Number | Publication Date |
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| CN205407784U true CN205407784U (en) | 2016-07-27 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201520835032.3U Active CN205407784U (en) | 2015-10-26 | 2015-10-26 | Pre divider |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116545438A (en) * | 2023-07-03 | 2023-08-04 | 麦斯塔微电子(深圳)有限公司 | Frequency divider and multi-modulus frequency divider |
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2015
- 2015-10-26 CN CN201520835032.3U patent/CN205407784U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116545438A (en) * | 2023-07-03 | 2023-08-04 | 麦斯塔微电子(深圳)有限公司 | Frequency divider and multi-modulus frequency divider |
| CN116545438B (en) * | 2023-07-03 | 2023-11-03 | 麦斯塔微电子(深圳)有限公司 | Frequency divider and multi-modulus frequency divider |
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| C14 | Grant of patent or utility model | ||
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| TR01 | Transfer of patent right |
Effective date of registration: 20211122 Address after: 214101 room 214, No. 1, Yingbin North Road, Dongting street, Xishan District, Wuxi City, Jiangsu Province Patentee after: Zhicode core (Wuxi) communication technology Co.,Ltd. Address before: Room 1219, building 1, 100 Jinyu Road, Pudong New Area, Shanghai, 201206 Patentee before: SHANGHAI YB ELECTRONICS CO.,LTD. |