CN108429549B

CN108429549B - Homologous time sequence self-adaption method, device and chip

Info

Publication number: CN108429549B
Application number: CN201710080586.0A
Authority: CN
Inventors: 薛建林; 何智; 卢艳东
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2017-02-15
Filing date: 2017-02-15
Publication date: 2020-10-09
Anticipated expiration: 2037-02-15
Also published as: CN108429549A

Abstract

The embodiment of the application provides a method, a device and a chip for self-adapting of a homologous time sequence. Wherein, the device includes: the device comprises a multi-phase generator, an edge detector, a phase configurator and a data sampler; the multi-phase generator is used for generating phase clock signals of N equal-difference phases according to the clock signals; the edge detector is used for carrying out jumping edge detection on the data signal according to the N phase clock signals configured by the phase configurator and judging whether the data signal has jumping edges; the phase configurator is used for determining a sampling clock signal according to two phase clock signals with adjacent phases corresponding to the jumping edges when the edge detector determines that the data signal has the jumping edges; and the data sampler is used for sampling the data signal according to the sampling clock signal determined by the phase configurator to obtain a first sampling signal. The homologous time sequence self-adaptive device provided by the embodiment of the application simplifies the wiring complexity of the PCB, saves the occupied area of the PCB and reduces the cost.

Description

Homologous time sequence self-adaption method, device and chip

Technical Field

The embodiment of the application relates to the technical field of electronics, in particular to a method, a device and a chip for self-adapting of a homologous time sequence.

Background

In the design of Printed Circuit Board (PCB), the synchronous parallel Interface between chips is the main Interface form for interconnection between chips, for example, Media Independent Interface (MII). The synchronous parallel interface is a physical interface capable of providing timing information according to a specified performance level, and realizes transmission of a clock signal and a data signal between the sending end chip and the receiving end chip, so that the receiving end chip can sample the data signal according to the clock signal to obtain data.

At present, a sending end chip sends out a data signal and a clock signal simultaneously through a synchronous parallel interface, and a certain phase relation is kept between the data signal and the clock signal. Typically, the transition edge of the clock signal is at the center of the data signal to be sampled. In order to ensure that the phases of the data signal and the clock signal do not change when the data signal and the clock signal reach the receiving end chip, an equal-length wiring design is usually adopted on the PCB. Fig. 1 is a schematic diagram of a conventional PCB wiring, and as shown in fig. 1, a bent portion is a wiring specially designed for wiring with a long length.

However, the routing takes up additional area on the PCB, wasting PCB space, and also increasing the cost of the PCB.

Disclosure of Invention

The embodiment of the application provides a homologous timing sequence self-adaptive method, a homologous timing sequence self-adaptive device and a chip, which can simplify the wiring complexity of a PCB, save the occupied area of the PCB and reduce the cost.

In a first aspect, an embodiment of the present application provides a self-adaptive apparatus for homologous timing. The apparatus may include: a multiphase generator, an edge detector, a phase configurator and a data sampler. The multi-phase generator is respectively and electrically connected with the edge detector, the phase configurator and the data sampler, and the phase configurator is respectively and electrically connected with the edge detector and the data sampler. And the multiphase generator is used for acquiring the clock signal. And generating N phase clock signals with equal difference phases according to the clock signals. An edge detector for acquiring the data signal. And carrying out jump edge detection on the data signal according to the N phase clock signals configured by the phase configurator, and judging whether the data signal has jump edges. And the phase configurator is used for configuring the N phase clock signals for the edge detector. And when the edge detector determines that the data signal has a transition edge, determining a sampling clock signal according to two phase adjacent phase clock signals corresponding to the transition edge. And the data sampler is used for acquiring a data signal. And sampling the data signal according to the sampling clock signal determined by the phase configurator to obtain a first sampling signal.

With the homogeneous timing adaptive apparatus provided in the first aspect, the multiphase generator generates N phase clock signals. By means of these N phase clock signals, N phase segments with the same phase difference are obtained. The edge detector determines whether the data signal has a transition edge according to the N phase clock signals. If the data signal has a transition edge, the transition edge of the data signal is determined to be in a fixed phase segment. The phase configurator may then determine the sampling clock signal that matches the data signal based on the two phase-adjacent phase clock signals corresponding to the transition edges of the data signal. Because the sampling clock signal is determined in a phase segmentation mode, the phases of the data signal and the sampling clock signal can be matched, and therefore time sequence self-adaption is achieved. Equal-length wiring is not required to be designed in the inter-chip communication. The wiring complexity of the PCB is simplified, the occupied area of the PCB is saved, and the cost is reduced. And the saved PCB area can be designed with other circuits, thereby improving the effective utilization rate of the PCB area.

Optionally, in a possible implementation manner of the first aspect, the multi-phase generator may include: a phase locked loop and at least N D flip-flops. The phase-locked loops are electrically connected with clock pins of at least N D triggers respectively. The data input pin of the first D trigger is used for acquiring a clock signal, the data output pin of the first D trigger is electrically connected with the data input pin of the second D trigger, and the rest D triggers are electrically connected in sequence in the same way. The data output pins of N D triggers in the N D triggers output N phase clock signals with equal difference phases respectively. And the phase-locked loop is used for carrying out N times of frequency multiplication on the clock signal to obtain a frequency multiplication signal. And the D trigger is used for sampling the signal on the data input pin according to the frequency doubling signal.

A specific implementation of the multiphase generator is provided by the homogeneous timing adaptive apparatus provided by this possible embodiment. A phase-locked loop and at least N D flip-flops may be employed to generate N equal-difference phase clock signals.

Optionally, in a possible implementation manner of the first aspect, the number of D flip-flops may be N +2, and the phase clock signal is output from the third D flip-flop.

With the same source timing adaptation provided by this possible embodiment, the first D flip-flop and the second D flip-flop can be used to avoid metastability problems.

Optionally, in a possible implementation manner of the first aspect, the edge detector is specifically configured to: and respectively sampling the data signals according to two phase clock signals with adjacent phases in the N phase clock signals to obtain a second sampling signal and a third sampling signal. And if the XOR operation result of the second sampling signal and the third sampling signal is 1, determining that the data signal has a jump edge. And if the exclusive-or operation result of the second sampling signal and the third sampling signal is 0, determining that no transition edge exists in the data signal.

Optionally, in a possible implementation manner of the first aspect, the phase configurator is specifically configured to: any one of two phase-adjacent phase clock signals is taken as a first reference clock signal. A phase clock signal which is different from the first reference clock signal by M equal difference phases is used as a sampling clock signal.

Optionally, in a possible implementation manner of the first aspect, if the data signals are multiplexed, the homologous timing adaptive apparatus may further include a data synchronous sampler. The data synchronous sampler is electrically connected with the multiphase generator, the data sampler and the phase configurator respectively. The phase configurator is further configured to determine a synchronous sampling clock signal according to the sampling clock signal corresponding to each path of data signal. And the data synchronous sampler is used for sampling the first sampling signals respectively corresponding to each path of data signals according to the synchronous sampling clock signals determined by the phase configurator to obtain parallel sampling signals.

With the homologous timing adaptation apparatus provided by this possible embodiment, the homologous timing adaptation apparatus when the data signal is multiplexed is provided. The time sequence self-adaption of the multi-channel data signals is realized, the wiring complexity of the PCB is simplified, the occupied area of the PCB is saved, and the cost is reduced.

Optionally, in a possible implementation manner of the first aspect, the phase configurator is specifically configured to: taking the sampling clock signal with the largest phase in all the sampling clock signals as a second reference clock signal, and taking the sampling clock signal with the smallest phase as a third reference clock signal; and determining an equal difference phase between the phases of the second reference clock signal and a third reference clock signal in the next clock cycle, and taking the phase clock signal corresponding to the equal difference phase in the current clock cycle as a synchronous sampling clock signal.

Optionally, in a possible implementation manner of the first aspect, if the multiple data signals are processed in parallel, the phase configurator is further configured to: and determining sampling clock signals corresponding to each path of data signals in a preset time period.

By setting the preset time period, the source timing adaptive device provided by the possible embodiment can avoid the problem that the time for determining the synchronous sampling clock signal is increased because a certain path of data signal cannot determine the sampling clock signal.

Optionally, in a possible implementation manner of the first aspect, the edge detector performs transition edge detection on the data signal according to the N phase clock signals configured by the phase configurator, and determines whether the data signal has a transition edge, where a parallel processing manner or a serial processing manner may be used.

In a second aspect, an embodiment of the present application provides a method for homologous timing adaptation. Wherein, the method can comprise the following steps: a data signal and a clock signal are acquired. And generating N phase clock signals with equal difference phases according to the clock signals. And carrying out jump edge detection on the data signals according to the N phase clock signals, and judging whether the data signals have jump edges. And if the data signal has a jump edge, determining a sampling clock signal according to two phase clock signals with adjacent phases corresponding to the jump edge. And sampling the data signal according to the sampling clock signal to obtain a first sampling signal.

Optionally, in a possible implementation manner of the second aspect, generating phase clock signals with N equal-difference phases according to the clock signal may include: and carrying out N times of frequency multiplication on the clock signal by adopting a phase-locked loop to obtain a frequency multiplication signal. And sampling the clock signal by adopting a D trigger according to the frequency multiplication signal to obtain phase clock signals of N equal difference phases.

Optionally, in a possible implementation manner of the second aspect, the detecting a transition edge of the data signal according to the N phase clock signals, and determining whether the data signal has the transition edge may include: and respectively sampling the data signals according to two phase clock signals with adjacent phases in the N phase clock signals to obtain a second sampling signal and a third sampling signal. And if the XOR operation result of the second sampling signal and the third sampling signal is 1, determining that the data signal has a jump edge. And if the exclusive-or operation result of the second sampling signal and the third sampling signal is 0, determining that no transition edge exists in the data signal.

Optionally, in a possible implementation manner of the second aspect, determining the sampling clock signal according to two phase-adjacent phase clock signals corresponding to transition edges may include: any one of two phase-adjacent phase clock signals is taken as a first reference clock signal. A phase clock signal which is different from the first reference clock signal by M equal difference phases is used as a sampling clock signal.

Optionally, in a possible implementation manner of the second aspect, if the data signal is multiplexed, the method may further include: and determining synchronous sampling clock signals according to the sampling clock signals respectively corresponding to each path of data signals. And sampling the first sampling signals respectively corresponding to each path of data signals according to the synchronous sampling clock signals to obtain parallel sampling signals.

Optionally, in a possible implementation manner of the second aspect, determining the synchronous sampling clock signal according to the sampling clock signal corresponding to each data signal respectively may include: taking the sampling clock signal with the largest phase in all the sampling clock signals as a second reference clock signal, and taking the sampling clock signal with the smallest phase as a third reference clock signal; and determining an equal difference phase between the phases of the second reference clock signal and a third reference clock signal in the next clock cycle, and taking the phase clock signal corresponding to the equal difference phase in the current clock cycle as a synchronous sampling clock signal.

Optionally, in a possible implementation manner of the second aspect, if the multiple data signals are processed in parallel, before determining the synchronous sampling clock signal according to the sampling clock signal corresponding to each data signal, the method may further include: and determining sampling clock signals corresponding to each path of data signals in a preset time period.

In a third aspect, embodiments of the present application provide a chip. The chip may include the homologous timing adaptive apparatus provided in any embodiment of the present application.

With reference to the first aspect and the possible embodiments of the first aspect, the second aspect and the possible embodiments of the second aspect, and the third aspect, the frequency of the phase clock signal is the same as the frequency of the clock signal, and N is a positive integer greater than 4. M is a positive integer greater than 1 and less than N. The sampling clock signal and the first reference clock signal are located in one period of the clock signal. The synchronous sampling clock signal and the second reference clock signal are located in one period of the clock signal.

The embodiment of the application provides a method, a device and a chip for self-adapting of a homologous time sequence. Wherein, the device includes: a multiphase generator, an edge detector, a phase configurator and a data sampler. The homologous timing sequence self-adaptive device provided by the embodiment of the application determines the sampling clock signal matched with the data signal in a phase segmentation mode, and does not need to perform equal-length wiring among chips. The wiring complexity of the PCB is simplified, the occupied area of the PCB is saved, and the cost is reduced.

Drawings

FIG. 1 is a schematic diagram of a conventional PCB layout;

fig. 2 is a schematic structural diagram of a homologous timing adaptive apparatus according to an embodiment of the present disclosure;

fig. 3 is a signal flow diagram of a homologous timing adaptive apparatus according to an embodiment of the present application;

fig. 4 is a schematic structural diagram of a multi-phase generator according to an embodiment of the present disclosure;

fig. 5 is a schematic diagram of determining whether a data signal has a transition edge according to an embodiment of the present disclosure;

fig. 6 is a flowchart of a method for self-adapting a source timing according to an embodiment of the present application;

fig. 7 is a flowchart of another implementation manner of a homologous timing adaptation method according to an embodiment of the present application;

fig. 8 is a schematic structural diagram of a chip provided in an embodiment of the present application.

Detailed Description

Fig. 2 is a schematic structural diagram of a homologous timing adaptive apparatus according to an embodiment of the present disclosure, and fig. 3 is a signal flow diagram of the homologous timing adaptive apparatus according to the embodiment of the present disclosure. The homologous timing sequence self-adaptive device provided by the embodiment of the application can be applied to chips, and the chips can be used as receiving end chips in a communication scene among the chips. As shown in fig. 2 and fig. 3, the apparatus for self-adapting to a source timing provided in an embodiment of the present application may include: a multiphase generator 11, an edge detector 12, a phase configurator 13 and a data sampler 14.

The multiphase generator 11 is electrically connected to the edge detector 12, the phase configurator 13, and the data sampler 14, respectively, and the phase configurator 13 is electrically connected to the edge detector 12 and the data sampler 14, respectively.

A multiphase generator 11 for obtaining a clock signal. And generating N phase clock signals with equal difference phases according to the clock signals. The frequency of the phase clock signal is the same as the frequency of the clock signal, and N may be a positive integer greater than 4.

An edge detector 12 for acquiring the data signal. And detecting the jump edge of the data signal according to the N phase clock signals configured by the phase configurator 13, and judging whether the data signal has the jump edge.

A phase configurator 13 for configuring the edge detector 12 with N phase clock signals. When the edge detector 12 determines that the data signal has a transition edge, the sampling clock signal is determined according to two phase-adjacent phase clock signals corresponding to the transition edge.

A data sampler 14 for acquiring a data signal. The data signal is sampled according to the sampling clock signal determined by the phase configurator 13 to obtain a first sampling signal.

Specifically, the multiphase generator 11 may obtain a clock signal. The edge detector 12 and the data sampler 14 may acquire a data signal. The data signal and the clock signal are the data signal and the clock signal sent by the sending end chip.

The multiphase generator 11 generates N phase clock signals with equal phase difference according to the clock signal. The N phase clock signals are at the same frequency as the clock signals, but are out of phase. By the N phase clock signals, N phase segments with the same phase difference can be obtained, and the division of the phase is refined. In this embodiment, the value of N is not particularly limited. The larger the value of N is, the smaller the equiphase phase is, and the smaller the phase difference of each phase segment is. For example: if N is 8 and the phase of the clock signal is 0, the equiphase phase may be 360/8-45. The phase difference for each phase segment may be 45. The phases of the N equal-difference phase clock signals may be, in order: 0. 45, 90, 135, 180, 225, 270, 315. The N phase segments may be: 0-45, 45-90, 90-135, 135-180, 180-225, 225-270, 270-315, 315-0. If N is 9 and the phase of the clock signal is 40, the equiphase phase may be 360/9-40. The phase difference for each phase segment may be 40. The phases of the N equal-difference phase clock signals may be, in order: 40. 80, 120, 160, 200, 240, 280, 320, 0. The N phase segments may be: 40-80, 80-120, 120-160, 160-200, 200-240, 240-280, 280-320, 320-0, 0-40.

The multi-phase generator 11 transmits the generated N phase clock signals to the phase configurator 13. The phase configurator 13 configures the N phase clock signals for the edge detector 12. The edge detector 12 samples the data signal according to the N phase clock signals, and detects whether a transition edge exists in the data signal.

Specifically, the transition edge of the data signal indicates that the data signal may carry valid data information during a period of time from the transition edge. Wherein the transition edge may comprise a rising edge or a falling edge. Thus, the sampling position of the data signal can be determined from the transition edge of the data signal. If the data signal is sampled according to two phase clock signals with different phases respectively, and the data signal is determined to have a transition edge, the transition edge of the data signal is positioned between the phases of the two phase clock signals. As can be seen, through the N phase clock signals generated by the multi-phase generator 11, the edge detector 12 can determine between which two phases the transition edge of the data signal is located, and thus can determine two phase clock signals adjacent to each other corresponding to the transition edge of the data signal.

When the edge detector 12 determines that a transition edge exists in the data signal, the phase configurator 13 may determine a sampling clock signal matched with the data signal according to two phase-adjacent phase clock signals corresponding to the transition edge. Alternatively, the sampling clock signal may be one of N phase clock signals. In turn, the phase configurator 13 may transmit the sampling clock signal to the data sampler 14. The data sampler 14 may sample the data signal according to a sampling clock signal to obtain a first sampled signal.

It can be seen that, in the homologous timing adaptive apparatus provided in the embodiment of the present application, N phase clock signals having the same frequency but different phases from the clock signal sent by the sending-end chip are generated by the multi-phase generator 11. By means of these N phase clock signals, N phase segments with the same phase difference can be obtained. The edge detector 12 then determines whether the data signal has a transition edge based on the N phase clock signals. If the data signal has a transition edge, the transition edge of the data signal is determined to be in a fixed phase segment. The phase configurator 13 may then determine the sampling clock signal that matches the data signal based on the two phase-adjacent phase clock signals corresponding to the transition edges of the data signal. Because the sampling clock signal is determined in a phase segmentation mode, the phases of the data signal and the sampling clock signal can be matched, and therefore time sequence self-adaption is achieved. Equal-length wiring is not required to be designed in order to ensure that the phases of a data signal and a clock signal are not changed when the data signal and the clock signal reach a receiving end chip during inter-chip communication. There is no need to design unnecessary routing on the PCB for equal length routing. The wiring complexity of the PCB is simplified, the occupied area of the PCB is saved, and the cost is reduced. And the saved PCB area can be designed with other circuits, thereby improving the effective utilization rate of the PCB area.

It should be noted that, in the embodiment of the present application, specific implementation manners of the multi-phase generator 11, the edge detector 12, the phase configurator 13, and the data sampler 14 are not particularly limited. For example: the data sampler 14 may be implemented using D flip-flops.

Alternatively, as an example, the multi-phase generator 11 may include: a Phase Locked Loop (PLL) and at least N D flip-flops. The phase-locked loops are electrically connected with clock pins of at least N D triggers respectively. The data input pin of the first D trigger is used for acquiring a clock signal, the data output pin of the first D trigger is electrically connected with the data input pin of the second D trigger, and the rest D triggers are electrically connected in sequence in the same way. The data output pins of N D triggers in the N D triggers output N phase clock signals with equal difference phases respectively.

And the phase-locked loop is used for carrying out N times of frequency multiplication on the clock signal to obtain a frequency multiplication signal.

And the D trigger is used for sampling the signal on the data input pin according to the frequency doubling signal.

Specifically, the frequency of the multiplied signal is N times the frequency of the clock signal, so that there will be N rising edges in the multiplied signal during one cycle of the clock signal. Based on the turning characteristic of the D trigger, when the clock input of the D trigger is 0, keeping the output unchanged; when the clock input of the D flip-flop is changed from 0 to 1, the output is the same as the input. Therefore, the frequency multiplication signal is used as the clock input of the D flip-flop, the clock signal is used as the data input of the D flip-flop, and the phase clock signals of N equal difference phases can be obtained by adopting the D flip-flop.

Optionally, the number of D flip-flops is N +2, and the phase clock signal is output from the third D flip-flop.

By setting N + 2D flip-flops, the first D flip-flop and the second D flip-flop are used to avoid the meta-stability problem. Meta-stable refers to a state in which a flip-flop cannot reach an identifiable state within a specified period of time.

The following is a detailed description with a specific example. Suppose N is 8.

Fig. 4 is a schematic structural diagram of a multiphase generator according to an embodiment of the present disclosure. As shown in fig. 4, 10D flip-flops are denoted as D flip-flops 1 to 10, respectively. The input end of the PLL is used for acquiring a clock signal, and the PLL realizes 8 times of frequency multiplication. The PLLs are electrically connected to the clock pins of the 10D flip-flops, respectively. The data input pin of the D flip-flop 1 is used to acquire a clock signal. The data output pin of the D flip-flop 1 is electrically connected with the data input pin of the D flip-flop 2. The data output pin of the D flip-flop 2 is electrically connected with the data input pin of the D flip-flop 3. And the like are connected in sequence.

The data output pin of the D flip-flop 3 may output a phase clock signal clk0, and the phase may be 0. The data output pin of the D flip-flop 4 may output a phase clock signal clk1, which may be 45 in phase. The data output pin of the D flip-flop 5 may output a phase clock signal clk2, which may be 90 in phase. By analogy, the data output pin of the D flip-flop 10 may output the phase clock signal clk7, which may be 315 in phase.

Optionally, the edge detector 12 is specifically configured to:

and respectively sampling the data signals according to every two phase clock signals with adjacent phases in the N phase clock signals to obtain a second sampling signal and a third sampling signal.

And if the XOR operation result of the second sampling signal and the third sampling signal is 1, determining that the data signal has a jump edge.

And if the exclusive-or operation result of the second sampling signal and the third sampling signal is 0, determining that no transition edge exists in the data signal.

Specifically, fig. 5 is a schematic diagram for determining whether a data signal has a transition edge according to the embodiment of the present application. As shown in FIG. 5, CLK-P [ N-1] and CLK-P [ N ] are two phase-adjacent phase clock signals, and N is an integer greater than or equal to 1 and less than N. The data signals are sampled according to CLK-P [ n-1] and CLK-P [ n ], respectively, to obtain a second sampled signal D1 and a third sampled signal D2. Exclusive or operation is performed on D1 and D2. According to the XOR algorithm, if the result of the XOR operation is 1, D1 and D2 are indicated to have different values. If D1 is high, D2 is low, and the data signal has a falling edge. If D1 is low, D2 is high, and the data signal has a rising edge. If the XOR result is 0, it indicates that the values of D1 and D2 are the same. D1 and D2 may both be low or high, and there is no transition edge in the data signal. If the exclusive-or operation result of D1 and D2 is 0, detecting the transition edge of the data signal according to two adjacent phase clock signals in the N phase clock signals again until the data signal is determined to have the transition edge or traverse all two adjacent phase clock signals in the N phase clock signals.

Optionally, when the phase configurator 13 configures N phase clock signals for the edge detector 12, a serial processing mode may be adopted, and a parallel processing mode may also be adopted.

When the serial processing mode is adopted, the phase configurator 13 may configure the edge detector 12 with two phase-adjacent phase clock signals corresponding to one phase segment at a time until all the phase segments are traversed. The traversal order of the phase segments is not particularly limited in the embodiments of the present application. For example: if N is 8 and the phase of the clock signal is 0, the clock signal may sequentially traverse from phase 0. Assume that the phase clock signal is denoted as CLK-P [ k ], k ∈ [0,7 ]. The phase of CLK-P [0] is 0. The traversal order may be: CLK-P [0] and CLK-P [1], CLK-P [1] and CLK-P [2], …, CLK-P [6] and CLK-P [7 ].

When the parallel processing method is adopted, the number of parallel processing paths is not particularly limited. For example, also taking N as 8 as an example, the phase configurator 13 may configure two phase-adjacent phase clock signals corresponding to 8 phase segments at a time. Two phase-adjacent phase clock signals corresponding to 4 phase segments respectively can also be configured at a time until all phase segments are traversed.

Optionally, the edge detector 12 performs transition edge detection on the data signal according to the N phase clock signals configured by the phase configurator 13, and determines whether the data signal has a transition edge, which may be a serial processing manner or a parallel processing manner. When the parallel processing method is adopted, the number of parallel processing paths is not particularly limited.

Optionally, the phase configurator 13 is specifically configured to:

any one of two phase-adjacent phase clock signals is taken as a first reference clock signal.

And taking a phase clock signal which has M equal difference phases with the first reference clock signal as a sampling clock signal, wherein M is a positive integer which is more than 1 and less than N. The sampling clock signal and the first reference clock signal are located in one period of the clock signal.

The specific value of M is not particularly limited in the embodiments of the present application. Optionally, if single-edge sampling is performed on the data signal, the value of M may be one half of N. If the data signal is double-edge sampled, then M may take on a quarter of N. If N is a base number, then one-half or one-fourth of N may adopt rounding-up or rounding-down.

The following description will be given with specific examples.

For example: if N is 8, single edge sampling is used, and two phase clock signals adjacent to each other are CLK-P [1] and CLK-P [2], respectively, and the first reference clock signal is CLK-P [1], then the sampling clock signal may be CLK-P [1+4], i.e., CLK-P [5 ]. If N is 9, two edge sampling is used, two phase clock signals adjacent to each other are CLK-P [6] and CLK-P [7], respectively, one quarter of N is rounded down to 2, and the first reference clock signal is CLK-P [7], then the sampling clock signal may be CLK-P [7+2], i.e., CLK-P [1 ].

The embodiment of the application provides a self-adaptive device for homologous timing, which comprises a multi-phase generator, an edge detector, a phase configurator and a data sampler. The homologous timing sequence self-adaptive device provided by the embodiment of the application determines the sampling clock signal matched with the data signal in a phase segmentation mode, and does not need to perform equal-length wiring among chips. The wiring complexity of the PCB is simplified, the occupied area of the PCB is saved, and the cost is reduced.

Further, in the embodiment of the present application, if the data signals are multiplexed, the source timing adaptive apparatus may further include a data synchronous sampler 15. The data synchronous sampler 15 is electrically connected to the multiphase generator 11, the data sampler 14, and the phase configurator 13, respectively.

The phase configurator 13 is further configured to determine a synchronous sampling clock signal according to the sampling clock signal corresponding to each data signal.

And the data synchronous sampler 15 is configured to sample the first sampling signals corresponding to each data signal according to the synchronous sampling clock signal determined by the phase configurator 13, so as to obtain parallel sampling signals.

Specifically, when the data signals are multiple paths, after the data sampler 14 collects each path of data signals according to the corresponding collection clock signal to obtain the corresponding first sampling signal, the data synchronous sampler 15 needs to uniformly sample all the first sampling signals again according to the synchronous sampling clock signal, and the obtained parallel sampling signals are output as the final synchronous output after the sampling of the multiple paths of data signals.

It should be noted that, in the embodiment of the present application, a specific implementation manner of the circuit of the data synchronous sampler 15 is not particularly limited. For example: a D flip-flop implementation may be employed.

Optionally, the phase configurator 13 is specifically configured to:

and taking the sampling clock signal with the largest phase in all the sampling clock signals as a second reference clock signal, and taking the sampling clock signal with the smallest phase as a third reference clock signal.

And determining an equal difference phase between the phases of the second reference clock signal and a third reference clock signal in the next clock cycle, and taking the phase clock signal corresponding to the equal difference phase in the current clock cycle as a synchronous sampling clock signal.

The following is a description by specific examples.

For example: n is 8, and the phase of the clock signal is 0. The phase clock signal is denoted CLK-P [ k ], k ∈ [0,7 ]. The phase of CLK-P [0] is 0. The data signals have 4 paths, and the sampling clock signals corresponding to the 4 paths of data signals are CLK-P [1], CLK-P [3], CLK-P [4] and CLK-P [6], respectively. Of the 4 sampling clock signals, the sampling clock signal with the largest phase is CLK-P [6], and CLK-P [6] is taken as the second reference clock signal. The sampling clock signal with the smallest phase is CLK-P [1], and CLK-P [1] is taken as a third reference clock signal. There are also two equi-differential phases between CLK-P [6] and CLK-P [1] of the next clock cycle, the two equi-differential phases corresponding to the respective phase clock signals CLK-P [7] and CLK-P [0] in the current clock cycle. Either one of CLK-P [7] and CLK-P [0] may be used as the synchronous sampling clock signal. The clock cycle refers to a period of a clock signal.

Another example is: n is 8, and the phase of the clock signal is 0. The phase clock signal is denoted CLK-P [ k ], k ∈ [0,7 ]. The phase of CLK-P [0] is 0. The data signals have 4 paths, and the sampling clock signals corresponding to the 4 paths of data signals are CLK-P [4], CLK-P [5], CLK-P [6] and CLK-P [7], respectively. Of the 4 sampling clock signals, the sampling clock signal with the largest phase is CLK-P [7], and CLK-P [7] is taken as the second reference clock signal. The sampling clock signal with the smallest phase is CLK-P4, and CLK-P4 is used as the third reference clock signal. There are also four equi-differential phases between CLK-P [7] and CLK-P [4] of the next clock cycle, the four equi-differential phases corresponding to the respective phase clock signals CLK-P [0], CLK-P [1], CLK-P [2] and CLK-P [3] in the current clock cycle. Any one of CLK-P [0], CLK-P [1], CLK-P [2] and CLK-P [3] may be used as the synchronous sampling clock signal.

Optionally, if the multiple data signals are processed in parallel, the phase configurator 13 may further be configured to:

and determining sampling clock signals corresponding to each path of data signals in a preset time period.

Specifically, by setting the preset time period, the problem that the time for determining the synchronous sampling clock signal is increased because a certain data signal cannot determine the sampling clock signal can be avoided. If the sampling clock signal cannot be determined by a certain path of data signal, it is indicated that the path of data signal may be abnormal, and therefore, the influence of the path of data signal on the synchronous sampling clock signal does not need to be considered.

The specific value of the preset time period is not particularly limited in the embodiments of the present application.

The embodiment of the application provides a homologous timing sequence self-adaptive device, and particularly provides the homologous timing sequence self-adaptive device when data signals are in multiple paths. The time sequence self-adaption of the multi-channel data signals is realized, the wiring complexity of the PCB is simplified, the occupied area of the PCB is saved, and the cost is reduced.

Fig. 6 is a flowchart of a method for self-adapting a source timing according to an embodiment of the present application. As shown in fig. 6, an implementation subject of the method for self-adaptive timing of the same source according to the embodiment of the present application may be the self-adaptive timing apparatus of the same source according to any one of the apparatus embodiments shown in fig. 2 to 5. As shown in fig. 6, the method for self-adapting a source timing sequence provided in the embodiment of the present application may include:

step 101, acquiring a data signal and a clock signal.

And 102, generating phase clock signals with N equal difference phases according to the clock signals.

Wherein, the frequency of the phase clock signal is the same as the frequency of the clock signal, and N may be a positive integer greater than 4.

Optionally, as a specific implementation manner, the step 102 of generating phase clock signals with N equal-difference phases according to the clock signal may include:

and carrying out N times of frequency multiplication on the clock signal by adopting a phase-locked loop to obtain a frequency multiplication signal.

And sampling the clock signal by adopting a D trigger according to the frequency multiplication signal to obtain phase clock signals of N equal difference phases.

The number of the D triggers is at least N, wherein the data output pins of the N D triggers respectively output a phase clock signal.

And 103, carrying out jump edge detection on the data signal according to the N phase clock signals, and judging whether the data signal has jump edges.

Optionally, as a specific implementation manner, step 103, performing transition edge detection on the data signal according to the N phase clock signals, and determining whether the data signal has a transition edge, may include:

And step 104, if the data signal has a jump edge, determining a sampling clock signal according to two phase clock signals with adjacent phases corresponding to the jump edge.

Optionally, as a specific implementation manner, the step 104 of determining a sampling clock signal according to two phase-adjacent phase clock signals corresponding to the transition edge may include:

A phase clock signal which is different from the first reference clock signal by M equal difference phases is used as a sampling clock signal.

Wherein M may be a positive integer greater than 1 and less than N. The sampling clock signal and the first reference clock signal are located in one period of the clock signal.

And 105, sampling the data signal according to the sampling clock signal to obtain a first sampling signal.

The method for adapting to a homologous timing sequence provided in the embodiment of the present application is applied to the apparatus for adapting to a homologous timing sequence provided in the apparatus embodiments shown in fig. 2 to 5, and the technical principle and the technical effect are similar, and are not described herein again.

Fig. 7 is a flowchart of another implementation manner of the method for self-adapting a source timing according to the embodiment of the present application, which is based on the foregoing method embodiment and provides the method for self-adapting a source timing when data signals are multiplexed. As shown in fig. 7, in the embodiment of the present application, the method for source timing adaptation may further include:

step 201, determining a synchronous sampling clock signal according to the sampling clock signal corresponding to each data signal.

Step 202, sampling the first sampling signals respectively corresponding to each path of data signals according to the synchronous sampling clock signal, and obtaining parallel sampling signals.

Optionally, as a specific implementation manner, in step 201, determining a synchronous sampling clock signal according to a sampling clock signal corresponding to each data signal respectively, where the determining may include:

Optionally, if the multiple data signals are processed in parallel, before determining the synchronous sampling clock signal according to the sampling clock signal corresponding to each data signal in step 201, the method may further include:

Fig. 8 is a schematic structural diagram of a chip provided in an embodiment of the present application. As shown in fig. 8, the chip provided in the embodiment of the present application may include: the apparatus 21 for source timing adaptation according to any of the embodiments of the present application.

The chip provided in the embodiment of the present application is used as a receiving end chip in inter-chip communication, and the homologous timing adaptive device 21 included in the chip may be the homologous timing adaptive device provided in the device embodiments shown in fig. 2 to 5, and is used to execute the homologous timing adaptive method provided in the method embodiments shown in fig. 6 to 7, and the technical principle and the technical effect are similar, and are not described again here.

Claims

1. A homologous timing adaptation apparatus, comprising: the device comprises a multi-phase generator, an edge detector, a phase configurator and a data sampler;

the multi-phase generator is respectively electrically connected with the edge detector, the phase configurator and the data sampler, and the phase configurator is respectively electrically connected with the edge detector and the data sampler;

the multi-phase generator is used for acquiring a clock signal; generating phase clock signals of N equal difference phases according to the clock signals; the frequency of the phase clock signal is the same as that of the clock signal, and N is a positive integer greater than 4;

the phase configurator is used for configuring the N phase clock signals for the edge detector;

the edge detector is used for acquiring a data signal, detecting a transition edge of the data signal according to the N phase clock signals configured by the phase configurator, and judging whether the data signal has the transition edge;

the phase configurator is further configured to determine a sampling clock signal according to two phase clock signals with adjacent phases corresponding to a transition edge when the edge detector determines that the data signal has the transition edge;

the data sampler is used for acquiring the data signal; and sampling the data signal according to the sampling clock signal determined by the phase configurator to obtain a first sampling signal.

2. The apparatus of claim 1, wherein the multi-phase generator comprises: a phase-locked loop and at least N D flip-flops; the phase-locked loop is electrically connected with the clock pins of the at least N D triggers respectively; a data input pin of the first D trigger is used for acquiring the clock signal, a data output pin of the first D trigger is electrically connected with a data input pin of the second D trigger, and the rest D triggers are electrically connected in sequence by parity of reasoning; the data output pins of N D flip-flops in the at least N D flip-flops respectively output the phase clock signals of the N equal difference phases;

the phase-locked loop is used for carrying out N times of frequency multiplication on the clock signal to obtain a frequency multiplication signal;

and the D trigger is used for sampling the signal on the data input pin according to the frequency multiplication signal.

3. The apparatus of claim 2, wherein the number of D flip-flops is N +2, and the phase clock signal is output from a third D flip-flop.

4. The apparatus of claim 1, wherein the edge detector is specifically configured to:

sampling the data signal according to every two phase clock signals with adjacent phases in the N phase clock signals to obtain a second sampling signal and a third sampling signal;

if the result of the exclusive-or operation of the second sampling signal and the third sampling signal is 1, determining that a transition edge exists in the data signal;

and if the exclusive-or operation result of the second sampling signal and the third sampling signal is 0, determining that no jump edge exists in the data signal.

5. The apparatus of claim 1, wherein the phase configurator is specifically configured to:

taking any one of the two phase-adjacent phase clock signals as a first reference clock signal;

taking a phase clock signal which has a difference of M equal-difference phases from the first reference clock signal as the sampling clock signal, wherein M is a positive integer greater than 1 and less than N; the sampling clock signal and the first reference clock signal are located in one period of a clock signal.

6. The apparatus of any one of claims 1 to 5, wherein if the data signal is multiplexed, the apparatus further comprises a data synchronous sampler; the data synchronous sampler is electrically connected with the multiphase generator, the data sampler and the phase configurator respectively;

the phase configurator is further used for determining synchronous sampling clock signals according to the sampling clock signals respectively corresponding to each path of data signals;

the data synchronous sampler is used for sampling the first sampling signals respectively corresponding to each path of data signals according to the synchronous sampling clock signals determined by the phase configurator to obtain parallel sampling signals.

7. The apparatus of claim 6, wherein the phase configurator is specifically configured to:

taking the sampling clock signal with the largest phase in all the sampling clock signals as a second reference clock signal, and taking the sampling clock signal with the smallest phase as a third reference clock signal;

and determining an equal difference phase between the phases of the second reference clock signal and a third reference clock signal in the next clock cycle, and taking a phase clock signal corresponding to the equal difference phase in the current clock cycle as the synchronous sampling clock signal.

8. The apparatus of claim 6, wherein if the plurality of data signals are processed in parallel, the phase configurator is further configured to:

9. A method for homologous timing adaptation, applied to the apparatus of any one of claims 1-8, the method comprising:

acquiring a data signal and a clock signal;

generating phase clock signals of N equal difference phases according to the clock signals; the frequency of the phase clock signal is the same as that of the clock signal, and N is a positive integer greater than 4;

carrying out jump edge detection on the data signals according to the N phase clock signals, and judging whether the data signals have jump edges;

if the data signal has a jump edge, determining a sampling clock signal according to two phase clock signals with adjacent phases corresponding to the jump edge;

and sampling the data signal according to the sampling clock signal to obtain a first sampling signal.

10. The method of claim 9, wherein generating N equi-differential phase clock signals from the clock signal comprises:

carrying out N times of frequency multiplication on the clock signal by adopting a phase-locked loop to obtain a frequency multiplication signal;

and sampling the clock signal by adopting a D trigger according to the frequency multiplication signal to obtain the phase clock signals of the N equal difference phases.

11. The method of claim 9, wherein the detecting transition edges of the data signal according to the N phase clock signals and determining whether the data signal has transition edges comprises:

12. The method of claim 9, wherein determining the sampling clock signal according to two phase-adjacent phase clock signals corresponding to the transition edges comprises:

13. The method of any of claims 9 to 12, wherein if the data signal is multiplexed, the method further comprises:

determining synchronous sampling clock signals according to sampling clock signals corresponding to each path of data signals;

and sampling the first sampling signals respectively corresponding to each path of data signals according to the synchronous sampling clock signals to obtain parallel sampling signals.

14. The method of claim 13, wherein determining the synchronous sampling clock signal according to the sampling clock signal corresponding to each data signal comprises:

15. The method of claim 13, wherein before determining the synchronous sampling clock signal according to the sampling clock signal corresponding to each data signal if multiple data signals are processed in parallel, further comprising:

16. A chip, comprising: the apparatus of any of claims 1 to 8.