CN116545438A - Frequency divider and multi-modulus frequency divider - Google Patents

Frequency divider and multi-modulus frequency divider Download PDF

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Publication number
CN116545438A
CN116545438A CN202310805780.6A CN202310805780A CN116545438A CN 116545438 A CN116545438 A CN 116545438A CN 202310805780 A CN202310805780 A CN 202310805780A CN 116545438 A CN116545438 A CN 116545438A
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mos tube
mos
electrode
twenty
frequency
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CN202310805780.6A
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CN116545438B (en
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雷永庆
黄寿
李泽
黎兴荣
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Mestar Microelectronics Shenzhen Co ltd
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Mestar Microelectronics Shenzhen Co ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/197—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks

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  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Logic Circuits (AREA)

Abstract

The application discloses a frequency divider and a multi-mode frequency divider, wherein the frequency divider comprises a 2/3 configurable frequency dividing module, and the 2/3 configurable frequency dividing module comprises a clock input end, a control end, a locking end, a mode selection end, a first output end and a second output end; the clock input end is used for accessing a clock signal to be divided; the control end and the mode selection end are used for jointly limiting the frequency division mode of the 2/3 configurable frequency division module; the first output end and the second output end are used for outputting signals after frequency division; the locking terminal is used for enabling or shutting off the first output terminal. The power consumption of the corresponding multi-mode frequency divider can be reduced.

Description

Frequency divider and multi-modulus frequency divider
Technical Field
The application relates to the technical field of circuits, in particular to a frequency divider and a multi-mode frequency divider.
Background
A frequency Divider or a Multi-Modulus Divider (MMD) is one of important constituent blocks in a fractional phase-locked loop frequency synthesizer, which can convert a high frequency signal into a low frequency signal at a certain ratio. In phase locked loop frequency synthesizer systems, the frequency of the Voltage Controlled Oscillator (VCO) is high, typically at GHz and above, requiring the divider to operate properly at the higher input frequency. The power consumption is one of the key indexes of the frequency divider, and the low power consumption design of the frequency divider is one of the industrial problems of the existing frequency divider because the frequency divider needs to cover the highest frequency point of the circuit VCO to work normally and the circuit power consumption is positively related to the working frequency of the circuit VCO.
Disclosure of Invention
In view of this, the present application provides a frequency divider with low power consumption characteristics.
The frequency divider comprises a 2/3 configurable frequency dividing module, wherein the 2/3 configurable frequency dividing module comprises a clock input end, a control end, a locking end, a mode selection end, a first output end and a second output end; the clock input end is used for accessing a clock signal to be divided; the control end and the mode selection end are used for jointly limiting the frequency division mode of the 2/3 configurable frequency division module; the first output end and the second output end are used for outputting signals after frequency division; the locking terminal is used for enabling or shutting off the first output terminal.
Optionally, the 2/3 configurable frequency division module further includes a reset terminal, where the reset terminal is configured to access a reset signal to reset the 2/3 configurable frequency division module.
Optionally, the frequency divider comprises a frequency dividing unit and an auxiliary unit; the frequency dividing unit is used for carrying out frequency division or frequency halving on the clock signal; the auxiliary unit is used for providing a load for the frequency dividing unit.
Optionally, the auxiliary unit includes a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor, a sixth MOS transistor, a seventh MOS transistor, and an eighth MOS transistor; the grid electrode of the first MOS tube is used as the clock input end, the source electrode of the first MOS tube is connected with a set power supply, and the drain electrode of the first MOS tube is respectively connected with the drain electrode of the second MOS tube, the grid electrode of the fourth MOS tube, the grid electrode of the sixth MOS tube and the frequency dividing unit; the grid electrode of the second MOS tube is connected with the frequency dividing unit, and the source electrode of the second MOS tube is connected with the drain electrode of the third MOS tube; the grid electrode of the third MOS tube is connected with the clock input end, and the source electrode of the third MOS tube is grounded; the source electrode of the fourth MOS tube is connected with the set power supply, and the drain electrode of the fourth MOS tube is respectively connected with the drain electrode of the fifth MOS tube, the drain electrode of the seventh MOS tube and the drain electrode of the eighth MOS tube and serves as the second output end; the grid electrode of the fifth MOS tube is connected with the clock input end, and the source electrode of the fifth MOS tube is connected with the drain electrode of the sixth MOS tube; the source electrode of the sixth MOS tube is grounded; the grid electrode of the seventh MOS tube is used for being connected with a reset signal, and the source electrode of the seventh MOS tube is connected with the set power supply; and the grid electrode of the eighth MOS tube is used as the mode selection end, and the source electrode is grounded.
Optionally, the frequency dividing unit includes a ninth MOS transistor, a tenth MOS transistor, an eleventh MOS transistor, a twelfth MOS transistor, a thirteenth MOS transistor, a fourteenth MOS transistor, a fifteenth MOS transistor, a sixteenth MOS transistor, a seventeenth MOS transistor, an eighteenth MOS transistor, a nineteenth MOS transistor, a twentieth MOS transistor, a twenty-first MOS transistor, a twenty-second MOS transistor, a twenty-third MOS transistor, a twenty-fourth MOS transistor, and a twenty-fifth MOS transistor; the grid electrode of the ninth MOS tube is respectively connected with the drain electrode of the twenty-second MOS tube, the grid electrode of the eleventh MOS tube, the drain electrode of the seventeenth MOS tube, the drain electrode of the eighteenth MOS tube, the drain electrode of the twenty-second MOS tube, the grid electrode of the twenty-third MOS tube and the grid electrode of the twenty-fifth MOS tube, the source electrode is connected with the set power supply, and the drain electrode is connected with the source electrode of the tenth MOS tube; the grid electrode of the tenth MOS tube is connected with the clock input end, and the drain electrode of the tenth MOS tube is respectively connected with the grid electrode of the second MOS tube, the grid electrode of the fourteenth MOS tube and the drain electrode of the eleventh MOS tube; the source electrode of the eleventh MOS tube is grounded; the grid electrode of the twelfth MOS tube is connected with the clock input end, the source electrode of the twelfth MOS tube is connected with a set power supply, and the drain electrode of the twelfth MOS tube is respectively connected with the source electrode of the thirteenth MOS tube and the source electrode of the sixteenth MOS tube; the grid electrode of the thirteenth MOS tube is connected with the second output end, and the drain electrode of the thirteenth MOS tube is respectively connected with the drain electrode of the fourteenth MOS tube, the drain electrode of the sixteenth MOS tube and the grid electrode of the eighteenth MOS tube; the source electrode of the fourteenth MOS tube is connected with the drain electrode of the fifteenth MOS tube; the grid electrode of the fifteenth MOS tube is connected with the clock input end, and the source electrode of the fifteenth MOS tube is grounded; the grid electrode of the sixteenth MOS tube is used as the control end; the grid electrode of the seventeenth MOS tube is respectively connected with the grid electrode of the nineteenth MOS tube and the drain electrode of the twenty first MOS tube, and the source electrode is connected with the set power supply; the source electrode of the eighteenth MOS tube is connected with the drain electrode of the nineteenth MOS tube; the source electrode of the nineteenth MOS tube is grounded; the grid electrode of the twentieth MOS tube is connected with the drain electrode of the first MOS tube, and the source electrode is connected with the set power supply; the grid electrode of the twenty-first MOS tube is used as the locking end, and the source electrode is grounded; the grid electrode of the twenty-second MOS tube is used for being connected with the reset signal, and the source electrode of the twenty-second MOS tube is connected with the set power supply; the source electrode of the twenty-third MOS tube is connected with the set power supply, and the drain electrode of the twenty-fourth MOS tube is connected with the source electrode of the twenty-fourth MOS tube; the grid electrode of the twenty-four MOS tube is connected with the locking end, and the drain electrode of the twenty-five MOS tube is connected with the drain electrode of the twenty-five MOS tube and used as the first output end; and the source electrode of the twenty-fifth MOS tube is grounded.
Optionally, the locking terminal includes a sub-enable terminal and a sub-state locking terminal; the grid electrode of the twenty-four MOS tube is used as the sub-enabling end, and the grid electrode of the twenty-four MOS tube is used as the sub-state locking end.
Optionally, the sub-enabling terminal enables the first output terminal when the sub-enabling terminal is connected with a low level, and turns off the first output terminal when the sub-enabling terminal is connected with a high level; when the sub-state locking end is connected with a high level, the 2/3 configurable frequency dividing module is locked, and the second output end outputs a fixed value.
The application also provides a multi-mode frequency divider, which comprises N frequency dividers of any one of the above and N-1 inverters; the first output end of the ith frequency divider is connected with the clock input end of the (i+1) th frequency divider, the second output end of the (i+1) th frequency divider is connected with the mode selection end of the (i) th frequency divider through the (i) th inverter, and the locking end of the (i+1) th frequency divider is connected with the regulating end of the (i) th inverter; wherein i and N are integers, and i is more than or equal to 1 and less than or equal to N.
Optionally, the multi-modulus divider is configured to determine an input value of a control terminal of each divider based on a desired division ratio and to determine an input value of a lock terminal of each divider based on the input value of the control terminal of each divider.
Optionally, the locking terminal includes a sub-enable terminal and a sub-state locking terminal, and the sub-state locking terminal of the (i+1) th frequency divider is connected to the sub-enable terminal of the (i) th frequency divider and the adjusting terminal of the (i) th inverter, respectively.
In the frequency divider and the multi-mode frequency divider provided by the application, the control end and the mode selection end are used for jointly limiting the frequency dividing mode of the 2/3 configurable frequency dividing module, so that the 2/3 configurable frequency dividing module can realize two frequency dividing or three frequency dividing under the configuration of the ports, the locking end can enable or switch off the first output end, in the process of cascading a plurality of frequency dividers to form the multi-mode frequency divider, the channel of the first output end can be controlled by a signal accessed by the locking end, and on the basis that the formed multi-mode frequency divider has the function of realizing any frequency dividing ratio frequency dividing on a clock signal, the flexibility in the configuration process of each frequency divider can be improved, and the purpose of reducing the power consumption of the corresponding multi-mode frequency divider can be achieved by configuring the locking end to switch off the ports or the frequency dividing function of at least part of the frequency divider.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly introduced below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a frequency divider according to an embodiment of the present application;
FIG. 2 is a schematic circuit diagram of a frequency divider according to an embodiment of the present application;
FIG. 3 is a schematic diagram of a frequency divider according to another embodiment of the present application;
fig. 4 is a schematic circuit diagram of a frequency divider according to another embodiment of the present application;
FIG. 5 is a schematic diagram of a multi-modulus divider according to one embodiment of the present application;
fig. 6 is a schematic diagram of a multi-modulus divider according to another embodiment of the present application.
Detailed Description
The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all, of the embodiments of the present application. All other embodiments, which can be made by those skilled in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application. The various embodiments described below and their technical features can be combined with each other without conflict.
The application provides a frequency divider, referring to fig. 1, the frequency divider includes a 2/3 configurable frequency dividing module 2, wherein the 2/3 configurable frequency dividing module 2 includes a clock input terminal Fi, a control terminal S, a locking terminal E, a mode selecting terminal mod_in, a first output terminal Fo and a second output terminal mod_out.
IN this embodiment, the clock input Fi is used to access the clock signal clk_in to be divided. The control terminal S and the mode selection terminal mod_in are configured to jointly define a frequency division mode of the 2/3 configurable frequency division module 2, so as to configure a suitable frequency division ratio to divide the clock signal clk_in to be divided. For example, when a certain signal is accessed by the mode selection terminal mod_in, the 2/3 configurable frequency dividing module 2 divides the clock signal clk_in by two, and when another signal is accessed by the mode selection terminal mod_in, the 2/3 configurable frequency dividing module 2 divides the clock signal clk_in by two or three, etc. according to the type of the signal accessed by the control terminal S. Specifically, when the mode selection terminal mod_in is connected to a high level (i.e., mod_in is set 1), the 2/3 frequency divider module 2 divides the clock signal clk_in by two. When the mode selection terminal mod_in is connected to a low level (i.e., mod_in is set to 0), if the control terminal S is connected to a high level (i.e., S is set to 1), the 2/3 configurable frequency division module 2 divides the clock signal clk_in by three; if the control terminal S is connected to a low level (i.e. S is set to 0), the 2/3 frequency division module 2 can divide the clock signal by two.
In this embodiment, the first output terminal Fo and the second output terminal mod_out are used to output the divided signals. Specifically, for a single independent frequency divider, the first output Fo is used to output a signal of the clock signal clk_in divided by the frequency divider according to the configured division ratio. The signal output from the second output terminal mod_out may have the same frequency as the signal output from the first output terminal Fo. If a plurality of frequency dividers are cascaded, the signal output by the second output terminal mod_out may be related to the cascaded frequency dividers, which will be described in detail later.
In this embodiment, the lock terminal E is used to enable or disable the first output terminal Fo. Specifically, when the lock terminal E is at the low level (i.e., E is set to 0), the first output terminal Fo is enabled by the lock terminal E and can output the divided signal; when the lock terminal E is at the access high level (i.e., E is set 1), the first output terminal Fo is turned off by the lock terminal E. It can be understood that the locking terminal E can also be used to adjust the state of the 2/3 configurable frequency dividing module 2, specifically, when the locking terminal E is connected to a low level (i.e. E is set to 0), the 2/3 configurable frequency dividing module 2 can work normally to participate in frequency division; when the locking terminal E is connected to a high level (i.e. E is set to 1), the state of the 2/3 configurable frequency dividing module 2 is locked, and the state is locked to be a determined state, and the output signal of the second output terminal mod_out is a fixed value, for example, 0, and cannot participate in frequency division. In this case, the 2/3 configurable frequency dividing module 2 is locked in a certain state, and if the 2/3 configurable frequency dividing module 2 needs to participate in frequency division afterwards, the access signal of the locking end E can be adjusted to change the state of the 2/3 configurable frequency dividing module 2, and the 2/3 configurable frequency dividing module 2 can accurately divide according to the frequency division ratio when the 2/3 configurable frequency dividing module 2 participates in frequency division for the first time afterwards.
In some embodiments, the 2/3 configurable frequency division module 2 may further include a reset terminal RN. The reset terminal RN may be used to access a reset signal to reset the 2/3 configurable frequency division module 2. Specifically, if the reset signal of the reset terminal RN is at a low level (i.e., RN is set to 0), the circuit of the 2/3 configurable frequency division module 2 is in a reset mode, each node state is fixed, and if the reset signal of the reset terminal RN is at a high level (i.e., RN is set to 1), the circuit of the 2/3 configurable frequency division module 2 can work normally. In this case, if the 2/3 configurable frequency division module 2 does not operate, the RN may be set to 0, and the circuit is in the reset mode, and each node is in a fixed state, so that the circuit has low power consumption, for example, only nA-level leakage current, so as to reduce power consumption.
IN the above-mentioned frequency divider, the control terminal S and the mode selection terminal mod_in are used to jointly define the frequency dividing mode of the 2/3 configurable frequency dividing module 2, so that the 2/3 configurable frequency dividing module 2 can select an appropriate frequency dividing ratio, such as a divide-by-two frequency division or a divide-by-three frequency division, under the configuration of the above-mentioned ports. The locking end E can enable or shut off the first output end Fo, so that IN the process of cascading a plurality of frequency dividers to form the multi-mode frequency divider, the channel of the first output end Fo can be controlled by a signal accessed by the locking end E, on the basis that the formed multi-mode frequency divider has the function of realizing arbitrary frequency division ratio frequency division on the clock signal CLK_IN, the flexibility IN the configuration process of each frequency divider can be improved, and the purpose of reducing the power consumption of the corresponding multi-mode frequency divider can be achieved by configuring the locking end E to shut off the first output end or the frequency division function of at least part of the frequency dividers.
In some embodiments, the circuit corresponding to the 2/3 configurable frequency division module 2 may use a TSPC structure. Referring to fig. 2, the 2/3 configurable frequency dividing module 2 includes a frequency dividing unit 21 and an auxiliary unit 22. The frequency dividing unit 21 is connected to the auxiliary unit 22. The frequency dividing unit 21 is configured to divide the clock signal clk_in by two or three. The auxiliary unit 22 is used to provide a load for the frequency dividing unit 21. The 2/3 configurable frequency division module 2 provided by the application can realize ultrahigh frequency input and has the characteristic of low power consumption. For example, the circuit of the 2/3 configurable frequency division module 2 of the present application can be used to operate at a process size of 0.18um, and the 2/3 configurable frequency division module 2 can operate at a current as low as 600uA when the 2.4G input frequency and the supply voltage are 1.5V.
In some embodiments, referring to fig. 2, the auxiliary unit 22 may include a plurality of MOS transistors, which are a first MOS transistor M1, a second MOS transistor M2, a third MOS transistor M3, a fourth MOS transistor M4, a fifth MOS transistor M5, a sixth MOS transistor M6, a seventh MOS transistor M7, and an eighth MOS transistor M8, respectively.
The gate of the first MOS transistor M1 is used as a clock input terminal Fi, the source is connected to the set power supply VDD, and the drain is respectively connected to the drain of the second MOS transistor M2, the gate of the fourth MOS transistor M4, the gate of the sixth MOS transistor M6, and the frequency dividing unit 21 (e.g., the gate of the twentieth MOS transistor M20); the gate of the second MOS tube M2 is connected with the frequency dividing unit 21 (such as the drain of the tenth MOS tube M10), and the source is connected with the drain of the third MOS tube M3; the grid electrode of the third MOS tube M3 is connected with the clock input end Fi, and the source electrode is grounded GND; the source electrode of the fourth MOS tube M4 is connected with a set power supply VDD, and the drain electrode is respectively connected with the drain electrode of the fifth MOS tube M5, the drain electrode of the seventh MOS tube M7 and the drain electrode of the eighth MOS tube M8 and is used as a second output end MOD_OUT; the grid electrode of the fifth MOS tube M5 is connected with the clock input end Fi, and the source electrode of the fifth MOS tube M6 is connected with the drain electrode; the source electrode of the sixth MOS tube M6 is grounded to GND; the grid electrode of the seventh MOS tube M7 is used as a reset end RN for accessing a reset signal, and the source electrode is connected with a set power supply VDD; the gate of the eighth MOS transistor M8 is used as the mode selection terminal MOD_IN, and the source is grounded GND. In this embodiment, the power supply VDD is set to power the 2/3 configurable frequency division module 2. The set power supply VDD may refer to a power supply circuit or device that supplies power to the 2/3 configurable frequency division module 2.
Optionally, referring to fig. 2, each of the first to eighth MOS transistors M1 to M8 may further include a substrate, where the substrate may be connected to the power supply terminal VDD or the ground terminal GND according to a type of the corresponding MOS transistor, and the substrate may also be connected to another object (such as a source of the MOS transistor) or suspended. In this embodiment, the first MOS transistor M1, the fourth MOS transistor M4, and the seventh MOS transistor M7 in the first MOS transistor M1 to the eighth MOS transistor M8 may be PMOS transistors; the other MOS transistors may be NMOS transistors.
In some embodiments, referring to fig. 2, the frequency dividing unit 21 may include a plurality of MOS transistors, which are a ninth MOS transistor M9, a tenth MOS transistor M10, an eleventh MOS transistor M11, a twelfth MOS transistor M12, a thirteenth MOS transistor M13, a fourteenth MOS transistor M14, a fifteenth MOS transistor M15, a sixteenth MOS transistor M16, a seventeenth MOS transistor M17, an eighteenth MOS transistor M18, a nineteenth MOS transistor M19, a twentieth MOS transistor M20, a twenty-first MOS transistor M21, a twenty-second MOS transistor M22, a twenty-third MOS transistor M23, a twenty-fourth MOS transistor M24, and a twenty-fifth MOS transistor M25, respectively.
The grid electrode of the ninth MOS tube M9 is respectively connected with the drain electrode of the twenty-second MOS tube M22, the grid electrode of the eleventh MOS tube M11, the drain electrode of the seventeenth MOS tube M17, the drain electrode of the eighteenth MOS tube M18, the drain electrode of the twentieth MOS tube M20, the grid electrode of the twenty-third MOS tube M23 and the grid electrode of the twenty-fifth MOS tube M25, the source electrode is connected with a set power supply VDD, and the drain electrode is connected with the source electrode of the tenth MOS tube M10; the gate of the tenth MOS transistor M10 is connected with the clock input end Fi, and the drain is respectively connected with the auxiliary unit 22 (such as the gate of the second MOS transistor M2), the gate of the fourteenth MOS transistor M14 and the drain of the eleventh MOS transistor M11; the source electrode of the eleventh MOS tube M11 is grounded to GND; the grid electrode of the twelfth MOS tube M12 is connected with the clock input end Fi, the source electrode is connected with the set power supply VDD, and the drain electrode is respectively connected with the source electrode of the thirteenth MOS tube M13 and the source electrode of the sixteenth MOS tube M16; the grid electrode of the thirteenth MOS tube M13 is connected with the second output end MOD_OUT, and the drain electrode is respectively connected with the drain electrode of the fourteenth MOS tube M14, the drain electrode of the sixteenth MOS tube M16 and the grid electrode of the eighteenth MOS tube M18; the source electrode of the fourteenth MOS tube M14 is connected with the drain electrode of the fifteenth MOS tube M15; the grid electrode of the fifteenth MOS tube M15 is connected with the clock input end Fi, and the source electrode is grounded GND; the grid electrode of the sixteenth MOS tube M16 is used as a control end S; the grid electrode of the seventeenth MOS tube M17 is respectively connected with the grid electrode of the nineteenth MOS tube M19 and the drain electrode of the twenty first MOS tube M21, and the source electrode is connected with a set power supply VDD; the source electrode of the eighteenth MOS tube M18 is connected with the drain electrode of the nineteenth MOS tube M19; the source electrode of the nineteenth MOS transistor M19 is grounded to GND; the gate of the twentieth MOS transistor M20 is connected to the auxiliary unit 22 (e.g., the drain of the first MOS transistor M1), and the source is connected to the set power supply VDD; the grid electrode of the twenty-first MOS tube M21 is used as a locking end E, and the source electrode is grounded GND; the grid electrode of the twenty-second MOS tube M22 is connected with the reset end RN for accessing a reset signal, and the source electrode is connected with a set power supply VDD; the source electrode of the twenty-third MOS tube M23 is connected with a set power supply VDD, and the drain electrode is connected with the source electrode of the twenty-fourth MOS tube M24; the grid electrode of the twenty-fourth MOS tube M24 is connected with the locking end, and the drain electrode of the twenty-fifth MOS tube M25 is connected with the drain electrode and serves as a first output end Fo; the source of the twenty-fifth MOS transistor M25 is grounded to GND.
Optionally, each MOS transistor, such as the ninth MOS transistor M9 to the twenty-fifth MOS transistor M25, may further include a substrate, where the substrate may be connected to the power supply terminal VDD or the ground terminal according to a type of the corresponding MOS transistor, and the substrate may also be connected to another object (such as a source of the MOS transistor) or suspended. Optionally, a ninth MOS transistor M9, a tenth MOS transistor M10, a twelfth MOS transistor M12, a thirteenth MOS transistor M13, a sixteenth MOS transistor M16, a seventeenth MOS transistor M17, a twentieth MOS transistor M20, a twenty-second MOS transistor M22, a twenty-third MOS transistor M23, and a twenty-fourth MOS transistor M24 in the ninth MOS transistor M9 to the twenty-fifth MOS transistor M25 may be PMOS transistors, and other MOS transistors may be NMOS transistors.
In some embodiments, referring to fig. 3, the lock terminal E may include a sub-enable terminal E1 and a sub-state lock terminal E2. As shown in fig. 4, the gate of the twenty-fourth MOS transistor M24 is used as the sub-enable end E1, and the gate of the twenty-first MOS transistor M21 is used as the sub-state locking end E2. The first output terminal Fo can be enabled or turned off by the sub-enable terminal E1, and the entire 2/3 configurable frequency dividing module 2 is locked by the sub-state locking terminal E2, which contributes to further reducing the power consumption of the corresponding frequency divider.
Optionally, the sub-enable terminal E1 enables the first output terminal Fo when the low level (i.e. E1 is set to 0) is accessed, and turns off the first output terminal Fo when the high level (i.e. E1 is set to 1) is accessed.
Optionally, when the sub-state locking terminal E2 is connected to a low level (i.e., E2 is set to 0), the 2/3 configurable frequency dividing module 2 can work normally to participate in frequency division; when the sub-state locking terminal E2 is connected to a high level (i.e., E2 is set to 1), the state of the 2/3 configurable frequency dividing module 2 is locked, and the state is locked to be a certain state, and the output signal of the second output terminal mod_out is a fixed value, for example, 0, and cannot participate in frequency division. In this case, the 2/3 configurable frequency dividing module 2 is locked to a certain state, and if the 2/3 configurable frequency dividing module 2 needs to participate in frequency division afterwards, the access signal of the sub-state locking terminal E2 can be adjusted to change the state of the 2/3 configurable frequency dividing module 2, and the 2/3 configurable frequency dividing module 2 can accurately divide according to the frequency dividing ratio when the 2/3 configurable frequency dividing module 2 participates in frequency division for the first time afterwards.
The application also provides a multi-mode frequency divider, which comprises N frequency dividers according to any embodiment and N-1 inverters, wherein the N frequency dividers are cascaded, and an inverter, such as the (i+1) th frequency divider 2, is arranged between two adjacent frequency dividers i (or i+1st stage frequency divider 2) i ) Second output terminal mod_out of (a) i The ith frequency divider 2 is connected through an inverter i-1 (or i-th frequency divider 2) i-1 ) Mode selection terminal mod_in of (a) i-1 Wherein i and N are integers, and i is more than or equal to 1 and less than or equal to N.
Specifically, referring to fig. 1 and 5, in the multi-modulus divider, the i-th frequency divider 2 i-1 Is connected to the first output terminal Fo of (a) i-1 Connected to the (i+1) th frequency divider 2 i Clock input Fi of (a) i To divide the ith frequency divider 2 i-1 A first output terminal Fo i-1 Output signal F i-1 Input of the (i+1) th frequency divider 2 i Clock input Fi of (a) i The method comprises the steps of carrying out a first treatment on the surface of the I+1th frequency divider 2 i Second output terminal mod_out of (a) i The ith frequency divider 2 is connected through the ith inverter i-1 Mode selection terminal mod_in of (a) i-1 I+1th frequency divider 2 i Second output terminal MOD of (2)_OUT i An input terminal connected to the ith inverter, an ith frequency divider 2 i-1 Mode selection terminal mod_in of (a) i-1 The output end of the ith inverter is connected; in this case, the (i+1) th frequency divider 2 i Second output terminal mod_out of (a) i The output signal is processed by the ith inverter and then is input into the ith frequency divider 2 i-1 Mode selection terminal mod_in of (a) i-1 . Wherein the (i+1) th frequency divider 2 i Is locked at end E of (2) i And the regulating end of the ith inverter is connected. In this embodiment, the inverter may be provided with a regulating terminal for controlling the operating state of the inverter. In this case, the operation state of the ith inverter may be equal to that of the (i+1) th frequency divider 2 i Is locked at end E of (2) i Is related to the input of (a). Specifically, when the regulation terminal is connected to a low level (i.e. regulation terminal is set to 0), the inverter normally operates to divide the (i+1) th frequency divider 2 i Second output terminal mod_out of (a) i The output is inverted and input to the ith frequency divider 2 i-1 Mode selection terminal mod_in of (a) i-1 . When the regulating terminal is connected to high level (i.e. regulating terminal 1), the inverter will not be effective, i-th frequency divider 2 i-1 Mode selection terminal mod_in of (a) i-1 Accessing the (i+1) th frequency divider 2 i Second output terminal mod_out of (a) i The output signal, at this time, if the (i+1) th frequency divider 2 i Second output terminal mod_out of (a) i The output signal is 0, the i-th frequency divider 2 i-1 Mode selection terminal mod_in of (a) i-1 The signal of the access is 0.
In the present embodiment, the 1 st frequency divider 2 of the multi-modulus frequency dividers 0 (i.e. first stage divider 2 0 ) Can be used as an input port of a multi-modulus divider for accessing the clock signal CLK IN to be divided. 1 st frequency divider 2 0 Second output terminal mod_out of (a) 0 The output port of the multi-mode frequency divider can be used for outputting the frequency division signal after the frequency division of the multi-mode frequency divider.
Alternatively, in the multi-modulus divider, the control terminal S and the locking terminal E of each frequency divider may be connected to the logic circuit of the multi-modulus divider, so that the logic circuit locks the control terminal S and the locking terminal EThe end E performs configuration; the control terminal S and the locking terminal E of each frequency divider may also be directly used as external terminals for manual configuration. Specifically, the multi-modulus frequency divider may configure the control terminal S and the locking terminal E of each frequency divider according to a desired frequency division ratio to determine the number of frequency dividers involved IN frequency division and the frequency division ratio of each frequency divider, thereby implementing frequency division of the clock signal clk_in according to the desired frequency division ratio. The divided signal can be divided by a first stage divider 2 0 Second output terminal mod_out of (a) 0 And outputting. It will be appreciated that the second output MOD_OUT of the first stage divider 0 The frequency of the signal output by the clock output terminal (such as the first output terminal Fo or the second output terminal mod_out) of the designated frequency divider can be consistent. Wherein a given divider refers to the maximum number of stages of the divider that at least need to participate in the division, as determined by the desired division ratio. The signal output from the second output terminal mod_out of the specified stage divider may be identical in frequency to the signal divided by the specified stage divider.
In some embodiments, multiple cascaded frequency dividers may achieve a division ratio of 2 K ~2 K+1 -1, wherein K refers to the number or number of divider stages in the multi-modulus divider that participate in the division.
In some embodiments, the multi-modulus divider of the present application may be adjusted according to actual needs to achieve a corresponding desired division ratio. In particular, the multi-modulus divider may be configured such that a corresponding configuration signal may be generated to configure the control terminals of the respective dividers according to a desired division ratio. For example, the actually required desired frequency division ratio is 4, the configuration signal corresponding to the control terminal of each frequency divider is represented as 100, the configuration signals generated according to the desired frequency division ratio are sequentially configured from low to high according to the number of frequency divider stages, and the 1 st frequency divider 2 0 Control terminal S of (2) 0 The input is 0 (i.e. control terminal S 0 Access to low level), 2 nd stage frequency divider 2 1 Control terminal S of (2) 1 The input is 0 (i.e. control terminal S 1 Access to low level), 3 rd stage frequency divider 2 2 Control terminal S of (2) 2 The input is 1 (i.e. control terminal S 2 Access to high level), the control terminal of the higher-order frequency divider can be floating or default to be input with 0 (e.gThe control terminal S of the higher order divider is switched in low).
Further, the multi-modulus divider may be further configured to configure the lock terminal according to an input value of the control terminal. For current-stage frequency dividers (e.g. i-th stage frequency divider 2 i-1 ) In other words, if there is a higher order divider (e.g., the (i+1) th order divider 2 i To nth stage frequency divider 2 N-1 ) If the input of the control terminal S is 1, the locking terminal of the current stage is set to 1, so that the clock output terminal (the first output terminal) of the current stage is turned off, the frequency divider of the current stage cannot participate in frequency division, the frequency divider of the current stage is locked, the output signal of the second output terminal is a fixed value, at the moment, the corresponding mod_out=0, and the corresponding frequency divider does not participate in frequency division; otherwise, the locking end E of the current stage is set to 0, so that the clock output end of the current stage can output the frequency-divided signal, and the current stage frequency divider can participate in frequency division in normal operation. In this case, the number of frequency dividers involved in frequency division can be determined by the configuration of the lock terminal, and the frequency division ratio of each frequency divider can be determined by the configuration of the control terminal, thereby achieving a desired frequency division ratio. In addition, the locking end can lock the frequency divider which does not participate in frequency division into a determined state, so that the frequency divider can be ensured to be logically correct when participating in frequency division for the first time in the subsequent frequency division process if the frequency divider is needed. IN this embodiment, the mode selection terminal mod_in of the last divider involved IN the frequency division is turned on low. It will be appreciated that the last stage of divider 2 in multi-modulus divider 1 N-1 Mode selection port mod_in of (a) N-1 The low level can always be accessed.
In another embodiment, referring to fig. 3, 4 and 6, the locking terminal E includes a sub-enable terminal E1 and a sub-state locking terminal E2. In comparison with the multi-modulus divider of FIG. 5, the multi-modulus divider of FIG. 6 utilizes the divider of FIG. 3 having a sub-enable E1 and a sub-state lock E2, wherein the (i+1) th divider 2 i Sub-state lock terminal E2 of (1) i Respectively connected with the ith frequency divider 2 i-1 Is the child enable terminal E1 of (1) i And the adjusting end of the ith inverter, and the connection mode of the other ends is unchanged. In this case, the multi-modulus divider mayConfiguring a control end S and a sub-state locking end E2 according to the expected frequency division ratio; due to the current-stage frequency divider (e.g. i-th stage frequency divider 2 i-1 ) The sub-enable terminal E1 of (1) is connected with the next adjacent stage (i+1st stage frequency divider 2 i ) Is connected to the sub-state lock terminal E2, the sub-enable terminal E1 of the current stage frequency divider is the same as the input of the sub-state lock terminal E2 of the next adjacent stage.
In this embodiment, the configuration of the control terminal S and the sub-state locking terminal E2 is the same as the configuration of the control terminal S and the locking terminal E shown in fig. 5.
In particular, for the current stage frequency divider (e.g. the i-th stage frequency divider 2 i-1 ) In other words, if there is a higher order divider (e.g., the (i+1) th order divider 2 i To nth stage frequency divider 2 N-1 ) If the input of the control terminal S is 1, the sub-state locking terminal E2 of the current stage may be set to 1 to lock the current stage frequency divider, the output signal of the second output terminal is a fixed value, for example, the corresponding mod_out=0, the frequency divider of the current stage does not participate in frequency division, and in addition, since the sub-state locking terminal E2 of the current stage is connected with the sub-enabling terminal E1 of the adjacent upper stage frequency divider (for example, the i-1 stage frequency divider 2 i-2 ) The sub-enable end E1 of the upper stage frequency divider is also set to be 1, so that the clock output end of the upper stage frequency divider is turned off, and the frequency-divided signal cannot be input into the current stage frequency divider; otherwise, the sub-state locking end E2 of the current stage is set to 0, so that the current stage frequency divider can participate in frequency division in normal operation, and the enabling end E1 of the previous stage is also set to 0 due to the input of the state locking end E2 of the current stage, and the previous stage can output the frequency-divided signal to the current stage frequency divider to participate in frequency division.
For the current-stage frequency divider, if the input of the sub-state locking end E2 of the next-stage frequency divider is 0, the inverter connected with the current-stage frequency divider works normally, and the mode selection end MOD_IN of the current stage is connected with the inverted signal of the signal output by the second output end MOD_OUT of the next-stage frequency divider and is controlled by the second output end MOD_OUT of the next-stage frequency divider; if the input of the sub-state locking terminal E2 of the next stage frequency divider is 1, the inverter connected with the sub-state locking terminal E2 does not generate an effect, the mode selection terminal mod_in of the current stage frequency divider is connected to the output signal of the second output terminal mod_out of the next stage frequency divider, at this time, the output of the second output terminal mod_out of the next stage frequency divider is 0, and the input of the mode selection terminal mod_in of the current stage frequency divider is 0.
The multi-mode frequency divider provided in this embodiment can determine the number of frequency dividers involved in frequency division and the frequency division ratio of each frequency divider so as to achieve the desired frequency division ratio, and compared with the multi-mode frequency divider shown in fig. 5, the multi-mode frequency divider provided in this embodiment can directly shut off the first output terminal Fo of the specified stage frequency divider, so that the corresponding signal does not enter the next stage frequency divider, thereby further reducing power consumption.
The above multi-modulus frequency divider, including N frequency dividers according to any of the above embodiments, has all the advantages of the frequency divider according to any of the above embodiments, and is not described herein.
Although the application has been shown and described with respect to one or more implementations, equivalent alterations and modifications will occur to others skilled in the art based upon a reading and understanding of this specification and the annexed drawings. This application is intended to cover all such modifications and variations, and is limited only by the scope of the appended claims. In particular regard to the various functions performed by the above described components, the terms used to describe such components are intended to correspond, unless otherwise indicated, to any component which performs the specified function of the described component (e.g., that is functionally equivalent), even though not structurally equivalent to the disclosed structure which performs the function in the herein illustrated exemplary implementations of the specification.
That is, the foregoing embodiments are merely examples of the present application, and are not intended to limit the scope of the patent application, and all equivalent structures or equivalent processes using the descriptions and the contents of the present application, such as the combination of technical features of the embodiments, or direct or indirect application to other related technical fields, are included in the scope of the patent protection of the present application.
In addition, the present application may use the same or different reference numerals for structural elements having the same or similar characteristics. Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more features. In the description of the present application, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
In this application, the term "exemplary" is used to mean "serving as an example, instance, or illustration. Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments. The previous description is provided to enable any person skilled in the art to make or use the present application. In the above description, various details are set forth for purposes of explanation. It will be apparent to one of ordinary skill in the art that the present application may be practiced without these specific details. In other instances, well-known structures and processes have not been shown in detail to avoid unnecessarily obscuring the description of the present application. Thus, the present application is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features disclosed herein.

Claims (10)

1. The frequency divider is characterized by comprising a 2/3 configurable frequency dividing module, wherein the 2/3 configurable frequency dividing module comprises a clock input end, a control end, a locking end, a mode selection end, a first output end and a second output end;
the clock input end is used for accessing a clock signal to be divided;
the control end and the mode selection end are used for jointly limiting the frequency division mode of the 2/3 configurable frequency division module;
the first output end and the second output end are used for outputting signals after frequency division;
the locking terminal is used for enabling or shutting off the first output terminal.
2. The frequency divider of claim 1, wherein the 2/3 configurable frequency divider module further comprises a reset terminal for accessing a reset signal to reset the 2/3 configurable frequency divider module.
3. The frequency divider of claim 1, wherein the frequency divider comprises a frequency dividing unit and an auxiliary unit;
the frequency dividing unit is used for carrying out frequency division or frequency halving on the clock signal;
the auxiliary unit is used for providing a load for the frequency dividing unit.
4. The frequency divider of claim 3, wherein the auxiliary unit comprises a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor, a sixth MOS transistor, a seventh MOS transistor, and an eighth MOS transistor;
the grid electrode of the first MOS tube is used as the clock input end, the source electrode of the first MOS tube is connected with a set power supply, and the drain electrode of the first MOS tube is respectively connected with the drain electrode of the second MOS tube, the grid electrode of the fourth MOS tube, the grid electrode of the sixth MOS tube and the frequency dividing unit; the grid electrode of the second MOS tube is connected with the frequency dividing unit, and the source electrode of the second MOS tube is connected with the drain electrode of the third MOS tube; the grid electrode of the third MOS tube is connected with the clock input end, and the source electrode of the third MOS tube is grounded; the source electrode of the fourth MOS tube is connected with the set power supply, and the drain electrode of the fourth MOS tube is respectively connected with the drain electrode of the fifth MOS tube, the drain electrode of the seventh MOS tube and the drain electrode of the eighth MOS tube and serves as the second output end; the grid electrode of the fifth MOS tube is connected with the clock input end, and the source electrode of the fifth MOS tube is connected with the drain electrode of the sixth MOS tube; the source electrode of the sixth MOS tube is grounded; the grid electrode of the seventh MOS tube is used for being connected with a reset signal, and the source electrode of the seventh MOS tube is connected with the set power supply; and the grid electrode of the eighth MOS tube is used as the mode selection end, and the source electrode is grounded.
5. The frequency divider of claim 4, wherein the frequency dividing unit comprises a ninth MOS transistor, a tenth MOS transistor, an eleventh MOS transistor, a twelfth MOS transistor, a thirteenth MOS transistor, a fourteenth MOS transistor, a fifteenth MOS transistor, a sixteenth MOS transistor, a seventeenth MOS transistor, an eighteenth MOS transistor, a nineteenth MOS transistor, a twentieth MOS transistor, a twenty-first MOS transistor, a twenty-second MOS transistor, a twenty-third MOS transistor, a twenty-fourth MOS transistor, and a twenty-fifth MOS transistor;
the grid electrode of the ninth MOS tube is respectively connected with the drain electrode of the twenty-second MOS tube, the grid electrode of the eleventh MOS tube, the drain electrode of the seventeenth MOS tube, the drain electrode of the eighteenth MOS tube, the drain electrode of the twenty-second MOS tube, the grid electrode of the twenty-third MOS tube and the grid electrode of the twenty-fifth MOS tube, the source electrode is connected with the set power supply, and the drain electrode is connected with the source electrode of the tenth MOS tube; the grid electrode of the tenth MOS tube is connected with the clock input end, and the drain electrode of the tenth MOS tube is respectively connected with the grid electrode of the second MOS tube, the grid electrode of the fourteenth MOS tube and the drain electrode of the eleventh MOS tube; the source electrode of the eleventh MOS tube is grounded; the grid electrode of the twelfth MOS tube is connected with the clock input end, the source electrode of the twelfth MOS tube is connected with a set power supply, and the drain electrode of the twelfth MOS tube is respectively connected with the source electrode of the thirteenth MOS tube and the source electrode of the sixteenth MOS tube; the grid electrode of the thirteenth MOS tube is connected with the second output end, and the drain electrode of the thirteenth MOS tube is respectively connected with the drain electrode of the fourteenth MOS tube, the drain electrode of the sixteenth MOS tube and the grid electrode of the eighteenth MOS tube; the source electrode of the fourteenth MOS tube is connected with the drain electrode of the fifteenth MOS tube; the grid electrode of the fifteenth MOS tube is connected with the clock input end, and the source electrode of the fifteenth MOS tube is grounded; the grid electrode of the sixteenth MOS tube is used as the control end; the grid electrode of the seventeenth MOS tube is respectively connected with the grid electrode of the nineteenth MOS tube and the drain electrode of the twenty first MOS tube, and the source electrode is connected with the set power supply; the source electrode of the eighteenth MOS tube is connected with the drain electrode of the nineteenth MOS tube; the source electrode of the nineteenth MOS tube is grounded; the grid electrode of the twentieth MOS tube is connected with the drain electrode of the first MOS tube, and the source electrode is connected with the set power supply; the grid electrode of the twenty-first MOS tube is used as the locking end, and the source electrode is grounded; the grid electrode of the twenty-second MOS tube is used for being connected with the reset signal, and the source electrode of the twenty-second MOS tube is connected with the set power supply; the source electrode of the twenty-third MOS tube is connected with the set power supply, and the drain electrode of the twenty-fourth MOS tube is connected with the source electrode of the twenty-fourth MOS tube; the grid electrode of the twenty-four MOS tube is connected with the locking end, and the drain electrode of the twenty-five MOS tube is connected with the drain electrode of the twenty-five MOS tube and used as the first output end; and the source electrode of the twenty-fifth MOS tube is grounded.
6. The frequency divider of claim 5, wherein the lock terminal comprises a sub-enable terminal and a sub-state lock terminal; the grid electrode of the twenty-four MOS tube is used as the sub-enabling end, and the grid electrode of the twenty-four MOS tube is used as the sub-state locking end.
7. The frequency divider of claim 6, wherein the sub-enable enables the first output when a low level is accessed and turns off the first output when a high level is accessed;
when the sub-state locking end is connected with a high level, the 2/3 configurable frequency dividing module is locked, and the second output end outputs a fixed value.
8. A multi-modulus divider comprising N dividers according to any of claims 1 to 7 and N-1 inverters;
the first output end of the ith frequency divider is connected with the clock input end of the (i+1) th frequency divider, the second output end of the (i+1) th frequency divider is connected with the mode selection end of the (i) th frequency divider through the (i) th inverter, and the locking end of the (i+1) th frequency divider is connected with the regulating end of the (i) th inverter; wherein i and N are integers, and i is more than or equal to 1 and less than or equal to N.
9. The multi-modulus divider of claim 8, wherein the multi-modulus divider is configured to determine an input value for a control terminal of each of the dividers based on a desired division ratio and to determine an input value for a lock terminal of each of the dividers based on the input value for the control terminal of each of the dividers.
10. The multi-modulus divider of claim 9, wherein the lock terminal includes a sub-enable terminal and a sub-state lock terminal, the sub-state lock terminal of the i+1th divider being connected to the sub-enable terminal of the i-th divider and the adjustment terminal of the i-th inverter, respectively.
CN202310805780.6A 2023-07-03 2023-07-03 Frequency divider and multi-modulus frequency divider Active CN116545438B (en)

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