JPH10303874A - System for detecting synchronized edge between different clocks - Google Patents

Abstract

PROBLEM TO BE SOLVED: To internally detect a synchronized edge between clocks only with two clocks mutually related in different cycles. SOLUTION: A sample signal generating circuit 2 generates a sample signal by sampling a toggle signal, which is driven by the rise edge of clock signal CLKA having one frequency, generated by a toggle signal generating circuit 1 with a clock signal CLKB having a higher frequency, a pattern holding circuit 3 observes this sample signal, reads and holds a pattern change and based on this pattern change, a synchronized edge detection circuit 4 detects the matched edge of two clocks CLKA and CLKB. At the same time, a synchronizing signal SYNCb for applying data timing between units to be driven by different clocks is generated by the clock signal CLKB. On the other hand, a synchronizing signal generating circuit 5, which receives this matched edge, generates a synchronizing signal SYNCa based on the clock signal CLKA.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for detecting a synchronous edge between different clocks when data is transferred between two units operating with two clocks synchronized with each other and having different frequencies, and a different clock using the same. The present invention relates to an inter-synchronous signal generation circuit, and more particularly to a inter-clock inter-synchronous edge detection method capable of detecting a sync edge between different clocks without using any clock other than these two clocks, that is, only with two clocks related to each other.

[0002]

2. Description of the Related Art Generally, in a computer or other electronic device, an optimum operating frequency is set for each unit constituting the device, so that the operating frequency may be different for each unit. Therefore, when performing stable data transfer between units having different operating frequencies,
It is common to generate a synchronous clock that periodically matches the edges of the two clock signals supplied to each unit.

For example, as shown in FIG. 6, the frequency ratio of two clock signals CLK a and CLK b, that is, the clock signal CLK a of the lower frequency and the clock signal CLK b of the higher frequency are frequency ratio. In the case of 2: 3, the synchronous clock is generated such that the clock edges overlap each other for each of these least common multiples.

That is, a stable reference clock signal that causes the rising edges of the clock edges to coincide with each other is generated every second clock signal CLK a and every third clock signal CLK b, and the phase of data to be transmitted and received. By adjusting the relationship based on the coincident clock edge, stable data transfer can be performed.

As described above, when data is transferred between a plurality of units operating with clocks of different frequencies which are synchronized with each other, the timing condition of the data transfer differs depending on the phase difference between the two clocks, so that the appropriate phase relationship is obtained. It is necessary to control to send and receive data in. That is, in order to perform stable data transfer, it is necessary to correctly recognize the phase relationship between the two clocks during data transfer.

In general, a data signal is often transmitted at the same timing as a synchronous edge that coincides between clocks. However, a data signal may be transmitted / received with a phase relationship shifted depending on conditions such as delay.

Conventionally, in this type of synchronous edge detection between different clocks, in order to recognize the phase relationship between clocks in a plurality of units involved in transmission / reception of data transfer, a clock generation circuit or the like is provided outside the units, and this clock is used. A signal indicating a phase is supplied separately from a clock signal received by the unit from a generation circuit or the like, and a synchronization edge between different clocks is often set based on the signal indicating the phase.

[0008]

The above-described conventional different clock synchronization edge detection method has the following problems.

First, the first problem is that it is difficult to manage the skew with respect to the shift of the clock edge.

[0010] The reason is that the length of the connection line between the two operation circuits using the same two clock signals and the clock generation circuit for generating the clock and distributing the clock signal is different in many cases. This is because a difference in the propagation delay time occurs, the same clock signal cannot arrive at the same flip-flop circuit in the two target operation circuits, and the value of the flip-flop circuit lacks accuracy.

The second problem is that an additional circuit is required, which increases the failure rate.

The reason for this is that the reference clocks for giving timings with aligned edges to the two circuits operating with different clock signals are generated at frequencies different from the operating frequencies of the two target circuits. This is because the number of components for the reference clock generation circuit increases, and therefore, an increase in space for mounting components and an increase in the failure rate due to mounting components are inevitable.

Further, a third problem is that the integrated circuit to be operated requires an increase in the number of input / output pins.

The reason is that an additional signal line for distributing the added reference clock becomes redundant, so that it is necessary to secure input / output pins.

An object of the present invention is to solve the above-mentioned problems and to use a clock other than the two clocks of interest without special use.
That is, it is to provide a synchronization edge detection method between different clocks that can detect a synchronization edge between different clocks only with two clocks related to each other.

[0016]

A synchronous edge detection method between different clocks according to the present invention detects a synchronous edge between different clocks when data is transferred between circuits operating with two clocks synchronized with each other and having mutually different frequencies. In this method, a toggle signal is created by a clock of one lower frequency, and this toggle signal is observed by a clock of the other higher frequency. On the other hand, there is provided a detecting means for detecting a rising edge that coincides with the least common multiple as a synchronization edge between different clocks based on a predetermined change of the bit pattern.

One of the concrete means is a different clock synchronization edge detection method when data is transferred between circuits which are synchronized with each other and operate with two clocks having a frequency ratio of 2 to 3. , A toggle signal generation circuit that creates a toggle signal with one of the lower frequency clocks, and a flip-flop circuit with a plurality of serial connection configurations that operates the created toggle signal with the other higher frequency clock. It is composed of a synchronization circuit that latches a plurality of continuous signal states as sample signals by outputting via the output, and a plurality of serial flip-flop circuits that operate by the clock of the higher frequency The latched circuit and the multiple values latched by the flip-flop circuit of this latch circuit are the same. Out, and a synchronous edge detection means for detecting a center point of the same section as the synchronized edges between different clocks.

According to this configuration, the clock signals output from each of the two clocks are input without receiving a reference clock or a phase relationship separately created from the outside, and internally synchronized only by the two clock signals. An edge has been detected.

[0019]

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a functional block diagram showing an embodiment of the present invention.

In the synchronous edge detection method between different clocks according to the present invention, the toggle signal generation circuit 1, the sample signal generation circuit 2, the pattern holding circuit 3, the synchronous edge detection circuit 4, and the synchronous signal generation circuit 5 form the synchronous edge detection means. The synchronization edge detection circuit 4 detects a synchronization edge between two different clocks, and based on the detected synchronization edge, the transfer timing of the data transfer of the unit driven by the clock signal. Are output from the synchronous edge detecting circuit 4 and the synchronous signal generating circuit 5, respectively.

The toggle signal generation circuit 1 converts the input clock signal CLKA of the lower frequency into a toggle signal that forms a periodic pattern change by code "0/1", and outputs the toggle signal.

The sample signal generation circuit 2 samples the toggle signal output from the toggle signal generation circuit 1 with the clock signal CLKB of the higher frequency to generate a sampling signal and sends it to the pattern holding circuit 3. I do.

The pattern holding circuit 3 holds the same bit pattern of the sample signal output from the sample signal generation circuit 2 which is repeated at a constant period.

The synchronous edge detection circuit 4 selects the timing of the matching rising edge set in advance from the bit patterns held by the pattern holding circuit 3 in accordance with the clock signal CLKB of the higher frequency, and sets it to a higher value. It is assumed that the synchronous clock SYNC b of the lower frequency is output and the rising edge is taken out as the synchronous edge.

The synchronizing signal generation circuit 5 obtains the rising edge of the synchronizing edge output from the synchronizing edge detecting circuit 4 and generates and outputs a synchronizing clock SYNC a having a lower frequency.

Next, the operation principle of the present invention will be described with reference to FIG. 1 and FIG.

In FIG. 2, for simplification of explanation, it is assumed that the frequency ratio of the two clock signals CLKA and CLKB is 2: 3. In this case, as shown in the figure, the bit pattern is determined by the three sample signals, and the intermediate position when two identical values continue in the change pattern is the timing at which the rising edges of two different clocks overlap.

Therefore, the sample signal generation circuit 2 in FIG. 1 has a three-stage series configuration using flip-flop circuits, and the pattern holding circuit 3 has a series configuration using two-stage flip-flop circuits so as to hold continuous sample signals. Shall be.

In FIG. 1, as described above, the toggle signal generation circuit 1 generates a toggle signal at the rising edge of the lower frequency clock signal CLKA and outputs the same to the sample signal generation circuit 2.

The sample signal generation circuit 2 samples the input toggle signal with the clock signal CLKB having the higher frequency, and can successively hold three consecutive sample signals in three flip-flop circuits. The pattern holding circuit 3 sequentially takes in the output of the final stage flip-flop circuit of the sample signal generation circuit 2 and sequentially holds two consecutive sample signals in the two flip-flop circuits.

The number of flip-flop circuits constituting each of the sample signal generation circuit 2 and the pattern holding circuit 3 and the location where the pattern holding circuit 3 inputs from the sample signal generation circuit 2 are appropriately determined based on the frequency ratio of the two clocks. Is set.

In the case of FIG. 2A, which is an example of a frequency ratio of 2 to 3, two clock signals CLK A and CLK indicated by arrows are shown.
The timing at which the rising edges of B coincide with each other is the timing at which the value of the toggle signal changes from "1" to the value "0". In the case of FIG. 2B, the timing at which this edge coincides with the value of the toggle signal "0". It is the timing when the value changes from "" to "1".

That is, the rising edge in the synchronous edge detecting circuit 4 is changed pattern "1" in FIG. 2 (A).
→ 1 ”, and in FIG. 2B, the change pattern is“ 0 → 0 ”
The output value “1” rises at this timing.

Therefore, the synchronous edge detection circuit 4 detects that the same value of the two flip-flop circuits of the pattern holding circuit 3 is continuous by, for example, a comparator, and the rising edges of the two clock signals CLK A and CLK B. As a detection of the timing at which the clock signal CLKB overlaps, an edge rises and a synchronization signal SYNC b having an interval time between rising edges of the clock signal CLKB is generated and output.

The synchronizing signal generating circuit 5 receives the signal from the synchronizing edge detecting circuit 4, raises the edge at the same time as the synchronizing signal SYNC b output by the synchronizing edge detecting circuit 4, and the time interval between the rising edges of the clock signal CLK A. Generates and outputs a synchronization signal SYNC a.

Although the flip-flop circuit is used in the above description, another circuit configuration may be used as long as it has the same function.

[0037]

Next, with reference to FIGS. 3 to 5, only clock signals having two different frequencies, which are objects of the present invention, are inputted, and their coincident edges are detected. An embodiment for generating the two synchronization signals described above will be described.

In FIG. 3, as in FIG. 2, it is assumed that the frequency ratio for each of two clock signals CLK A and CLKB having different frequencies is 2: 3. Further, the clock signals CLK A and CLK B are synchronized with each other, so that the mutual relationship does not change with the elapsed time, and that the clock edges coincide with each other in a predetermined cycle within a predetermined skew range. It has been done.

FIG. 4 shows the case of FIG. 2A described above, and FIG. 5 shows the case of FIG. 2B described above.

First, each component will be described with reference to FIG.

In the illustrated different clock synchronization edge detection method, the toggle signal generation circuit 11 and the delay guarantee buffer 1 are used.
2. Synchronization circuit 13 corresponding to sample signal generation circuit 2 in FIG. 1, latch circuit 1 corresponding to pattern holding circuit 3
4, 15, a comparator 16 corresponding to the synchronous edge detection circuit 4, a hold circuit 17, an AND circuit 18, a selector circuit 19 and a loop circuit 20, and a negative AND circuit 21 corresponding to the synchronous signal generating circuit 5, a selector It is assumed that the circuit 22, the synchronizing circuit 23, and the comparator 24 constitute synchronous edge detecting means.

The synchronous edge detecting means includes two clock signals each having its own operating frequency and the operating frequency of the data transfer destination, ie, a lower frequency clock signal CLKA and a higher frequency clock signal CLKA. Assume that you have received CLKB.

The toggle signal generation circuit 11 receives the clock signal CLKA of the lower frequency, generates and outputs a toggle signal that forms a periodic pattern change by code "0/1", and has a one-stage configuration. It is assumed that the circuit is a T-type flip-flop circuit.

The delay guarantee buffer 12 includes a synchronization circuit 13
In order to manage the delay until the input to the signal, the phase of the toggle signal generated by the toggle signal generation circuit 11 is delayed by an amount necessary for the operation unit.

The synchronization circuit 13 includes the delay guarantee buffer 12
Is a three-stage serial D-type flip-flop circuit for sampling the toggle signal output from the higher frequency clock signal CLKB to read the change pattern, and operating with the clock signal CLKB to avoid an unstable state. It shall be composed of The number of serial stages is set by the frequency ratio of two clock signals, as described above.

The latch circuit 14 outputs the output of the synchronization circuit 13,
The latch circuit 15 latches each output of the latch circuit 14 as a sample signal with the clock signal CLKB, and is assumed to be a one-stage flip-flop circuit.

The comparator 16 includes the latch circuits 14 and 1
5 are compared with each other, a continuation of sample signals of the same value is detected, and a signal referred to as a source signal SYNC-b0, which is a basis of the synchronization signal SYNCb, is output to the selector circuit 19. The above-described intermediate point of the same value is the coincident synchronous edge of the two clock signals CLK A and CLK B.

After the reset signal RST is input, the hold circuit 17 waits for a certain period of time until the detection of the synchronous edge until the entire circuit becomes stable, and the edge detection start signal S
YNC-r shall be output.

When receiving the start signal SYNC-r, the AND circuit 18 changes the output generation signal SYNC-g from the value "0" to the value "1".

The selector circuit 19 receives the original signal SYNC-b0 from the comparator 16, and after the generated signal SYNC-g received from the AND circuit 18 changes to the value "1", after the first detection of the synchronous clock edge. In this example, a new signal is not detected, and the mode is switched to a mode in which a synchronization signal is continuously output periodically using the same number of shift registers as the period of the detected synchronization clock edge.

It is assumed that the loop circuit 20 receives the output of the selector circuit 19 and operates in response to the clock signal CLKB in a serial configuration of the same three-stage flip-flop circuit as the synchronizing circuit. This loop circuit 20 generates the generated signal SYNC-g.
Between the value "0" and the selector circuit 19 to form a closed loop circuit and synchronize with the clock signal CLKB to latch the change pattern of the pattern signal for observation. To do.

The negative logical product circuit 21 includes the latch circuit 1
A signal referred to as a primitive signal SYNC-a0, which is the basis of the synchronizing signal SYNC a, is output to the selector circuit 22 by taking the NAND of the values held by the signals 4 and 15.

The selector circuit 22 is a flip-flop circuit for selecting the synchronizing signal SYNCa, receives the original signal SYNC-a0, and inputs the clock signal CLKB and the logical product circuit 1
8 operates in response to the generated signal SYNC-g.

That is, in the selector circuit 22, the output changes to the value "1/0" when the generation signal SYNC-g has the value "1", but when the value "0", the generation signal SYNC-g. The signal set by is to be held. Therefore,
When the values of the latch circuits 14 and 15 coincide with each other, that is, when the sample signal continuously takes the same value, the value "0" is output if the value "1" continues at an intermediate timing. When the value “0” continues, each value “1” is held.

The synchronizing circuit 23 is serially constructed by the same three-stage D-type flip-flop circuit as the synchronizing circuit 13, and the output of the selector circuit 22 is input to the synchronizing signal 23.
It shall operate by LKA. Therefore, the selector circuit 2
2 will be synchronized by the clock signal CLKA.

The comparator 24 receives the output of the synchronization circuit 23 and the toggle signal output from the toggle signal generation circuit 11, and outputs the coincident part as a synchronization signal SYNCNa driven by the clock signal CLKA. I do.

Next, a functional operation according to the present invention will be described with reference to FIGS.

First, the clock signal CLK of the lower frequency
From A, the value is changed from “0 → 1 → 0” in a cycle that matches this frequency.
The toggle signal that changes from "1" to the toggle signal generation circuit 1
It is generated by one T-type flip-flop circuit.

Then, the toggle signal is given a necessary delay time by the delay guarantee buffer 12, and then, in order to avoid an unstable state, a three-stage flip-flop circuit and latch circuits 14, 15 of a synchronization circuit 13 in series. Are sampled by the higher frequency clock signal CLKB as a sample signal, and two successive values of a periodic pattern as shown in FIG. It is latched to each 15.

As shown in FIG. 2, an edge sandwiched between two consecutive same values has two clock signals CLK.
A and CLKB have the same edge, and synchronizing signals SYNC a and SYNC b synchronized with this edge are clock signals CLK.
Generated for each of A and CLKB.

Therefore, the value "1" of the synchronizing signal SYNC a is the timing of the toggle signal having a value opposite to the continuous value,
On the other hand, the value "1" of the synchronization signal SYNC b is the timing of the toggle signal of the second value which is a continuous value. That is, as shown in FIG. 2A, in FIG. 2A, the synchronization signal SYNC b is generated at the second timing of the value “1” which is continuous with the sample signal, and the synchronization signal SYNC a is not continuous with the sample signal. It is generated at the timing of the toggle signal at the value “0”.

Returning to the explanation, the two values latched in the latch circuits 14 and 15 are compared by the comparator 16 on the one hand, and if they match, the value "1" is output from the comparator 16. The source signal SYNC-b0 is generated at the timing. On the other hand, a source signal SYNC-a0 for the synchronizing signal SYNC a is generated by the NAND circuit 21 between the two values.

As a result, the value "1" is obtained as shown in FIG.
, The sync signal SYNC b becomes the value “1” at the intermediate timing, and this inverted value “0” becomes the select signal of the sync signal SYNC a.

When the value "0" is continuous as shown in FIG. 5, the synchronization signal S is output at an intermediate timing.
YNCb becomes the value "0", and the inverted value "1" becomes the select signal of the synchronization signal SYNCa.

Generation signal SYN input to selector circuit 19
Cg is the output of the AND circuit 18 and the reset signal R
After the value of ST becomes “1”, when the first-stage flip-flop circuit of the loop circuit 20 latches the value “1”,
Since the inverted value “0” is output to the AND circuit 18,
The generated signal SYNC-g which is the output of the AND circuit 18 has the inverted value “1” until it becomes the value “0”.

During this time, the selector circuit 19 outputs the input original signal SYNC-b0 to the loop circuit 20, and the selector circuit 22 inputs the original signal SYNC-a0 from the NAND circuit 21.

Next, the first-stage flip-flop circuit of the loop circuit 20 holds the original signal SYNC-b0 while the generated signal SYNC-g is at the value "1". On the other hand, the selector circuit 22
Is the original signal SYNC-a0 while the generated signal SYNC-g is "1".
Is the value that was last taken, while the signal SYNC-g is "0",
Hold.

When the reset signal RST is released, the logic value 1 is held by the hold circuit 19 for a period necessary for stabilizing the latch operation of all flip-flop circuits, and after waiting for this period, , The start signal SYNC-r is output at the value “1”.

Each of the three-stage flip-flop circuits of the loop circuit 20 is set to an initial value "0", and calculates the logical product of these inverted values and the value "1" of the start signal SYNC-r by a logical product circuit. By obtaining the output value "1" at 18, the generation signal SYNC-g becomes the value "1" and the operation of detecting the coincident edge of the two clock signals CLKA, CLKB is started.

For the clock signal CLKA, when the generation signal SYNC-g becomes “1”, the output value of the NAND circuit 21, that is, the sample signal The value "1" is latched when the continuous value is "0", and the value "0" is latched when the sample signal is the continuous value "1". This value is sent to the comparator 24 via the three-stage serial flip-flop circuit of the synchronization circuit 23.
Is output to

In the comparator 24, the output synchronization signal S
The selector circuit 22 as shown in FIG.
In the case where the value is "0", the value "1" is output while the value of the toggle signal is "0", while when the value is "1" in the selector circuit 22 as shown in FIG. 5, the value of the toggle signal is The value “1” is output during “1”.

Therefore, the synchronizing signal SYNC a can give the transfer timing of the data transfer of the unit driven by the clock signal CLKA.

On the other hand, for the clock signal CLKB, the selector circuit 19 while the generation signal SYNC-g has the value "1".
, I.e., the value "1" of the original signal SYNC-b0 at which the coincidence of the edges, which is the intermediate timing of the same data of the sample signal, is input to the loop circuit 20.

Since the negative value "0" of the value "1" output from the first-stage flip-flop circuit of the loop circuit 20 to the second stage is input to the AND circuit 18, the AND circuit 18 is provided. The generated signal SYNC-g of the output of the above takes the theoretical value "0". By inputting the generated signal SYNC-g of the theoretical value “0”, the selector circuit 19 is connected to the series three-stage flip-flop circuit of the loop circuit 20 to form a feedback loop circuit.

Therefore, one of the three-stage flip-flop circuits of the loop circuit 20 synchronized with the clock signal CLKB takes the value "1", and the other two take the value "0". As a result, the generated signal SYNC-g has a theoretical value of "0".
, The feedback loop circuit once formed is permanently configured.

This means that the pattern of the value "1, 0, 0" is sequentially set in the three-stage flip-flop circuits of the loop circuit 20, so that the output of the last-stage flip-flop circuit, that is, the loop circuit The output of 20 becomes the synchronizing signal SYNC b, and the synchronizing signal SYNC b gives the transfer timing of the data transfer of the unit driven by the clock signal CLKB.

In the above description, the case where the frequency ratio of the two clocks is 2: 3 has been described. However, the present invention is not limited to this ratio.
The present invention can be easily applied to clocks which have a simple integer ratio and are mutually synchronized such that clock edges coincide with each other at a constant period, that is, at the least common multiple of the clock period. In such a case, since the change pattern of the sample signal is uniquely determined according to the frequency ratio of the clock, it is sufficient to detect the pattern and generate the synchronization signal SYNC.

In the above description, the functional blocks have been illustrated and described. However, the components can be freely changed by separating and merging the functions as long as the above functions are satisfied. For example, although it may be a module, or only a flip-flop circuit has been described as a specific means for realizing the above function, other circuits may be applied. Thus, the configuration is free as long as the above functions are satisfied, and the above description does not limit the present invention.

[0079]

As described above, according to the present invention, the following effects can be obtained.

The first effect is that the number of components can be reduced. As a result, the chip size of an integrated circuit forming a unit or a module can be reduced, and the reliability of an operation circuit can be improved.

The reason is that it is not necessary to externally create and supply edge information or phase information that coincides with two clocks having different frequencies, and thus a signal line that receives information for coincident edges from the outside is unnecessary. In addition, it is possible to eliminate the need for a clock generation circuit that generates a clock having coincident edges from the supplied information.

The second effect is that the number of pins in the integrated circuit can be saved.

The reason is that, as described above, the dedicated pin for receiving the information for matching the edges from the outside is unnecessary.

The third effect is that the skew management for the shift of the clock edge becomes easy.

The reason is that, as described above, since the coincident clock edge is detected and generated internally, the permissible range of the shift between clocks can be made larger than that detected by externally applied information.

The third effect is that the applicable range is wide for two clock frequencies.

The reason is that the principle of the present invention can be applied to two clocks having an arbitrary integer ratio.

[Brief description of the drawings]

FIG. 1 is a functional block diagram showing an embodiment of the present invention.

FIG. 2 is an explanatory diagram showing the principle of the present invention.

FIG. 3 is a block diagram showing one embodiment of the present invention.

FIG. 4 is a time chart under the conditions of FIG. 2A in FIG.

FIG. 5 is a time chart under the conditions of FIG. 2B in FIG.

FIG. 6 is an explanatory diagram of a reference clock signal when the frequency ratio of two clocks is 2 to 3.

[Explanation of symbols]

 1, 11 toggle signal generation circuit 2 sample signal generation circuit 3 pattern holding circuit 4 synchronous edge detection circuit 5 synchronization signal generation circuit 12 delay guarantee buffer 13, 23 synchronization circuit 14, 15 latch circuit 16, 24 comparator 17 hold circuit 18 logic Product circuits 19 and 22 Selector circuits 20 Loop circuits 21 Negative AND circuits

Claims (3)

[Claims] 1. A method for detecting a synchronous edge between different clocks when data is transferred between two circuits synchronized with each other and operated by two clocks having different frequencies, a toggle signal is generated by a clock having one of the lower frequencies. And
Observe this toggle signal with the other higher frequency clock, and use the greatest common divisor for the frequency of these clocks and the least common multiple for the clock period, and use the rising edge that matches with the least common multiple as the synchronization edge between different clocks. A synchronous edge detection method between different clocks, comprising a detecting means for detecting based on a predetermined change of a bit pattern. 2. In a different clock synchronous edge detection method for performing data transfer between circuits operating with two clocks synchronized with each other and having different frequencies, a toggle signal is generated by a clock having one lower frequency. A toggle signal generation circuit, a sample signal generation circuit that sequentially latches the toggle signal with a clock of the other higher frequency to generate a sample signal, a pattern holding circuit that holds a continuous bit pattern, A synchronous edge detecting circuit for detecting a predetermined bit pattern from the bit pattern and detecting a predetermined time point of the bit pattern as a synchronous edge between different clocks. 3. A synchronous edge detection method between different clocks when data is transferred between two circuits synchronized with each other and operated by two clocks having a frequency ratio of 2: 3, using a clock having one of the lower frequencies. A toggle signal generating circuit for generating a toggle signal, and a plurality of continuous toggle signals generated by outputting the generated toggle signal through a flip-flop circuit having a series connection configuration operated by a clock having the other higher frequency. A synchronization circuit that latches a signal state as a sample signal, a latch circuit configured by a plurality of serial flip-flop circuits that receive an output of the synchronization circuit and operate with a clock having a higher frequency, A case where a plurality of values latched by the flip-flop circuit are the same is detected, and the center point of the same section is different. A synchronous edge detecting means for detecting a synchronous edge between clocks.