JP2596336B2 - Asynchronous digital communication device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital communication apparatus, and more particularly, to an asynchronous digital communication apparatus for transferring data between modules operating with independent clocks.

[0002]

2. Description of the Related Art A printed circuit board (PC) in a card cage is an example of a digital device for transferring data between two modules having independent clock phases.
B), and each PCB is supplied with a clock from a separate clock source. Also, each PCB is considered here as a module. Another example of such a digital device is
An integrated circuit (IC) on a PCB, and each PCB is supplied with a clock from a separate clock source. In addition, each IC
Are considered here as modules.

[0003] Conventional asynchronous digital communication methods use a bitwise handshake protocol.
However, the maximum transfer rate is limited by the interconnect delay on the link between the modules. If the bit-wise handshake protocol is implemented by a synchronous digital device, ie, dependent on a common clock, the maximum transmission rate is also limited by the synchronization delay. If a self-synchronization circuit is applied for the implementation of a bitwise handshake protocol, synchronization delays can be avoided. However, software tools for designing and verifying self-synchronous circuits are not widely used at present.

Another method of transferring data between modules having independent clock sources has been used in digital communication devices. In such digital communication devices, the timing information is derived from the data, for example using a synchronization word, or from an additional data valid signal in parallel with the data. Synchronization of data with the local clock is performed by PLL (Phase
Locked Loop) is performed. However, in a synchronous circuit based on the PLL method, P
The clock rate of LL is several times faster than the data bit rate.

[0005]

As clock speeds of digital devices increase, interconnect delay and clock skew become relatively large. Therefore, it is difficult to distribute a global clock for synchronizing data transfer. Conventionally, the maximum communication speed of the asynchronous handshake protocol has been limited by interconnect delay.

It is an object of the present invention to provide an NR parallel to data, independent of the interconnect delay between the transmitting and receiving circuits.
An object of the present invention is to provide an asynchronous digital communication device for performing digital data transfer between modules operating with independent clocks by using a Z write signal.

Another object of the present invention is to

It is an object of the present invention to provide an asynchronous digital communication device which can be realized using currently available chip design tools and standard synchronous logic elements.

[0009]

SUMMARY OF THE INVENTION The present invention relates to an asynchronous digital communication apparatus for asynchronously transferring data between a transmitting circuit and a receiving circuit which operate on independent clocks.

[0010] The transmission circuit includes a means for generating an NRZ write signal, a means for generating transmission data in which input data is relatively delayed as compared with the NRZ write signal, and a BAF signal from the reception circuit. Means for synchronizing with a local clock of a transmitting circuit, and means for stopping the asynchronous transfer using the BAF signal, wherein the receiving circuit synchronizes the NRZ write signal with a local clock of the receiving circuit, A synchronization unit for latching the transmission data and generating a write signal using the NRZ write signal, and storing the transmission data latched by the write signal, wherein the stored data exceeds a certain amount. And a FIFO buffer for outputting the BAF signal.

[0011]

The large-scale digital system is regarded as a set of synchronization areas, and each area is supplied with an independent clock. The clock relationship of each area is mesochronous (mesochronous: a common clock source but different phases) or plesiochronous (pleschronous).
iochronous: different clock sources but the same clock speed), or heterochronous (heter
ochronous: different clock speeds).

FIG. 1 shows a communication link between two synchronization domains. The receiving module is a synchronous circuit (SYNC)
And an FIFO buffer.

[0013] The synchronization module receives the input write signal WR1.
And the data signal D2 are synchronized with the local clock CLK2H. The write signal WR1 is input in parallel with the data signal D2, and indicates when data is valid. NRZ
The (Non Return to Zero) signal method is used for the write signal WR1. This means that the level of the write signal WR1 is changed every time new data exists. NRZ signaling requires a minimum transition in the write signal WR1 for each data bit transferred. This is an important point for the later synchronization of the write signal WR1.

The FIFO buffer 8 has an elastic buffer.
A memory is provided to compensate for clock speed differences between local clock signal CLK1H and local clock signal CLK2H. If the relationship between local clock signal CLK1H and local clock signal CLK2H is mesochronous, data flows continuously and there is no danger of overflow. However, if the clock relationship between the two areas is plesiochronous or heterochronous, there is a risk of overflow. Thus, a feedback loop from the FIFO buffer in the form of a Buffer Almost Full signal guarantees control of data inflow. Since the signal BAF is transmitted between the two synchronization regions, the signal BAF is transmitted to the local clock signal CL.
It is necessary to synchronize with K1H. To keep the system immune to interconnect delays and synchronization delays, FIFO buffers must be configured with capacity overhead to ensure that no data is lost in the wiring.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First, the components of the circuit configuration of the present invention will be described with reference to FIG. The present invention includes a circuit (transmitting circuit) 1 for transmitting data and a circuit (receiving circuit) 2 for receiving data. These two circuits are connected via an n-bit data cable 17, a write signal cable 18, and a signal BAF (Buffer Almost Full) cable 19.

The transmission circuit 1 has an n-bit width input register 3 for latching input data DIN to be transmitted, and an NRZ (Non-Return) signal from the input write signal WRIN.
(nto Zero) toggle flip-flop 4 for generating write signal WR1, n-bit width negative edge toggle register 5 for delaying data D1 by １ ／ cycle of local clock signal CLK1H, and signal B
And a D flip-flop 6 for synchronizing the AF1 with the local clock CLK1H.

The receiving circuit 2 includes a synchronizing circuit 7 for synchronizing the data D2 and the NRZ write signal WR1 with the local clock CLK2H, and an n-bit width synchronous FIFO (First In First) serving as an elastic buffer.
(st Out) buffer 8, a D flip-flop 9 for generating an appropriate read pulse for the FIFO buffer 8, and a two-input AND gate 10.

The configuration of the synchronization circuit 7 will be described with reference to FIG. The synchronization circuit includes n 2-input AND gates 1 for enabling or disabling n-bit width data D2.
1, data D2 sampling and write signal WR1S
D flip-flop 12 and a two-input EXOR gate 14 that control the generation of
D flip-flop 13 for synchronizing signal WR1 with local clock CLK2H, n-bit width register 15 for sampling data D2, and write signal WR
And a D flip-flop 16 holding 1S.

Each circuit element in FIG. 1 is connected as follows. The n-bit width input data DIN is connected to the input D of the register 3 synchronized by the clock signal CLK1. Output Q of register 3 is connected to input D of negative edge trigger register 5 synchronized by local clock signal CLK1H. The output Q of the negative edge trigger register 5 is the output signal D
2 are connected. The output signal D2 is connected to the data input DI of the synchronization circuit 7 of the reception circuit 2 via the cable 17. The write signal WRIN is the clock signal CLK.
1 is connected to the enable input E of the toggle flip-flop 4 which is synchronized by 1. The output Q of the toggle flip-flop 4 is connected to the output signal WR1. The output signal WR1 is connected via a cable 18 to a write input WR of the synchronization circuit 7 of the reception circuit 2. Transmission circuit 1
Is output from the local clock signal CL.
It is connected to the output Q of the D flip-flop 6 synchronized by K1H. Input D of D flip-flop 6
Is connected to the signal BAF of the FIFO buffer 8 of the receiving circuit 2 via the cable 19.

The synchronization circuit 7 and the FIFO buffer 8
It is connected via an n-bit data connection D2S and a write signal WR1S. Output data D of FIFO buffer 8
O is connected to the output data DOUT, and the output signal BE of the FIFO buffer 8 is connected to the output signal BEOUT. The synchronization circuit 7, FIFO buffer 8, and D flip-flop 9 are synchronized by the local clock signal CLK2H. The read signal RDIN is connected to one input of the AND gate 10. AND gate 1
The other input of 0 is the inverted output / Q of the D flip-flop 9.
, And the output of the AND gate 10 is connected to the input D of the D flip-flop 9. The output Q of the D flip-flop 9 is connected to the read input RD of the FIFO buffer 8.

Each circuit element in FIG. 2 is connected as follows. Each bit of the data D2 from the cable 17 is
It is connected to one input of each of the n AND gates 11. The outputs of the n AND gates 11 are connected to the inputs D of the n D flip-flops 15. Cable 1
8 is connected to the input D of the D flip-flop 13. The output Q of the D flip-flop 13 corresponds to the inputs D and E of the D flip-flop 12.
It is connected to one input of XOR gate 14. The output Q of the D flip-flop 12 is connected to the other input of the EXOR gate 14. The output of the EXOR gate 14 is the input D of the D flip-flop 16 and the n A flip-flops.
It is connected to the other input of the ND gate 11. The output Q of the n-bit width register 15 is connected to the n-bit width input DI of the FIFO buffer 8. The output Q of the D flip-flop 16 is connected to the write input WR of the FIFO buffer 8. All flip-flops of the synchronization circuit 7 are synchronized by the local clock signal CLK2H.

The operation of the asynchronous digital communication device of the present invention will be described with reference to the timing chart of FIG. 3 and the block diagram of FIG. The transmitting circuit 1 and the receiving circuit 2 are arranged in two different modules. Each module is provided with a separate local clock source. Therefore, local clock signal CLK1H is independent of local clock signal CLK2H. The frequency of the clock signal CLK1 is the local clock signal CLK1H
And a certain phase difference exists between the clock signal CLK1 and the local clock signal CLK1H. The frequency of clock signal CLK2 is の of the frequency of local clock signal CLK2H, and there is a certain phase difference between clock signal CLK2 and local clock signal CLK2H.

Data is transmitted in the same manner as a write signal to the synchronous FIFO buffer 8. Write signal WRIN
Is high, the input data DIN is transferred to the FIFO buffer 8. The data speed of the input data DIN is the same as the clock speed of the clock signal CLK1. On the receiving side, the data is read as if it were in the synchronous FIFO buffer 8. When the read signal RDIN is logic “high”, the data in the FIFO buffer 8
Output to output data DOUT. Output data DOUT
Is read from the FIFO buffer 8 at the same speed as the clock speed of the clock signal CLK2. Signal BAFOU
T indicates that the FIFO buffer 8 is almost full (al
signal when it will be the most full. Signal BE
OUT indicates when the data in the FIFO buffer 8 becomes empty.

FIG. 3 shows an example in which five words are transferred between the transmission circuit 1 and the reception circuit 2. The FIFO buffer 8 becomes almost full, and data transfer must be stopped before sufficient data is read from the FIFO buffer 8. Since the transmission circuit 1 and the reception circuit 2 are operated by independent clock sources, and the signals must propagate through the cables 17 to 19, after the buffer becomes full in the reception circuit 2, the transmission circuit 1 and the reception circuit 2 There is a delay before it is detected at. To avoid overflow of the FIFO buffer 8, a buffer almost full signal BAF is used instead of buffer full. This provides overhead for the additional data word, and overflow is prevented even if the data word comes in after signal BAF is a logic "high". This overhead depends on the interconnect delay and the synchronization delay.

Referring to the timing chart of FIG.
The function of will be described. Data word DIN is in register 3
Is input synchronously. This data is again synchronously input to the second register 5 which delays the data D2 as compared with the write signal WR1. When the write signal WRIN is logic “high”, the toggle flip-flop 4 changes the level,
Signal that the data is valid. This type of signaling is based on NRZ (Non Return to Zero)
o) Also called a method. The use of the NRZ method causes a minimum transition in the write signal WR1. this is,
When the write signal WR1 is at the change level, the write signal WR
This is an important point for reducing the possibility of sampling.

The function of the synchronization circuit 7 will be described with reference to FIG. The D flip-flop 12 and the two-input EXOR gate 14 control sampling of the data signal D2 and generation of the write signal WR1S. FIG. 5 shows a state transition diagram of this function. Each time the level of the synchronized write signal WR1 changes, the data signal D2 is sampled and the write signal WR1S is set. An important point in the above-described communication method is synchronization of the write signal WR1 with respect to the local clock signal CLK2H. Write signal WR1
The data signal D2 does not need to be synchronized because the delay between the data signal D2 and the data signal D2 can be assumed to be constant. The phase of the write signal WR1 is the local clock signal CLK2H
, The reception D flip-flop 13 of the synchronization circuit 7 may fall into an unstable state in which the output Q is undefined. After a certain period defined as the settling time t _E , there is a possibility that the output will stabilize at a constant level. However, it cannot be predicted whether the level of the output Q of the D flip-flop 13 is at logic “1” or logic “0”. Therefore, the clock speed for synchronizing the D flip-flop 13 must be twice the data bit transfer speed. This is shown in FIGS. 6 and 7. Here, the D flip-flop 13 is in an unstable state. This is because the level of the write signal WR1 changes simultaneously with the rising edge of the local clock signal CLK2H. This is shown as hatched areas in FIGS. In FIG. 6, the output Q of the D flip-flop 13, that is, the signal WR2 is stabilized at the logic "high" level, while in FIG. 7, it is stabilized at the logic "low" level. FIGS. 6 and 7 both show that data signal D2 is successfully sampled. If the data signal D2 is not sampled on the first clock edge, it will be sampled on the second clock edge.

Next, the function of the receiving circuit 2 will be described with reference to FIG. The output data signal D2S from the synchronization circuit 7 is
It may fluctuate within one period of the local clock signal CLK2H. FIFO buffer 8 compensates for this variation. The digital device connected to the receiving circuit 2
It operates at half the clock speed of the O buffer 8. D flip-flop 9 and AND gate 1
0 indicates that the read signal RDIN is 1 of the clock signal CLK2.
When logic high during the period, reading of only one data word is guaranteed.

The asynchronous digital communication device of the present invention is independent of the interconnect delay between the transmitting and receiving circuits. By using the NRZ write signal in parallel with the data signal, a simple synchronization circuit can be obtained. Also, the asynchronous digital communication device of the present invention can be implemented using currently available chip design tools and standard synchronous logic elements.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a block diagram illustrating details of a synchronization circuit in FIG. 1;

FIG. 3 is a timing chart for explaining the operation of the asynchronous digital communication device of FIG. 1;

FIG. 4 is a timing chart illustrating the operation of the transmission circuit of FIG. 1;

FIG. 5 is a state transition diagram for explaining the operation of the synchronization circuit of FIG. 2;

FIG. 6 is a timing chart illustrating the operation of the synchronization circuit of FIG. 2;

FIG. 7 is a timing chart for explaining the operation of FIG. 2;

FIG. 8 is a timing chart illustrating the operation of the receiving circuit of FIG. 1;

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 transmission circuit 2 reception circuit 3 n-bit width input register 4 toggle flip-flop 5 negative edge trigger register 6, 9, 12, 13, 16 D flip-flop 7 synchronization circuit 8 FIFO buffer 10 2-input AND gate 11 2-input AND gate 14 2-input EXOR gate 15 n-bit width input register 17, 18, 19 Cable

Claims (2)

(57) [Claims] 1. An asynchronous digital communication device that performs asynchronous transfer of data between a transmission circuit and a reception circuit that operate on independent clocks, wherein the transmission circuit generates an NRZ write signal;
Means for generating transmission data in which input data is relatively delayed as compared with the NRZ write signal, means for synchronizing a BAF signal from the reception circuit with a local clock of the transmission circuit, and using the BAF signal. Means for stopping the asynchronous transfer, wherein the receiving circuit synchronizes the NRZ write signal with a local clock of the receiving circuit, and
Using a write signal, synchronizing means for latching the transmission data and generating a write signal, storing the transmission data latched by the write signal, and when the stored data exceeds a certain amount, An asynchronous digital communication device comprising: a FIFO buffer that outputs a BAF signal. 2. The method of claim 1, wherein the synchronization of the NRZ write signal is performed at twice the clock rate of the data bit rate, and the synchronization further converts the NRZ write signal into a synchronous strobe signal. An asynchronous digital communication device as described.