JP2008041106A - Semiconductor integrated circuit device, clock control method and data transfer control method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a function for attaining signal synchronization between modules which operate by clocks of non-integer multiples by a simple method in a semiconductor integrated circuit device. <P>SOLUTION: The semiconductor integrated circuit device has a first internal module, a second internal module which transfers data with the first internal module via an internal bus, a clock generating section which generates a first reference clock to be supplied to the first internal module and generates a clock synchronizing signal indicating an effective position of a clock edge of a second reference clock corresponding to positions of clock edges of the second reference clock and the first reference clock to be supplied to the second internal module, wherein the first internal module transfers the data according to the clock edge of the first reference clock and the second internal module transfers the data according to the effective clock edge based on the second reference clock and the clock synchronizing signal. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit device and a clock control method for reducing power consumption of internal modules connected to a bus. More particularly, the present invention relates to a semiconductor integrated circuit device and a clock control method for controlling the operating frequency of an internal module and an internal bus by controlling a clock and a clock synchronization signal to reduce power consumption.

  In recent years, with the increase in speed and scale of semiconductor processors, how to reduce the power consumption of the processors has become a major issue. In order to reduce the power consumption of the semiconductor integrated circuit device, 1) a method of dynamically lowering the clock frequency when high-speed operation of the processor is unnecessary, and 2) a clock having an operation frequency required for each module in the processor. 3) A method of stopping the clock of a module that does not require operation (controlled by a register or the like), 4) A method of reducing the power of the clock tree by using a gated clock, and the like have been used. .

  Here, the main power consumption factor P of the semiconductor processor can be expressed by the following equation.

P = C × V ^ 2 × F (C: load capacity, V: power supply voltage, F: operating frequency)
The above-described method is a method for reducing power by paying attention to the operating frequency F (or the switching probability of the load capacity) in this equation. Many methods for reducing power consumption by controlling the power supply voltage V have been implemented, but in recent years, a method for controlling clock supply to peripheral modules that are not mainly required to operate has attracted attention. .

  On the other hand, as a conventional technique related to the present invention, Japanese Patent Application Laid-Open No. 2002-328744 discloses an apparatus for preventing a loss of synchronization of data transfer between modules when the clock frequency is switched.

  Japanese Patent Laying-Open No. 2003-58271 discloses an apparatus and method for avoiding the occurrence of hang-up when switching the clock frequency or when shifting to the power-down mode.

  Japanese Patent Laid-Open No. 6-202754 discloses an apparatus and method for powering down a functional unit (module) of an integrated circuit. The status of each module is monitored, and when it is not necessary, the clock input to that module is stopped.

  Japanese Patent Application Laid-Open No. 8-194663 discloses a method for enabling or disabling clock line characteristics for a computer system and a peripheral bus. A command register for clock control is provided to perform clock control such as stopping the clock supply to modules that do not require operation.

Japanese Laid-Open Patent Publication No. 2000-35886 discloses that signal synchronization between clocks is performed using a latch when performing signal transfer between modules operating when the corresponding clock ratio is not an integral multiple. ing.
JP 2002-328744 A JP 2003-58271 A JP-A-6-202754 JP-A-8-194663 JP 2000-35886 A

  With recent progress in system LSI development, system-on-chip (SOC) development in which a large number of function IP macros (functional units for realizing specific functions) are mounted on one chip has become possible. Yes. As the circuit scale increases, the power consumption increases accordingly, and how to reduce power consumption is a major issue.

  Such a system-on-chip (SOC) typically has an internal module with a number of functional IP macros. Conventionally, as a countermeasure against power consumption, a register or the like indicating whether or not each module is operable (activated state) is provided. When the module is inoperable / unnecessary (inactive state), the module A method of stopping the clock supply to has been taken.

  However, in such a conventional method, once the clock supply of a specific module is turned ON, the clock to that module is not related to the presence or absence of bus access to that module or the operating state of the module itself. Continue to be supplied. Nearly 10 to 30% of the power consumption of the semiconductor chip (this value depends on the circuit configuration of the chip) is consumed by the clock tree (a group of buffers inserted in a tree shape for clock skew adjustment). Therefore, it is desirable to stop or suppress redundant clock supply when the macro IP is not operating.

  In other words, even if unnecessary signal transitions such as a data bus and an arithmetic unit are suppressed by a gated clock or the like, useless power is continuously consumed in the clock tree. If a gated clock or the like is not used, the useless power is consumed remarkably. It is desired to reduce the power consumption of the chip by reducing this extra power consumption.

  Furthermore, in general, in a semiconductor processor having various internal modules such as a CPU core, SDRAM controller, peripheral bus controller, and timer, a specific internal module always requires a certain processing capability, and the CPU is required to operate at high speed. . In such a semiconductor processor, the minimum clock frequency required for application processing is supplied, and the maximum performance is demanded depending on conditions such as process performance (manufacturing variation), power supply voltage, temperature, etc. In order to satisfy the above, there is a case where it is desired to control the clock ratio of the clock frequency between the CPU core unit and a specific internal module by a non-integer multiple, for example, 0.5.

  In response to such a request, when a clock generation unit in the processor generates a plurality of clocks having a clock ratio having a frequency that is a non-integer multiple, and supplies them to each internal module including the CPU core unit, the clock edge of each clock Has a problem that the signal synchronization circuit section between modules must operate at a frequency twice that of the earlier clock.

  The existence of such a circuit that operates at high speed becomes a major problem in logic design, layout, timing verification, and the like in LSI development.

  The present invention has been made in view of the above points, and in the semiconductor integrated circuit device and the clock control method, provides a function for realizing signal synchronization between modules operating with a non-integer multiple clock by a simple method. The purpose is to do.

  In order to solve the above problems, a semiconductor integrated circuit device of the present invention includes an internal bus, a first internal module having a first module body connected to the internal bus and realizing a predetermined function, and the internal bus. And a second module main body that realizes a predetermined function, generates a first reference clock, and a second internal module that transfers data via the first internal module and the internal bus And supplying the second internal clock to the first internal module and indicating a clock edge position of the second reference clock corresponding to the clock edge position of the second reference clock and the first reference clock. A clock generation unit that generates a signal and supplies the signal to the second internal module, wherein the first internal module The first module body performs predetermined processing according to the first reference clock, and performs data transfer according to the clock edge of the first reference clock. The second internal module is connected to the second module body. A predetermined process is performed according to the second reference clock, and data transfer is performed according to the valid clock edge based on the second reference clock and the clock synchronization signal.

  Furthermore, in order to solve the above-described problem, a semiconductor integrated circuit device according to the present invention includes an internal bus, a first internal module having a first module body connected to the internal bus and realizing a predetermined function, A second internal module connected to an internal bus and having a second module body for realizing a predetermined function, and transferring data via the first internal module and the internal bus; and a first reference clock And a first clock synchronization signal indicating a position of a valid clock edge of the first reference clock is generated and supplied to the first internal module, and the second reference clock and the second reference clock A semiconductor integrated circuit device comprising: a clock generation unit that generates a second clock synchronization signal indicating a position of a valid clock edge and supplies the second clock synchronization signal to the second internal module The first internal module executes a predetermined process in the first module body in accordance with the first reference clock, and based on the first reference clock and the first clock synchronization signal. Data transfer is performed according to a clock edge of the first reference clock, and the second internal module executes a predetermined process according to the second reference clock in the second module body, and the second reference clock Data transfer is performed according to a valid clock edge of the second reference clock based on the clock and the second clock synchronization signal.

  According to the semiconductor integrated circuit device described above, even when the corresponding clock ratio is not an integral multiple, it is possible to operate at a desired operating frequency without very high-speed signal transfer between modules operating with each clock. can do.

  According to the semiconductor integrated circuit device and the clock control method of the present invention, it is possible to reduce power consumption in the clock tree and redundant power consumption in the modules connected to the clock tree. This is effective in reducing power consumption in a semiconductor integrated circuit device such as a system-on-chip having an internal module equipped with a plurality of function IP macros. In addition, according to the clock synchronization control system of the present invention, even when the clock ratio of the corresponding high-speed clock and low-speed clock is not an integer multiple, very high-speed signal transfer can be performed between modules operating with each clock. Instead, the processor can be operated at a desired operating frequency.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 shows a basic processor configuration in one embodiment of the present invention.

  In FIG. 1, 1 is an external input clock, 2 is an external input terminal signal for performing clock control, 3 is a PLL (phase-locked loop) circuit for generating an input clock to the clock generator in this embodiment, In the present embodiment, a clock generation unit, 4a is a frequency dividing circuit in the clock generation unit 4, 5 is a CPU core in the present embodiment, 5a is a bus interface (BI) in the CPU core 5, and 6 is an internal module in the present embodiment. , 6a is a bus interface (BI) in the internal module 6, 7 is an internal module in this embodiment, 7a is a bus interface (BI) in the internal module 7, 8 is a clock control register in the internal module 7, and 9 is a book The internal on-chip bus (OCB) 10 in the embodiment is supplied to the CPU core 5 in the present embodiment. Is a high-speed reference clock (bus clock), 11 is a clock synchronization signal corresponding to the reference clock 10 supplied to the CPU core 5 in this embodiment, and 12 is a low-speed supplied to the internal modules 6 and 7 in this embodiment. , 13 is a clock synchronization signal supplied to the internal modules 6 and 7 in this embodiment, 14 is a clock control signal according to a program command from the CPU core 5 to the clock generator 4 in this embodiment, and 15 is this embodiment. The clock control signals from the clock control register 8 of the example to the clock generation unit 4 are shown respectively.

  The semiconductor integrated circuit device according to this embodiment is applied to the processor of FIG. The processor of FIG. 1 includes a PLL circuit 3, a clock generation unit 4, a CPU core 5, an internal module 6, an internal module 7, and an internal on-chip bus (OCB) 9. The semiconductor integrated circuit device of this embodiment includes a clock generation unit 4, internal modules 6 and 7, and an internal on-chip bus 8.

  The PLL circuit 3 receives the external input clock 1 and outputs a PLL output signal synchronized with the external input clock 1 to the clock generation unit 4.

  The clock generation unit 4 receives the external input terminal signal 2 through the external input terminal and also receives the PLL output signal from the PLL circuit 3. The clock generation unit 4 receives the clock control signal 14 sent from the CPU core 5 and uses it for clock synchronization control. The clock generator 4 receives a clock control signal 15 sent from a clock control register 8 provided in the internal module 7 and uses it for clock synchronization control.

  The CPU core 5, the internal module 6, and the internal module 7 are connected to the on-chip bus 9 via the bus interface 5a, the bus interface 6a, and the bus interface 7a, respectively. In the CPU core 5 and the internal modules 6 and 7, an internal clock having a clock frequency suitable for internal operation is generated based on the supplied reference clock and clock synchronization signal.

  FIG. 2 is a waveform diagram for explaining a reference clock and a clock synchronization signal in one embodiment of the present invention.

  2, (1) is a reference clock in this embodiment, (2) is a clock synchronization signal in this embodiment, and (3) is a gated clock generated using the reference clock and the clock synchronization signal in this embodiment. (Internal clock) is shown respectively.

  As shown in FIG. 2, the gated clock (internal clock) (3) of the present invention has a rising edge (an edge changing from LOW to HIGH) among a plurality of pulses of the reference clock (1). The signal (2) is generated by controlling so that only a pulse in a period in which the signal (2) is at a HIGH level is passed. An internal clock having a frequency lower than that of the reference clock is generated, and the frequency of the internal clock is changed by changing the cycle and duty ratio of the clock synchronization signal (2).

  FIG. 3 shows an internal module of a semiconductor integrated circuit device according to an embodiment of the present invention.

  In FIG. 3, 31 is an internal module connected to an on-chip bus having a specific function, 32 is a synchronous control module for generating an internal clock in the internal module 31, and 33 is for realizing a specific function in the internal module 31. The module body 34, the control state machine 34 in the module body 33, the internal on-chip bus 9, the reference clock 16, the clock synchronization signal 17, the interrupt request to the internal module 31, a DMA (direct memory access) request, etc. , 19 is a bus request signal defined by the bus protocol of the on-chip bus 9, 20 is a bus acknowledge signal defined by the bus protocol of the on-chip bus 9, and 21 is a reference clock by the synchronization control module 32. Live using clock synchronization signal The generated gated clock (internal clock), 22 is a clock control signal notified from the control state machine 34 of the module body 33 to the synchronous control module 32 (for example, a signal indicating that the control state is the IDLE state), and 32a is A logic circuit for generating a gated clock in the synchronization control module 32, 32b is a control state machine in the synchronization control module 32, 37 is output from the control state machine 32b, and controls input of the clock synchronization signal 17 to the logic circuit 32a. Each of the internal clock control signals is shown.

  The synchronization control module 32 generates the internal clock 21 based on the reference clock 16, the clock synchronization signal 17, and the internal clock control signal 37, and outputs it from the logic circuit 32a. The module main body 33 executes predetermined processing according to the internal clock 21 output from the synchronization control module 32. Details of the synchronization control module 32 will be described later.

  Returning to FIG. 1, the clock generation unit 4 generates a specific reference clock 10 (for example, a bus clock) and a plurality of low-speed clocks 12 (for example, a supply clock to the internal module), and at the same time, each low-speed reference clock 12. In order to achieve clock synchronization with each other, each clock synchronization signal 13 generated at a predetermined cycle of the reference clock is generated and supplied to each internal module in each processor. One set or a plurality of sets of clock synchronization signals corresponding to the reference clock may be present.

  The clock synchronization signal 13 may be asserted immediately before a necessary clock edge, or may be one cycle before the reference clock.

  In the semiconductor integrated circuit device of the present invention, the reference clocks 10 and 12 and the clock synchronization signals 11 and 13 change clocks in the transfer control circuit between the clocks (for example, a bus interface or a bus bridge in each internal module). Synchronous control between signals generated with a frequency clock is performed.

  The semiconductor integrated circuit device according to the present invention includes a synchronization control module for generating an internal clock in each internal module that receives a reference clock and a clock synchronization signal in the configuration of a processor having a clock generation unit 4 as shown in FIG. Or a SYNC module).

  The semiconductor integrated circuit device of the present invention has a control mechanism for performing control related to variation in the clock frequency ratio of the reference clock supplied to each internal module and ON / OFF of clock supply to each internal module. Specifically, control is performed by an external terminal of the LSI, an internal clock control register, or an instruction in the instruction set of the processor.

  The clock generator in the processor includes a mechanism (see Patent Document 2) for selectively stopping each reference clock and the clock synchronization signal or changing the clock frequency, and various modules prior to clock control. You may provide the function (refer patent document 1) which performs handshake control.

  In a semiconductor integrated circuit device according to an embodiment of the present invention, a synchronization control module is provided in each internal module connected to a bus, and an internal clock in each internal module is generated by the synchronization control module. The synchronization control module has a function of stopping the internal clock supply or a function of decelerating the internal clock supply. Here, each internal module connected to the bus includes both a bus master and a bus slave.

  First, a method for stopping the internal clock when there is no bus access will be described. FIG. 4 shows a configuration example of the synchronization control module according to the embodiment of the present invention shown in FIG.

  In FIG. 4, 41 is a reference clock, 42 is a clock synchronization signal, 43 is an internal clock control signal generated in the synchronization control module 32, 44 is an AND element for masking the clock synchronization signal 42 with the clock control signal 43, 45 is a latch cell, 46 is an AND element for generating a gated clock, and 47 is a generated gated clock.

  FIG. 5 is a waveform diagram for explaining the operation of the synchronization control module of FIG.

  5, (1) is the reference clock 41 (bus clock) in FIG. 4, (2) is the clock synchronization signal 42 in FIG. 4 (in this case, it is set to HIGH level indicating the fastest clock), ( 3) is a bus request signal (bus_req), (4) is an address phase signal in the pipeline bus, and (5) is a signal (read / write) indicating whether the transfer on the bus is a read or a write. ), (6) is a bus acknowledge signal (bus_ack), (7) is read data (read_data) returned to the bus, (8) is a request signal such as an interrupt request or DMA request in the synchronization control module 32, and the module body 33 Clock control signal, bus request signal, and bus acknowledge signal from the control state machine 34 Shows the internal clock control signal is generated based on whether the deviation, (9) a reference clock, a clock synchronization signal and a gated clock generated by the internal clock control signal, respectively.

  With the circuit configuration shown in FIGS. 3 and 4, a synchronization control module for generating an internal clock is provided in an internal module connected to the bus, and a reference clock (bus clock) and a clock supplied from the clock generator 4 are provided. From the synchronization signal and the internal clock control signal generated in the internal module, the internal clock in the module is generated by the synchronization control module.

  That is, as shown in FIG. 5, the supply / stop of the internal clock is controlled by controlling the supply / stop of the clock synchronization signal to the gated clock generator by the internal clock control signal. In FIG. 5, the HIGH level is set to indicate that the frequency is the same as that of the reference clock. However, as shown in FIG. 2, the period of the clock synchronization signal is set to a predetermined multiple of the reference clock, and the duty ratio is set. By setting appropriately, the frequency of the internal clock can be set to a predetermined value lower than that of the reference clock.

  A period during which the internal module needs to operate normally in the control state machine 32b in the synchronous control module 32 by a bus request signal for notifying the occurrence of bus transfer, an external interrupt request signal, a DMA (direct memory access) request signal, or the like. The internal clock control signal is masked by negating the internal clock control signal during periods when normal operation is not required to stop the supply of the internal clock, and the internal clock control signal is asserted during periods when normal operation is required Then, an internal clock is generated by supplying the clock synchronization signal to the clock generation gated clock unit without masking the clock synchronization signal.

  Regarding the determination of the period for which normal operation is required in the synchronous control module, the timing for starting the supply of the internal clock, that is, the timing for asserting the internal clock control signal, relates to the timing at which a bus request occurs or some interrupt factor such as an external interrupt. The timing at which the signal is asserted may be used.

  Some consideration is necessary for the timing of stopping the supply of the internal clock, that is, the timing of negating the internal clock control signal. Specifically, if the clock supply module is a simple register file or the like, the subsequent clock supply may be stopped at the timing when the end of bus transfer is detected by the bus acknowledge signal indicating the end of bus access. it can.

  However, in a module that needs to continue to operate for a certain period after the bus access is completed, the clock stop timing cannot be determined only by the bus acknowledge signal. Therefore, in the synchronous control module that generates the internal clock of the module that needs to be supplied for a certain period of time after the bus access is completed, the internal operating state of the module is monitored by a specific signal, and the clock is supplied until the operation is completed It is necessary to

  In the example of FIG. 5, the internal clock control signal is asserted in response to the rising edge of the bus request signal bus_req, and the internal clock control signal is negated in response to the falling edge of the bus acknowledge signal bus_ack.

  As a signal for monitoring the internal state, for example, a signal indicating an IDLE state (for example, a control state machine 34 in the module main body 33) sent from a control state machine that controls internal operations of the internal module 31 (for example, A clock control signal 22) or the like is used.

  Next, an example of the internal clock deceleration method when there is no bus access will be described. FIG. 6 shows a configuration example of a synchronization control module according to an embodiment of the present invention.

  In FIG. 6, 61 is a reference clock, 63 is an internal clock control signal generated in the synchronization control module 32, and 64 is further masked with the clock control signal 63 when the internal clock is unnecessary. AND element 65, latch cell 66, AND element 66 for generating an internal gated clock, 67 generated gated clock, 62-1 a clock synchronization signal (sync1) indicating a specific speed, 62- 2 is a clock synchronization signal (sync2) indicating a specific speed, 62-3 is a clock synchronization signal (sync3) indicating a specific speed, 68 is a selection circuit, 69 is a different speed generated by the synchronization control module 32. A selection signal for selecting one of the clock synchronization signals 62-1 to 62-3 shown in FIG. It is.

  The clock deceleration method of the embodiment of FIG. 6 is realized by selecting a plurality of clock synchronization signals by the selection circuit 68 based on the selection signal 69. A reference clock 61 and a plurality of clock synchronization signals 62-1 to 62-3 indicating a plurality of clock frequencies are supplied from the clock generation unit 4 in the processor to generate an internal clock of the internal module to be supplied with the clock. In the synchronization control module 32, the clock synchronization signal corresponding to the clock frequency suitable for the operation of the internal module is selected, and the operation of the internal module is performed based on the selected clock synchronization signal, the internal clock control signal, and the reference clock. Generate an internal clock with a suitable frequency. The selection signal 69 is supplied from, for example, the clock generation unit 4.

  With respect to the timing for starting the clock supply and the timing for stopping the clock supply in the method of this embodiment, the same method as that described with reference to FIGS. 4 and 5 can be used.

  One variation of the clock synchronization signal to be selected in the synchronization control module includes selecting a LOW clip signal indicating a clock stop or the like.

  Next, another example of the in-module clock speed reduction method when there is no bus access will be described. FIG. 7 shows a synchronization control module according to an embodiment of the present invention.

  In FIG. 7, 71 is a reference clock, 72 is a clock synchronization signal, 73 is an internal clock control signal generated in the synchronization control module 32, and 74 is a mask generated by the counter 78 when the internal clock is not required. An AND element for further masking with a signal, 75 is a latch cell, 76 is an AND element for generating an internal gated clock, 77 is a generated gated clock, and 78 is a mask for slowing (or stopping) the clock. Each counter that generates a signal is shown.

  The clock decelerating method of the embodiment of FIG. 7 is realized by thinning out the clock synchronization signal for generating the internal clock by the mask signal generated by the counter 78.

  That is, the reference clock 71 and the clock synchronization signal 72 corresponding to the maximum speed of the internal module are supplied from the clock generator 4 inside the processor to the internal module to be supplied with the clock. When the synchronization control module 32 in each internal module determines that the internal module does not require any operation, the AND element 74 masks the clock synchronization signal 72 by outputting a mask signal with a fixed LOW level from the counter 78. Then, the internal clock is stopped, or a mask signal having a constant period and duty ratio is output from the counter 78, so that the AND clock 74 decimates the clock synchronization signal 72 at a constant rate to decelerate the internal clock. . The clock deceleration method of this embodiment is effective for reducing the power consumption of the semiconductor integrated circuit device.

  In the clock decelerating method of this embodiment, as a method of thinning out the clock synchronization signal, it is effective to mask the clock synchronization signal 72 with a constant period and a constant cycle with the output signal of the counter 78.

  The counter 78 operates based on the internal clock control signal 73 and the reference clock 71. An example of the operation of the counter 78 will be described below. The internal clock control signal 73 functions as an enable signal for the counter 78. The counter 78 includes an up counter or a down counter, and performs a counting operation in response to the reference clock 71.

  When the counter 78 is in an enabled state (internal clock control signal 73 is HIGH level), the counter 78 compares the current count value with a preset reference value, and outputs a HIGH level or LOW level signal according to the comparison result. Thus, a signal having a constant period and a duty ratio is output as a mask signal. Here, the period and the duty ratio of the mask signal can be changed by changing the internal setting of the counter 78 (reference value or count upper limit value). Further, when the counter 78 is in a disabled state (the internal clock control signal 73 is LOW level), the counter 78 outputs a signal having a fixed LOW level as a mask signal.

  In addition, as a variation of the clock synchronization signal in the synchronization control module 32, selecting a LOW clip signal or the like indicating a clock stop is also included.

  Next, still another example of the internal clock deceleration method when there is no bus access will be described. FIG. 8 shows a configuration example of a synchronization control module according to still another embodiment of the present invention.

  In FIG. 8, 81 is a reference clock, 82 is a clock synchronization signal (here, a low-speed synchronization signal), 83 is an internal clock control signal generated in the synchronization control module 32, and 84 is a high-speed clock synchronization signal. An OR element for masking and generating a high-speed internal clock, 85 is a latch cell, 86 is an AND element for generating an internal gated clock, and 87 is a generated gated clock.

  In the clock decelerating method of this embodiment, when not operating (default), a low-speed internal clock is generated using a low-speed clock synchronization signal, and during operation, a high-speed internal clock is generated using a HIGH mask signal. Realize.

  A reference clock 81 and a low-speed clock synchronization signal 82 are supplied from the clock generator 4 in the processor to the internal module to be supplied with the clock. In the synchronous control module 32 in each module, the internal clock control signal is fixed at the LOW level during a period when the module does not require an operation. As a result, a low-speed internal clock is generated based on the low-speed clock synchronization signal as it is, thereby decelerating the internal clock and reducing power consumption. Alternatively, in the synchronization control module 32, the low-speed clock synchronization signal is LOW masked by a logic element (not shown) to stop the internal clock and reduce power consumption.

  When the internal module requires normal operation, the synchronization control module 32 outputs the reference clock 81 as it is by masking the clock synchronization signal HIGH by fixing the internal clock control signal to HIGH level. Fast internal clock.

  Further, by masking the clock synchronization signal (taking a logical OR) so that a higher period (clock ACTIVE period) than that of the low-speed clock synchronization signal can be obtained by a counter or the like, a faster internal clock can be obtained in the internal module. Can be generated.

  For example, in FIG. 8, when the gated clock output consisting of the next clock edge of the reference clock is obtained when the clock synchronization signal is HIGH, the above clock synchronization signal is masked by the internal clock control signal. By taking the logical OR of the clock synchronization signal supplied from the block and the mask signal (internal clock control signal), the internal clock generation control signal (for the gated clock buffer that generates the internal clock) for generating the required clock frequency Enable signal).

  For the clock supply start timing and the clock supply stop timing in the clock deceleration method of this embodiment, the same method as that described in FIGS. 4 and 5 may be used.

  Next, a supply clock generation circuit (synchronous control module) for each internal module is provided on the bus, and a clock is sent only to the relevant bus master and bus slave when there is a bus transfer request, or to the bus slave only. A method of supplying will be described.

  First, a method applied to a general pipeline bus will be described. FIG. 9 shows a synchronization control method according to an embodiment of the present invention.

  In FIG. 9, 91-1 is the bus master (master_1) in this embodiment, 91-2 is the bus master (master_2), 91-3 is the bus master (master_3), and 94 has a specific bus protocol. A bus unit, 95 is a bus control unit in the bus unit 94, 96 is a selection circuit for selecting and outputting any one of the data signals from the bus masters 91-1 to 91-3, 97-1. Is a bus slave (slave_1), 97-2 is a bus slave (slave_2), 97-3 is a bus slave (slave_3), 98 is a data signal for each bus slave selected by the selection circuit 96, 92- 1 is a data signal from the bus master 91-1 to the bus unit 94, and 92-2 is a bus unit 94 from the bus master 91-2. , 92-3 is a data signal from the bus master 91-3 to the bus unit 94, 93-1 is an internal clock for the bus slave 97-1 generated by the bus controller 95, 93-2 Indicates an internal clock for the bus slave 97-2 generated by the bus control unit 95, and 93-3 indicates an internal clock for the bus slave 97-3 generated by the bus control unit 95.

  In particular, there is no need to limit the bus protocol, and the bus protocol includes a plurality of bus masters and a plurality of bus slaves. In the bus control unit 95, arbitration of which bus master is permitted to transfer and transfer to which bus slave. This can be applied to a general pipeline bus that transfers data between a corresponding bus master and a bus slave. The bus control unit 95 controls the selection circuit 96 to select the data signal from the bus master involved in the data transfer of the bus from the data signals output from the bus masters 91-1 to 91-3. Output to bus slaves 97-1 to 97-3.

  In this embodiment, a synchronization control module corresponding to each internal module is provided in the bus control unit 95 in the bus unit 94. Each synchronization control module is supplied with a reference clock and a clock synchronization signal from a clock generator (not shown). In the synchronous control module, an internal clock for each internal module connected to the bus is selectively generated. Here, selectively generating means that only the clocks of the bus master and the bus slave involved in bus transfer are generated. The clock to the modules (bus master / slave) not involved in bus transfer is stopped / decelerated, thereby reducing the power consumption of the entire module block connected to the bus.

  The specific clock generation means in the synchronization control module for generating the internal clock may be the same as that in the above embodiment.

  In addition, the clock supply start timing and the clock supply stop timing in this method are the same as in the above embodiment.

  Next, a method applied to the crossbar bus will be described. FIG. 10 shows a synchronization control method according to an embodiment of the present invention.

  In FIG. 10, 91-1 is a bus master (master_1) in this embodiment, 92-1 is a data signal sent from the bus master 91-1, 91-2 is a bus master (master_2), 92-2. Is a data signal sent from the bus master 91-2, 91-3 is a bus master (master_3), 92-3 is a data signal sent from the bus master 91-3, and 94A is a specific bus protocol. A bus unit 97-1 is a bus slave (slave_1), 97-2 is a bus slave (slave_2), 97-3 is a bus slave (slave_3), 95-1 is a bus unit in the bus unit 94A. The interface unit (M1i / f) 95-2 with the master 91-1 is connected to the bus master 91-2 in the bus unit 94A. An interface unit (M2i / f), 95-3 is an interface unit (M3i / f) with the bus master 91-3 in the bus unit 94A, and 96-1 is a bus slave 97-1 in the bus unit 94A. Interface unit (S1i / f), 93-1 is an internal clock from the interface unit 96-1 to the bus slave 97-1, and 96-2 is an interface with the bus slave 97-2 in the bus unit 94A. Section (S2i / f), 93-2 is an internal clock from the interface section 96-2 to the bus slave 97-2, and 96-3 is an interface section (S3i with the bus slave 97-3 in the bus unit 94A). / F) and 93-3 indicate internal clocks from the interface unit 96-3 to the bus slave 97-3.

  In FIG. 10, there is no particular limitation on the bus protocol, and each bus master can independently access a desired bus slave via a bus matrix in a so-called crossbar bus. is there. An interface unit for each bus master or each bus slave is provided in the bus unit 94A.

  When transfer from a plurality of bus masters 91-1 to 91-3 to one bus slave competes in the interface units 96-1 to 96-3 of each bus slave or the bus matrix arbitration circuit provided in the bus unit 94A, Arbitration is performed to determine which bus master should preferentially process the transfer from. In the bus unit 94A, based on control of a bus control unit (not shown), interface units corresponding to a bus master and a bus slave involved in bus data transfer are connected to each other.

  In the clock synchronization control system of the embodiment of FIG. 10, each of the master interface units 95-1 to 95-3, slave interface units 96-1 to 96-3, etc., connected to the bus unit that processes the bus transfer. A synchronization control module for generating an internal clock of the module is provided. Depending on the presence / absence of bus transfer or the like, the synchronous control module corresponding to the bus master and bus slave requiring clock supply selectively generates and supplies the clock. Each synchronization control module is supplied with a reference clock and a clock synchronization signal from a clock generator (not shown).

  FIG. 11 shows a synchronization control module provided in each of the slave interface units 96-1 to 96-3 in the bus unit 94A of FIG.

  In FIG. 11, 101 is a reference clock, 102 is a clock synchronization signal, 104 is a logical OR of the clock synchronization signal 102 and request signals 103-1 to 103-3 from the bus masters 92-1 to 92-3, and an internal gated clock. OR element for generating an internal clock generation control signal for generation, 105 is a latch cell, 106 is an AND element for generating an internal gated clock, 107 is a generated internal gated clock, 103-1 is a bus master 91 -1 is a request signal generated by the interface unit 95-1, 102-2 is a request signal generated by the interface unit 95-2 of the bus master 91-2, and 103-3 is an interface of the bus master 91-3. Each of the request signals generated by the unit 95-3 is shown.

  In the example of FIG. 11, when any one or more of the transfer request request signals 103-1 to 103-3 (for convenience, req_1 to req_n) from each bus master are HIGH, the output of the OR element 104 is active. It becomes. An internal clock generation control signal (referred to as clk_sync for convenience) for generating an internal clock of each module in each synchronization control module can be expressed by the following equation.

clk_sync = req_1 + req_2 + ... + req_n
In the above formula, “+” indicates a logical OR. The gated clock (module_clk) to each module can be expressed as:

module_clk = (clk_sync * cnt) & reference clock where “cnt” indicates various clock control factors. For example, the period during which the target module needs clock supply in each synchronization control module is shown. “&” Indicates a logical AND. “*” Means that an arbitrary logic is taken as necessary.

  In FIG. 11, when a bus transfer is requested between any one of the bus masters 91-1 to 91-3 and the corresponding bus slave, and any one of the request signals 103-1 to 103-3 becomes HIGH, an internal clock is generated. The control signal is fixed to HIGH level. Accordingly, the reference clock 101 is output from the AND element 106 as it is as an internal clock of each module.

  On the other hand, when none of the bus masters 91-1 to 91-3 has a bus transfer request and all the request signals 103-1 to 103-3 are LOW, the clock synchronization signal 102 is output as an internal clock generation control signal. Thereby, the internal clock of each module becomes a signal obtained by decelerating the reference clock 101 according to the clock synchronization signal 102.

  As a specific clock generation means in the synchronization control module for generating the internal clock of each module, the configuration shown in FIG. 11 may be used, or the same configuration as that of the above embodiment may be used.

  Further, the clock supply start timing and the clock supply stop timing in this method are the same as those in the above embodiment.

  Next, a method of stopping / decelerating when the bus clock itself serving as a reference clock for the bus interface unit does not have bus access will be described.

  From a clock generation unit inside the processor, a bus clock serving as a specific reference clock and a specific clock synchronization signal corresponding to the bus clock are supplied. In the bus unit, a synchronization control module for generating the internal clock of each module and a synchronization control module for generating the clock of the bus interface unit itself are provided. In each synchronization control module, the reference clock and the clock synchronization signal are provided. Each module generates the necessary clock.

  The bus access request is notified to the clock generation unit in the processor, and the clock generation unit starts, stops, decelerates, etc. the bus clock in response to the bus access request.

  The clock generation unit always supplies a low-speed clock synchronization signal or a clock synchronization signal indicating a stopped state. When a bus access occurs, each synchronization control module supplies the internal clock of the related module during bus transfer by simultaneously masking the clock synchronization signal that generates the internal clock of each bus master and bus slave involved in the bus access. To do.

  In each of the above embodiments, the above-described clock supply method may be applied to the bus clock itself serving as the reference clock. That is, a clock synchronization control system is realized using a two-stage synchronization control module.

  In addition, the clock of a specific module has a control means for indicating that the clock is continuously supplied, for example, a module / clock supply control register, an external terminal, etc., and according to an instruction from the control means, In each of the clock generation synchronous control modules, control for continuously supplying the clock at the highest speed, control for continuing to supply the clock at a constant operating frequency although not at the maximum speed, and the like may be performed.

  FIG. 12 shows an internal module of a semiconductor integrated circuit device according to an embodiment of the present invention.

  In FIG. 12, 31A is an internal module connected to the on-chip bus 9 having a specific function in this embodiment, 32A is a synchronization control module for generating an internal clock in the internal module 31A, and 33 is an internal module 31A. A module body for realizing a specific function, 34 is a control state machine in the module body 33, 35 is a bus interface unit in the internal module 31A, 36 is a control state machine in the bus interface unit 35, 16 is a reference clock, 17 Is a clock synchronization signal, 18 is a request signal such as an interrupt request or DMA request for the internal module 31A, 19 is a bus request signal defined by the bus protocol of the on-chip bus 9, and 20 is a bus protocol of the on-chip bus 9. Defined bus acknowledge The signal 21-1 is an internal clock for the module body 33 among the gated clocks generated by the logic circuit 32 a-1 of the clock generation synchronization control module 32 A using the reference clock and the clock synchronization signal, and 21-2 is the clock. Of the gated clocks generated by the logic circuit 32a-2 of the generation synchronization control module 32A using the reference clock and the clock synchronization signal, an internal clock for the bus interface unit 35, 22-1 is a control state machine of the module body 33. 34 is a clock control signal (for example, a signal indicating that the control state machine 34 is in the IDLE state) notified from the control state machine 36 of the bus interface unit 35 to the synchronization control module 32A. Clock control signal to be notified 37 is output from the control state machine 32b, respectively an internal clock control signal for controlling the inputs to the logic circuit 32a-1,32a-2 of the clock synchronization signal 17. However, when the bus request signal 19 and the bus acknowledge signal 20 are sufficient, the clock control signals 22-1 and 22-2 are unnecessary.

  In the internal module 31A of the semiconductor integrated circuit device according to the present embodiment, the internal clock is divided between the bus interface unit 35 in the internal module 31A connected to the bus and the other modules in the internal module 31A, and is generated by the synchronization control module 32A. Only the internal clock of the bus interface unit 35 controls the clock supply according to a predetermined request (bus request, interrupt factor, etc.). For a module that does not need to operate in the internal module 31A, the corresponding internal clock is stopped / decelerated.

  According to the semiconductor integrated circuit device and the clock control method of the above-described embodiments, power consumption in the clock tree when no operation is required and redundant power consumption in the modules connected to the clock tree are reduced. It becomes possible. This is effective in reducing power consumption in a semiconductor integrated circuit device such as a system-on-chip having an internal module equipped with a plurality of function IP macros.

  Next, a clock synchronization control system according to an embodiment of the present invention will be described.

  In general, in a semiconductor processor having various internal modules such as a CPU core, SDRAM controller, peripheral bus controller, and timer, a specific internal module always requires a certain processing capability, and the CPU is required to operate at high speed. In such a semiconductor processor, the minimum clock frequency required for application processing is supplied, and the maximum performance is demanded depending on conditions such as process performance (manufacturing variation), power supply voltage, temperature, etc. In order to satisfy the following, for example, the clock frequency between the CPU core unit and the specific internal module is set as follows: (1) Internal module = 200 MHz, CPU core = 300 MHz (1.5 times), (2) Internal module = 200 MHz, CPU core = 400 MHz (2.0 times), (3) Internal module = 200 MHz, CPU core = 500 MHz (2.5 times), (4) Internal module = 200 MHz, CPU core = 600 MHz (3.0 times),. In some cases, it is desired to control the clock ratio of the corresponding clock frequency in increments of 0.5.

  In response to such a request, the clock generation unit in the processor generates a plurality of clocks having a clock ratio of 1: 1.5, 1: 2.5, 1: 3.5, etc. When the signal is supplied to the internal module, there is a problem that when the clock edges of the respective clocks are equally spaced, the signal synchronization circuit between the modules must operate at a frequency twice that of the earlier clock.

  The existence of such a circuit that operates at high speed becomes a major problem in logic design, layout, timing verification, and the like in LSI development.

  In the clock synchronization control method according to the present embodiment, even when the corresponding clock ratio is not an integral multiple, it is possible to operate at a desired operating frequency without very high-speed signal transfer between modules operating with each clock. It can be. In the clock synchronization control method according to the present embodiment, signal synchronization between modules operating with a non-integer multiple clock is realized by a simple method.

  FIG. 13 is a waveform diagram for explaining problems in the case of a reference clock (high-speed clock) and a 1.5 times clock (low-speed clock).

  In FIG. 13, (1) is a high-speed clock (in this case, a 300-MHz clock generated by dividing the 600-MHz PLL output clock by 2), and (2) is a low-speed clock (in this case, the 600-MHz PLL output clock is 3). (200 MHz clock generated by frequency division), (3) is the operating frequency at which the transfer circuit must operate when transferring signals from the high-speed clock to the low-speed clock, and (4) is from the low-speed clock to the high-speed clock. Indicates the operating frequency at which the transfer circuit must operate when changing signals.

  As shown in FIG. 13, when data signals are synchronized between two modules respectively operating with two clocks having non-integer multiple frequencies, the clock edges are aligned with each other. There is a problem that it is necessary to operate the transfer circuits of both modules at a high clock frequency corresponding to the least common multiple of the frequency of each clock.

  FIG. 14 is a waveform diagram for explaining the clock synchronization control method of the present invention in the case of FIG. 13 (clock ratio is 1: 1.5). FIG. 15 is a waveform diagram for explaining the clock synchronization control method of the present invention when the clock ratio is 1: 2.5. FIG. 16 is a waveform diagram for explaining the clock synchronization control method of the present invention when the clock ratio is 1: 3.5.

  14, 15, and 16, (1) is a PLL clock, (2) is a high-speed clock, (3) is a conventional low-speed clock with a constant cycle (clock edges are equally spaced), and (4) is the present embodiment. (5) shows the clock synchronization signal according to this embodiment.

  In the case of FIG. 14, the high-speed clock (2) and the low-speed clock (3) are each generated from the PLL clock (1), and the edges of each clock are equally spaced. In this state, as shown in FIG. 13, the signal transfer circuit between modules operating with both clocks must operate at twice the operating frequency of the high-speed clock.

  Therefore, in the clock synchronization control system of the present invention, control is performed so that the edge of the low-speed clock is aligned with the clock edge of the immediately preceding high-speed clock, as in the low-speed clock of this embodiment shown in (4) of FIG. Thus, signal transfer between modules operating with both clocks can be easily realized without using a clock having a frequency twice that of the high-speed clock. That is, as long as the signal transfer circuit of this embodiment can operate even at a high-speed clock frequency, signals can be transferred between modules operating with both clocks without any problem.

  At this time, since the clock edges of the low-speed clock are not equally spaced, the clock synchronization signal (5) is generated as a signal for indicating the position of the clock edge of the low-speed clock, and the clock synchronization signal (5) is transferred to the data signal. Used for control. By supplying the clock synchronization signal to the module that operates with the high-speed clock, the module that operates with the high-speed clock can recognize the data signal capture timing generated by the module that operates with the low-speed clock. Can be synchronized. The clock synchronization signal (5) is generated in accordance with the clock edge of the high-speed clock.

  FIG. 15 shows a waveform when the clock ratio between the high-speed clock and the low-speed clock is 1: 2.5. FIG. 16 shows a waveform when the clock ratio between the high-speed clock and the low-speed clock is 1: 3.5. In the case of FIG. 15 and FIG. 16, as in the case of FIG. 14, the clock synchronization signal for controlling the edge of the low-speed clock to be aligned with the edge of the high-speed clock and for indicating the position of the clock edge of the low-speed clock. Is used for control of data signal transfer, it is possible to synchronize signals generated by both non-integer multiple clocks.

  FIG. 17 is a waveform diagram for explaining the clock synchronization control method when the clock ratio is 1: 3. In FIG. 17, (1) is a PLL clock, (2) is a high-speed clock, (3) is a conventional low-speed clock with a constant period, and (4) is a clock synchronization signal.

  FIG. 17 shows a waveform when the clock ratio between the high-speed clock and the low-speed clock is an integer multiple of 1: 3. As can be seen from this waveform, when the clock ratio is an integral multiple, the positions of the clock edges of the low-speed clock are also equally spaced. The clock synchronization signal (5) is generated as a signal indicating the position of the clock edge of the low-speed clock.

  FIG. 18 shows a clock generator according to an embodiment of the present invention.

  18, 201 is an external input clock, 202 is a PLL circuit, 203 is a clock generator inside the processor, 204 is a CPU core, 205 is an internal module, 206 is an internal module, 207 is a high-speed clock, and 208 is a clock. A synchronization signal, 209 is a low-speed clock, and 210 is an on-chip bus inside the processor.

  FIG. 18 shows an embodiment of a processor using a high-speed clock, a low-speed clock, and a clock synchronization signal in this embodiment.

  In the processor of FIG. 18, an external input clock 201 is multiplied by a PLL circuit 202, and the PLL circuit 202 generates a fastest clock (hereinafter referred to as a PLL clock) that is a source for generating various clocks.

  The clock generation unit 203 generates a reference clock (in this case, a high-speed clock 207 and a low-speed clock 209) to each internal module by dividing the PLL clock by the frequency dividing circuit 203a. The clock generation unit 203 also generates a clock synchronization signal 208 indicating the position of the edge of the low-speed clock at the same time, and outputs the high-speed clock 207 and the clock synchronization signal 208 to the CPU core 204. A low speed clock 209 is supplied to the internal modules 205 and 206.

  The CPU core 204 basically operates with a high-speed clock (reference clock), but in an internal module 205 that operates with a low-speed clock, and an interface unit (BI) 204a with an on-chip bus 210 connected to the internal module 206. Uses the clock synchronization signal 208 to synchronize with the bus data signal.

  That is, the interface unit 204 a in the CPU core 204 grasps the position of the clock edge of the low-speed clock based on the clock synchronization signal 208. As a result, the interface unit 204a appropriately controls the timing of taking in the data signal supplied from the internal module to receive data, and appropriately controls the output timing of the data signal to the on-chip bus 210 to the internal module. Send the data.

  With such a circuit configuration, especially by using the low-speed clock 209 and the clock synchronization signal 208, there is no signal transfer by a high-speed clock even when the clock ratio is a non-integer multiple such as 1: 1.5. In addition, the processor circuit can be easily configured.

  FIG. 19 shows a clock generator according to another embodiment of the present invention.

  In the processor of FIG. 19, 201 is an external input clock, 202 is a PLL circuit, 203A is a clock generator inside the processor, 204 is a CPU core, 205A is an internal module, 206A is an internal module, 207 is a high-speed clock (reference clock), 208 is a clock synchronization signal, 210 is an on-chip bus inside the processor, 211 is a low-speed clock generated by the gated clock generation unit 205a of the internal module 205A, and 212 is a low-speed clock generated by the gated clock generation unit 206a of the internal module 206A. Respectively.

  In the embodiment of FIG. 19, the low-speed clock used in the internal module 205A and the internal module 206A is generated by the gated clock buffer in each internal module based on the high-speed clock 207 and the clock synchronization signal 208. The specific clock generation means for generating the low-speed clock of each internal module has the configuration of the synchronization control module described in each of the above embodiments in addition to the gated clock generation units 205a and 206a shown in FIG. It may be used.

  With such a configuration, the entire chip can generate a clock tree with one high-speed clock, and it is easy to reduce clock skew during layout design.

  FIG. 20 shows a clock generator according to another embodiment of the present invention.

  In the processor of FIG. 20, 201 is an external input clock, 202 is a PLL circuit, 203A is a clock generator inside the processor, 204 is a CPU core, 205B is an internal module, 206B is an internal module, 207 is a high-speed clock (reference clock), 208 is a clock synchronization signal, 210 is an on-chip bus inside the processor, 211 is a low-speed clock generated by the gated clock generators 205a and 205b of the internal module 205B, and 212 is generated by the gated clock generators 206a and 206b of the internal module 206B. Each of the low speed clocks to be performed is shown.

  FIG. 20 shows a circuit configuration in the case where the clock synchronization signal according to the embodiment of FIG. 19 is supplied by being shifted one cycle before the high-speed clock. The gated clock generators in the internal modules 205B and 206B include latch circuits 205b and 206b that hold the clock synchronization signal 208 in response to the high-speed clock 207, respectively.

  FIG. 21 is a waveform diagram for explaining the clock synchronization control method in the embodiment of FIG. In FIG. 21, (1) is a PLL clock, (2) is a high-speed clock, (3) is a conventional low-speed clock with a constant period, (4) is a low-speed clock according to this embodiment, and (5) is a clock according to this embodiment. The synchronization signal is output at a stage one cycle before the high-speed clock with respect to each clock edge of the low-speed clock.

  As shown in FIG. 21, according to the clock synchronization control system of this embodiment, the timing of the clock synchronization signal used as the control signal of the gated clock can be determined, and a safer clock design becomes possible. .

  In the clock synchronization control system of the above-described embodiment, even when the corresponding clock ratio is not an integral multiple, the data signal can be synchronized between the modules operating with the respective clocks without the signal transfer by the very high-speed clock. Therefore, the processor can be operated at a desired operating frequency. Specifically, when designing a processor having a plurality of clock frequencies that are non-integer multiples (especially layout and timing verification), the signal switching unit (bus interface unit) between modules is at least the faster clock frequency. It is possible to operate the processor at a desired operating frequency without any problem.

  Furthermore, a clock synchronization control system according to another embodiment of the present invention will be described.

  FIG. 22 is a waveform diagram for explaining a clock synchronization control method according to an embodiment of the present invention when the clock ratio between the high-speed clock and the low-speed clock is 1: 1.5 (FIG. 13).

  In FIG. 22, (1) is a PLL clock, (2) is a clock synchronization signal SYNC1 of a high-speed clock, (3) is a high-speed clock (reference clock) CLK1 (fast), (4) is a clock synchronization signal SYNC2 of a low-speed clock, (5) is a low-speed clock (reference clock) CLK2 (slow), (6) is a data signal generated by the high-speed clock CLK1 and its clock synchronization signal SYNC1, or is generated by the low-speed clock CLK2 and its clock synchronization signal SYNC2. The data signal (7) indicates a valid data position in data transfer between modules operating with both clocks in the data of (6).

  The high-speed clock (3) and the low-speed clock (5) are respectively generated by frequency division from the PLL clock (1), and the clock edges are equally spaced. In this state, as shown in FIG. 13, since the clock edges of both clocks are not aligned, the signal transfer circuit between modules operating on both clocks must operate at twice the operating frequency of the high-speed clock. .

  Therefore, in the clock synchronization control system of the present invention, the clock synchronization signals SYNC1 and SYNC2 shown in (2) and (4) of FIG. 22 are signals indicating positions where the clock edges of the high-speed clock and the low-speed clock coincide with each other. Generated with the corresponding clock. Based on the clock synchronization signals SYNC1 and SYNC2, data transmission / reception (transfer) is performed only when the corresponding clock edges are aligned in both clocks, making it easy to transfer signals between modules operating on both clocks. It can be realized.

  At this time, since the data transfer between the two modules is performed only when the clock edges coincide with each other between the two clocks, the operation frequency of the data transfer becomes the value of the greatest common divisor of the frequencies of the two clocks.

  That is, the clock synchronization signals SYNC1 and SYNC2 indicate the positions of clock edges effective for data transmission / reception (transfer) in the corresponding clock. The clock synchronization signals SYNC1 and SYNC2 are generated in accordance with the clock edges of the high-speed clock and the low-speed clock, respectively.

  Therefore, if the signal transfer circuit (bus interface circuit) of this embodiment can operate at the frequency of the greatest common divisor of both clocks, it is possible to transfer signals between modules operating with both clocks without any problem.

  FIG. 23 shows a basic configuration of a clock synchronization control system according to an embodiment of the present invention.

  In FIG. 23, 301 is a CPU core in this embodiment, 302 is a bus interface unit BI in the CPU core 301 in this embodiment, 303 is a processor internal module in this embodiment, and 304 is a processor internal module 303 in this embodiment. The bus interface unit BI, 305 is a clock generation module inside the processor in the present embodiment, 306 is a high-speed clock (reference clock) CLK1 (300 MHz in this case), 307 is a clock synchronization signal SYNC1, 308 of the high-speed clock, Clock (reference clock) CLK2 (in this case, 200 MHz), 309 is a low-speed clock synchronization signal SYNC2, and 310 is a bus signal for connecting the CPU core 301 and the internal module 303 in this embodiment. Show.

  In the clock synchronization control system of FIG. 23, the CPU core 301 basically operates based on the 300 MHz clock CLK1, and the internal module 303 basically operates based on the 200 MHz clock CLK2. Then, the bus 310 connecting both modules having a clock ratio of 1: 1.5 is operated at an operating frequency equivalent to 100 MHz in the same manner as in FIG. 22 using the clock synchronization signals SYNC 1 and SYNC 2 of this embodiment. This eliminates the need for a 600 MHz signal transfer circuit as shown in FIG.

  FIG. 24 shows the configuration of a clock synchronization control system according to another embodiment of the present invention. In this configuration example, the internal module 303 in FIG. 23 is replaced with a processor bus 303A.

  24, reference numerals 301 to 310 are basically the same as those in FIG. 23, and only the internal module 303 in FIG. 23 is replaced with the processor bus 303A. In the clock synchronous control system of FIG. 24, 311 is a bus connecting the processor bus 303A and other internal modules 313, 312 is a bus connecting the processor bus 303A and other internal modules 314, and 313 is an internal module in this embodiment. Reference numerals 314 denote internal modules in this embodiment.

  In the embodiment of FIG. 24, the processor bus 303A is a pipeline bus, and is a bus that transfers data to the CPU core 301 based on a bus control signal in synchronization with a bus clock (low-speed clock CLK2). Data transfer between the processor 303A and the internal modules 313 and 314 is performed based on the low-speed clock CLK2 (200 MHz).

  FIG. 25 is a waveform diagram for explaining the operation of the embodiment of FIG.

  25, (1) to (5) are the same as the corresponding signals in FIG. 22, and (6) is a data signal (CPU) inside the CPU core when data is transferred from the CPU core 301 to the bus 310. , (7) is a data signal (BUS) on the bus transaction output from the CPU core 301 to the bus 310, and (8) is a bus control signal (BUS_CTRL) indicating a valid data position of the data signal on the bus transaction. ) Respectively.

  In FIG. 25, the data (6) generated by the high-speed clock CLK1 in the CPU core 301 is output as bus data (7) at the edge of the high-speed clock CLK1 when the clock synchronization signal SYNC1 (2) is HIGH. . In the interface unit 304 with the CPU core 301 in the processor bus 303A that operates with the low-speed clock CLK1, a bus control signal (8) is generated that validates a cycle in which the clock synchronization signal SYNC2 changes from HIGH to LOW. The In the bus control signal (8), the cycle following the valid cycle is set to the invalid cycle. The interface unit 304 takes in the bus data output to the bus 310 during the valid cycle based on the bus control signal provided with the valid cycle and the invalid cycle, thereby performing the bus transfer.

  The waveform of the bus control signal (8) is merely an example, and the same cycle as that of the clock synchronization signal SYNC2 may be valid (specifications are different for each bus protocol).

  By providing a valid period and an invalid period in the bus control signal (8), when synchronizing the signals between modules operating with a non-integer multiple clock, the clock edges of both clocks are aligned. Only generated data can be validated and data can be transmitted and received, and signal transfer between non-integer multiple clocks can be easily performed. However, since the signal transfer frequency apparently decreases to the greatest common divisor of both clocks (100 MHz in this embodiment), the slew rate of data transfer is reduced, but each module is operated at a desired operating frequency. It becomes possible. This is effective when executing an application with little memory access, or when processing of the application can be performed almost only in the cache in the CPU core.

  FIG. 26 shows a clock synchronization control system according to an embodiment of the present invention.

  In FIG. 26, reference numerals 301 to 314 are basically the same as the corresponding components in FIG. In the clock synchronization control system of FIG. 26, the data bus width of the data bus signal 310 is 64 bits, the bus matrix 303a of the processor bus 303A and the data bus widths of the bus signals 311 and 312 are 32 bits, and the data The bus width of the bus signal 310 and the bus width of the bus matrix 303a are different from each other.

  In the embodiment shown in FIG. 26, the CPU core 301 and the processor bus 303A have a 64-bit bus width, which is twice the 32-bit bit width of the bus matrix 303a of the normal processor bus 303A. It is possible to prevent a decrease in transfer slew rate that occurs at the time of signal transfer.

  FIG. 27 is a waveform diagram for explaining the operation of the embodiment of FIG.

  27, (1) to (8) are basically almost the same as the corresponding signals in FIG. However, (6) is different from the data signal (6) in FIG. 25 and is a data signal inside the CPU core 301 having a data bus width of 64 bits, and (7) is different from the data signal (7) in FIG. The bus signal is a data signal on a bus transaction having a data bus width of 32 bits, and the bus signal for alternately transferring the 32-bit data on the HIGH side and the LOW side of the data signal (6) inside the CPU core is shown. Is.

  In FIG. 26, 64-bit data is output from the CPU core 301 to the bus 310, and the 64-bit data can be divided and transferred to two 32-bit data in the interface unit 304 with the CPU core 301 in the processor bus 303A. Converted to. Accordingly, in the bus control signal in FIG. 27, the invalid cycle of the bus control signal (8) in FIG. 25 is replaced with a valid cycle in accordance with the number of data divisions. A cycle in which SYNC2 changes from HIGH to LOW is set as a valid cycle, and the next cycle is also set as a valid cycle. Thereby, it is possible to transfer all the divided 32-bit data as valid data.

  FIG. 28 shows a clock synchronization control system according to an embodiment of the present invention.

  In FIG. 28, reference numerals 301, 303A, 305 to 309, 311 to 314 are the same as the corresponding components in FIG. 28, reference numeral 315 denotes a bus interface port (BI1) in the CPU core 301 in this embodiment, 316 denotes a bus interface port (BI2) in the CPU core 301 in this embodiment, and 317 denotes this embodiment. The signal transfer wrapper circuit (i / f) 318 with the bus interface port 315 (BI1) in the processor bus 303A in FIG. 6 is a signal transfer wrapper circuit (i / f) 318 with the bus interface port 316 (BI2) in the processor bus 303A in this embodiment. i / f), 319 is a bus connecting the bus interface port 315 (BI1) and the bus wrapper circuit 317 (i / f), 320 is a bus interface port 316 (BI2) and the bus wrapper circuit 318 (i / f) Connect It shows the bus, respectively.

  The clock synchronization control system of FIG. 28 has substantially the same circuit configuration as that of the embodiment of FIG. 26, and prevents a decrease in transfer slew rate, which is a disadvantage of the embodiment for facilitating the transfer between non-integer multiple clocks. To do. Specifically, in this embodiment, the 64-bit bit width of the bus interface port 302 in FIG. 26 is divided into two ports, and the CPU has two bus interface ports. In this embodiment, the CPU / bus 303A is mounted with a 2-port CPU interface as the CPU has a plurality of bus interface ports.

  A waveform diagram for explaining the operation of the present embodiment is omitted because the transfer transaction shown in the waveform diagram of FIG. 25 is merely executed independently at each of the two ports.

  As described above, in the clock synchronization control system of this embodiment, even when the corresponding clock ratio is not an integral multiple, the desired operation can be performed without performing very high-speed signal transfer between modules operating with the respective clocks. It is possible to operate the processor at a frequency. Specifically, when designing a processor having a plurality of clock frequencies that are non-integer multiples (especially layout and timing verification), it is only necessary that the signal switching unit between modules operates at least at the earlier clock frequency. It is possible to operate at a desired operating frequency without any problem.

Furthermore, in the case of the present embodiment, the data transfer performance of the signal transfer unit itself between modules operating at non-integer multiple clocks is degraded, but data transfer between these modules does not occur so frequently, It is possible to operate at a desired operating frequency. In addition, it is possible to avoid a decrease in transfer performance of the signal transfer unit.
(Appendix 1)
An internal bus, a plurality of internal modules connected to the internal bus and having a module body that realizes a predetermined function, a reference clock and a clock synchronization signal indicating a position of a valid clock edge of the reference clock, and A semiconductor integrated circuit device comprising: a clock generator for supplying to at least one of the plurality of internal modules, wherein at least one of the plurality of internal modules is based on the reference clock and the clock synchronization signal A semiconductor integrated circuit device comprising a synchronization control module for generating an internal clock supplied to the circuit.
(Appendix 2)
The semiconductor integrated circuit device according to appendix 1, wherein the clock generation unit includes a plurality of signal pairs including a plurality of reference clocks having different clock frequencies and a plurality of clock synchronization signals corresponding to the plurality of reference clocks. A semiconductor integrated circuit device that generates and supplies the plurality of signal pairs to different internal modules.
(Appendix 3)
The semiconductor integrated circuit device according to appendix 1, wherein a position of a clock edge of the internal clock coincides with a position of the effective clock edge.
(Appendix 4)
The semiconductor integrated circuit device according to appendix 1, wherein the synchronization control module includes a control unit that generates an internal clock control signal indicating whether the internal module is operable, and the clock synchronization signal is based on the internal clock control signal. A semiconductor integrated circuit device that performs at least one of supply, stop, and mask processing.
(Appendix 5)
The semiconductor integrated circuit device according to appendix 1, wherein the synchronization control module further includes a gate unit that controls supply and stop of the clock synchronization signal to the internal module, and the gate unit operates the internal module. A semiconductor integrated circuit device, wherein output of the clock synchronization signal is stopped when unnecessary.
(Appendix 6)
The semiconductor integrated circuit device according to appendix 1, wherein the synchronization control module further includes a mask unit that controls supply of the clock synchronization signal to the internal module and mask processing, and the mask unit operates the internal module. A semiconductor integrated circuit device characterized in that the clock synchronization signal is masked to a predetermined level and output when it is necessary.
(Appendix 7)
The semiconductor integrated circuit device according to appendix 1, wherein the clock generation unit generates a plurality of the clock synchronization signals indicating a plurality of clock frequencies and supplies them to the internal module, and the synchronization control module includes the plurality of clock synchronization signals. A semiconductor integrated circuit device characterized by receiving a clock synchronization signal and generating the internal clock based on the plurality of clock synchronization signals and the reference clock in accordance with an operating frequency of the internal module.
(Appendix 8)
The semiconductor integrated circuit device according to appendix 1, wherein the synchronization control module receives the reference clock, performs a count operation and generates a mask signal according to a count value, and outputs the clock synchronization signal based on the mask signal. A semiconductor device comprising: a gate unit that generates an internal clock generation control signal by thinning out at a predetermined rate; and an internal clock generation unit that generates the internal clock based on the internal clock generation control signal and the reference clock Integrated circuit device.
(Appendix 9)
A plurality of internal modules each including a plurality of bus masters and a plurality of bus slaves each having a module body that realizes a predetermined function; a bus unit that connects the plurality of bus masters and the plurality of bus slaves in a pipeline manner; and a reference A clock generation unit that generates a clock synchronization signal indicating a position of a clock and a valid clock edge of the reference clock and supplies the clock unit to the bus unit, wherein the bus unit includes the reference clock and A semiconductor integrated circuit device comprising a synchronization control module for generating an internal clock supplied to at least one of the plurality of bus masters and the plurality of bus slaves based on the clock synchronization signal.
(Appendix 10)
The semiconductor integrated circuit device according to appendix 9, wherein the bus unit includes a bus control unit that controls connection between the plurality of bus masters and the plurality of bus slaves, and the bus control unit includes the synchronization control module. A semiconductor integrated circuit device comprising:
(Appendix 11)
A plurality of internal modules each including a plurality of bus masters and a plurality of bus slaves each having a module body that realizes a predetermined function; a bus unit that connects the plurality of bus masters and the plurality of bus slaves in a crossbar manner; and a reference A clock generation unit that generates a clock and a clock synchronization signal indicating a position of a valid clock edge of the reference clock, and supplies the clock synchronization signal to the bus unit, wherein the bus unit includes the reference clock and A semiconductor integrated circuit device comprising a synchronization control module for generating an internal clock supplied to at least one of the plurality of bus masters and the plurality of bus slaves based on the clock synchronization signal.
(Appendix 12)
The semiconductor integrated circuit device according to appendix 11, wherein the bus unit includes a plurality of bus interface units corresponding to the plurality of bus masters and the plurality of bus slaves, and at least one of the plurality of bus interface units is the A semiconductor integrated circuit device comprising a synchronization control module.
(Appendix 13)
The semiconductor integrated circuit device according to appendix 11, wherein the synchronization control module further includes a mask unit that controls supply of the clock synchronization signal to a corresponding bus interface unit and mask processing, and the mask unit corresponds to a corresponding bus master. Alternatively, a semiconductor integrated circuit device is characterized in that when the operation of a bus slave is necessary, the clock synchronization signal is masked and output to a predetermined level.
(Appendix 14)
The semiconductor integrated circuit device according to appendix 1, wherein the internal module includes a bus interface unit for the internal bus, and the synchronization control module receives different internal clocks for the module body and the bus interface unit. A semiconductor integrated circuit device produced by the method.
(Appendix 15)
The semiconductor integrated circuit device according to appendix 4, wherein the control unit of the synchronous control module includes an interrupt request signal to the internal module, a DMA request request signal, a clock control signal supplied from the module body, and A semiconductor integrated circuit device that generates the internal clock control signal based on either a bus request signal or a bus acknowledge signal defined by a bus protocol of the internal bus.
(Appendix 16)
Clock control for controlling an internal clock supplied to the internal module in a semiconductor integrated circuit device comprising an internal bus and a plurality of internal modules connected to the internal bus and having a module body that realizes a predetermined function A method of generating a clock synchronization signal indicating a reference clock and a position of a valid clock edge of the reference clock and supplying the clock synchronization signal to at least one of the plurality of internal modules; and At least one of the clock control methods includes a synchronization control step of generating the internal clock based on the reference clock and the clock synchronization signal.
(Appendix 17)
A first internal module having a first module body connected to the internal bus and realizing a predetermined function; and a second module body connected to the internal bus and realizing a predetermined function. A second internal module that performs data transfer via the first internal module and the internal bus, generates a first reference clock and supplies the first reference clock to the first internal module; Clock generation for generating a clock synchronization signal indicating the position of a valid clock edge of the second reference clock corresponding to the position of the clock edge of the reference clock and the first reference clock and supplying the clock synchronization signal to the second internal module The first internal module is connected to the first reference clock in the first module body. The second internal module performs predetermined processing according to the second reference clock in the second module main body, and performs data transfer according to the clock edge of the first reference clock. And performing data transfer according to the effective clock edge based on the second reference clock and the clock synchronization signal.
(Appendix 18)
18. The semiconductor integrated circuit device according to appendix 17, wherein a clock frequency of the first reference clock is lower than a clock frequency of the second reference clock.
(Appendix 19)
18. The semiconductor integrated circuit device according to appendix 17, wherein clock edges of the second reference clock are arranged at equal intervals, and clock edges of the first reference clock are not arranged at equal intervals. Integrated circuit device.
(Appendix 20)
18. The semiconductor integrated circuit device according to appendix 17, wherein the positions of the clock edges of the first reference clock all coincide with the positions of the clock edges of the second reference clock. apparatus.
(Appendix 21)
18. The semiconductor integrated circuit device according to appendix 17, wherein the clock frequency of the second reference clock is a non-integer multiple of the clock frequency of the first reference clock.
(Appendix 22)
The semiconductor integrated circuit device according to appendix 17, wherein data transfer between the first internal module and the second internal module is performed at an operating frequency equal to a clock frequency of the first reference clock. A semiconductor integrated circuit device.
(Appendix 23)
A first internal module having a first module body connected to the internal bus and realizing a predetermined function; and a second module body connected to the internal bus and realizing a predetermined function. Generating a clock synchronization signal indicating a position of a valid clock edge of a reference clock and the reference clock, a second internal module that performs data transfer via the first internal module and the internal bus, A semiconductor integrated circuit device comprising a clock generation unit for supplying to the first internal module and the second internal module, wherein the first internal module is based on the reference clock and the clock synchronization signal. An internal clock generator for generating an internal clock supplied to the first module body; The second internal module executes predetermined processing according to the reference clock in the second module main body while performing predetermined processing according to the internal clock and transferring data according to the clock edge of the internal clock. A semiconductor integrated circuit device that performs data transfer according to the effective clock edge based on the reference clock and the clock synchronization signal.
(Appendix 24)
24. The semiconductor integrated circuit device according to appendix 23, wherein clock edges of the reference clock are arranged at regular intervals, and clock edges of the internal clock are not arranged at regular intervals.
(Appendix 25)
24. The semiconductor integrated circuit device according to appendix 23, wherein the clock frequency of the reference clock is a non-integer multiple of the clock frequency of the internal clock.
(Appendix 26)
24. The semiconductor integrated circuit device according to appendix 23, wherein the internal clock generator is the synchronization control module according to any one of appendix 1 to appendix 15.
(Appendix 27)
24. The semiconductor integrated circuit device according to appendix 23, wherein the clock edge position of the clock synchronization signal indicating the position of the effective clock edge of the reference clock is one cycle before the position of the effective clock edge of the reference clock. A semiconductor integrated circuit device, comprising:
(Appendix 28)
24. The semiconductor integrated circuit device according to appendix 23, wherein data transfer between the first internal module and the second internal module is performed at an operating frequency equal to a clock frequency of the internal clock. Semiconductor integrated circuit device.
(Appendix 29)
24. The semiconductor integrated circuit device according to claim 23, wherein a position of a clock edge of the internal clock coincides with a position of the effective clock edge.
(Appendix 30)
A first internal module having a first module body connected to the internal bus and realizing a predetermined function; and a second module body connected to the internal bus and realizing a predetermined function. A semiconductor integrated circuit device comprising: the first internal module; and a second internal module that transfers data via the internal bus, wherein the first internal module and the second internal module are arranged between the first internal module and the second internal module. A data transfer control method for controlling data transmission, comprising: a first clock generation step of generating a first reference clock and supplying the first reference clock to the first internal module; a second reference clock; and the first reference Generating a clock synchronization signal indicating the position of a valid clock edge of the second reference clock corresponding to the position of the clock edge of the clock to generate the second internal module; A second clock generation step for supplying data to a network, a first data transfer control step for controlling the first internal module to perform data transfer in accordance with a clock edge of the first reference clock, And a second data transfer control step for controlling to transfer data according to the effective clock edge based on the second reference clock and the clock synchronization signal. Transfer control method.
(Appendix 31)
A first internal module having a first module body connected to the internal bus and realizing a predetermined function; and a second module body connected to the internal bus and realizing a predetermined function. A semiconductor integrated circuit device comprising: the first internal module; and a second internal module that transfers data via the internal bus, wherein the first internal module and the second internal module are arranged between the first internal module and the second internal module. A data transfer control method for controlling data transmission, wherein a clock synchronization signal indicating a reference clock and a position of an effective clock edge of the reference clock is generated and supplied to the first internal module and the second internal module And generating a clock based on the reference clock and the clock synchronization signal in the first internal module. An internal clock generating step for generating an internal clock to be supplied to the module main body, and in the second module main body, predetermined processing is executed in accordance with the internal clock and data transfer is performed in accordance with a clock edge of the internal clock. A first data transfer control step for controlling the second clock, and a predetermined process in the second module body in accordance with the reference clock, and data transfer in accordance with the effective clock edge based on the reference clock and the clock synchronization signal. And a second data transfer control step for controlling to perform the data transfer.
(Appendix 32)
A first internal module having a first module body connected to the internal bus and realizing a predetermined function; and a second module body connected to the internal bus and realizing a predetermined function. A first internal module and a second internal module for transferring data via the internal bus, and a first reference clock and a first clock indicating a position of a valid clock edge of the first reference clock. And generating a second clock synchronization signal indicating a position of a valid clock edge of the second reference clock and the second reference clock. A semiconductor integrated circuit device including a clock generation unit for supplying to the second internal module, wherein the first internal module is the first module book And performing predetermined processing according to the first reference clock, transferring data according to a clock edge of the first reference clock based on the first reference clock and the first clock synchronization signal, The second internal module executes predetermined processing in accordance with the second reference clock in the second module main body, and the second reference clock based on the second reference clock and the second clock synchronization signal. A semiconductor integrated circuit device which performs data transfer according to an effective clock edge of a clock.
(Appendix 33)
33. The semiconductor integrated circuit device according to attachment 32, wherein data transfer between the first internal module and the second internal module is performed by using a clock frequency of the first reference clock and a clock of the second reference clock. A semiconductor integrated circuit device, which is performed at an operating frequency equal to the greatest common divisor of the frequency.
(Appendix 34)
34. The semiconductor integrated circuit device according to attachment 32, wherein an effective clock edge position of the first reference clock and an effective clock edge position of the second reference clock coincide with each other. A semiconductor integrated circuit device.
(Appendix 35)
34. The semiconductor integrated circuit device according to appendix 32, wherein at least one of a rising edge or a falling edge is coincident between the first clock synchronization signal and the second clock synchronization signal. A semiconductor integrated circuit device.
(Appendix 36)
39. The semiconductor integrated circuit device according to appendix 32, wherein clock edges are arranged at equal intervals in both the first reference clock and the second reference clock.
(Appendix 37)
39. The semiconductor integrated circuit device according to appendix 32, wherein the first internal module and the second internal module receive the data signal on the internal bus when the first clock synchronization signal or the second internal module is received. A semiconductor integrated circuit comprising: an interface unit that generates a bus control signal indicating validity or invalidity of a data signal output to the internal bus based on a clock synchronization signal, and captures the data signal according to the bus control signal Circuit device.
(Appendix 38)
38. The semiconductor integrated circuit device according to appendix 37, wherein the bus control signal alternately outputs a signal indicating validity and a signal indicating invalidity of the data signal output to the internal bus. apparatus.
(Appendix 39)
38. The semiconductor integrated circuit device according to appendix 37, wherein a data bus width of the first internal module is different from a data bus width of the second internal module, and the first internal module and the second internal module 2. A semiconductor integrated circuit device according to claim 1, wherein the internal module having the smaller data bus width captures the data signal output from the larger internal module on the internal bus in accordance with the bus control signal.
(Appendix 40)
40. The semiconductor integrated circuit device according to appendage 39, wherein the bus control signal outputs a signal indicating the validity of the data signal output to the internal bus continuously for the number of cycles corresponding to the number of divisions of the data signal. A semiconductor integrated circuit device.
(Appendix 41)
38. The semiconductor integrated circuit device according to appendix 37, wherein a data bus width of the first internal module is different from a data bus width of the second internal module, and the first internal module and the second internal module The internal module with the smaller data bus width of the module has a plurality of the interface portions, and the data signals output from the larger internal module onto the internal bus are parallelized via the plurality of interface portions. A semiconductor integrated circuit device characterized by being captured.
(Appendix 42)
A first internal module having a first module body connected to the internal bus and realizing a predetermined function; and a second module body connected to the internal bus and realizing a predetermined function. A semiconductor integrated circuit device comprising: the first internal module; and a second internal module that transfers data via the internal bus, wherein the first internal module and the second internal module are arranged between the first internal module and the second internal module. A data transfer control method for controlling data transmission, wherein the first internal module generates a first reference clock and a first clock synchronization signal indicating a position of a valid clock edge of the first reference clock. A first clock generation step supplied to the second reference clock and a second clock indicating a position of a valid clock edge of the second reference clock and the second reference clock. A second clock generation step of generating a signal and supplying the signal to the second internal module; executing predetermined processing in the first module body in accordance with the first reference clock; and the first reference clock And a first data transfer control step for controlling data transfer in accordance with an effective clock edge of the first reference clock based on the first clock synchronization signal; and A predetermined process is executed in accordance with a reference clock of the second reference clock and data transfer is controlled in accordance with an effective clock edge of the second reference clock based on the second reference clock and the second clock synchronization signal. And a data transfer control step. 2. A data transfer control method comprising:
(Appendix 43)
An internal bus, a plurality of internal modules connected to the internal bus and having a module body that realizes a predetermined function, a reference clock and a clock synchronization signal indicating a position of a valid clock edge of the reference clock, and A semiconductor integrated circuit device including a clock generation unit for supplying to at least one of the plurality of internal modules, wherein at least one of the plurality of internal modules has a predetermined value based on the reference clock and the clock synchronization signal A semiconductor integrated circuit device that performs internal processing.
(Appendix 44)
44. The semiconductor integrated circuit device according to appendix 43, wherein the predetermined internal processing is internal clock generation processing for generating an internal clock supplied to the internal module.
(Appendix 45)
44. The semiconductor integrated circuit device according to appendix 43, wherein the predetermined internal processing is involved in the data transfer when the data transfer is performed between the plurality of internal modules via the internal bus, and at different operating frequencies. A semiconductor integrated circuit device characterized in that it is signal synchronization processing for performing synchronization control of a data signal between two operating internal modules.
(Appendix 46)
44. The semiconductor integrated circuit device according to appendix 43, wherein at least one of the plurality of internal modules includes a module that executes the predetermined internal processing in accordance with an effective clock edge of the reference clock. Integrated circuit device.

It is a block diagram which shows the structure of the basic processor in one Example of this invention. It is a wave form diagram for demonstrating a reference clock and a clock synchronizing signal. It is a block diagram which shows the internal module of the semiconductor integrated circuit device based on one Example of this invention. It is a circuit diagram which shows the synchronous control module which concerns on one Example of this invention. It is a wave form diagram for demonstrating the semiconductor integrated circuit device based on one Example of this invention. It is a circuit diagram which shows the synchronous control module which concerns on one Example of this invention. It is a circuit diagram which shows the synchronous control module which concerns on one Example of this invention. It is a circuit diagram which shows the synchronous control module which concerns on one Example of this invention. It is a block diagram which shows the synchronous control system which concerns on one Example of this invention. It is a block diagram which shows the synchronous control system which concerns on one Example of this invention. It is a circuit diagram which shows the synchronous control module which concerns on one Example of this invention. It is a block diagram which shows the internal module of the semiconductor integrated circuit device based on one Example of this invention. It is a wave form diagram for demonstrating a reference | standard clock and a 1.5 time clock. It is a wave form diagram for demonstrating the clock synchronous control system in the case of FIG. It is a wave form diagram for demonstrating the clock synchronous control system in case a clock ratio is 1: 2.5. It is a wave form diagram for demonstrating the clock synchronous control system in case a clock ratio is 1: 3.5. It is a wave form diagram for demonstrating the clock synchronous control system in case a clock ratio is 1: 3. It is a block diagram which shows the clock generation part which concerns on one Example of this invention. It is a block diagram which shows the clock generation part which concerns on one Example of this invention. It is a block diagram which shows the clock generation part which concerns on one Example of this invention. It is a wave form diagram for demonstrating the clock synchronous control system in the Example of FIG. It is a wave form diagram for demonstrating the clock synchronous control system which concerns on one Example of this invention. 1 is a block diagram illustrating a clock synchronization control system according to an embodiment of the present invention. 1 is a block diagram illustrating a clock synchronization control system according to an embodiment of the present invention. It is a wave form diagram for demonstrating the clock synchronous control system which concerns on one Example of this invention. 1 is a block diagram illustrating a clock synchronization control system according to an embodiment of the present invention. It is a wave form diagram for demonstrating the clock synchronous control system which concerns on one Example of this invention. 1 is a block diagram illustrating a clock synchronization control system according to an embodiment of the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 External input clock 2 External input terminal signal 3 PLL circuit 4 Clock generation part 5 CPU cores 6 and 7 Internal module 8 Clock control register 9 Internal on-chip bus 10 High-speed reference clocks 11 and 13 Clock synchronization signal 12 Low-speed reference clock 14 , 15 Clock control signal

Claims (10)

An internal bus,
A first internal module connected to the internal bus and having a first module body for realizing a predetermined function;
A second internal module connected to the internal bus and having a second module body for realizing a predetermined function, and transferring data via the first internal module and the internal bus;
Generating and supplying a first reference clock to the first internal module;
A clock synchronization signal indicating a valid clock edge position of the second reference clock corresponding to a second reference clock and a clock edge position of the first reference clock is generated and supplied to the second internal module. A semiconductor integrated circuit device comprising:
The first internal module performs predetermined processing according to the first reference clock in the first module body, and performs data transfer according to a clock edge of the first reference clock,
The second internal module performs predetermined processing according to the second reference clock in the second module main body, and data according to the effective clock edge based on the second reference clock and the clock synchronization signal. A semiconductor integrated circuit device that performs transfer. An internal bus,
A first internal module connected to the internal bus and having a first module body for realizing a predetermined function;
A second internal module connected to the internal bus and having a second module body for realizing a predetermined function, and transferring data via the first internal module and the internal bus;
A semiconductor integrated circuit device comprising: a reference clock and a clock generation unit that generates a clock synchronization signal indicating a position of a valid clock edge of the reference clock and supplies the clock synchronization signal to the first internal module and the second internal module There,
The first internal module includes an internal clock generation unit that generates an internal clock supplied to the first module main body based on the reference clock and the clock synchronization signal. In the first module main body, Performs predetermined processing according to the internal clock and performs data transfer according to the clock edge of the internal clock,
The second internal module performs predetermined processing according to the reference clock in the second module main body and performs data transfer according to the effective clock edge based on the reference clock and the clock synchronization signal. A semiconductor integrated circuit device. An internal bus,
A first internal module connected to the internal bus and having a first module body for realizing a predetermined function;
A second internal module connected to the internal bus and having a second module body for realizing a predetermined function, and transferring data via the first internal module and the internal bus;
A first clock synchronization signal indicating a position of a valid clock edge of the first reference clock and the first reference clock is generated and supplied to the first internal module, and the second reference clock and the second reference clock are generated. A clock generation unit that generates a second clock synchronization signal indicating a position of a valid clock edge of two reference clocks and supplies the second clock synchronization signal to the second internal module, and a semiconductor integrated circuit device,
The first internal module performs predetermined processing in the first module body according to the first reference clock, and the first internal module based on the first reference clock and the first clock synchronization signal. Data transfer according to the clock edge of the reference clock
The second internal module executes a predetermined process according to the second reference clock in the second module main body, and the second internal module based on the second reference clock and the second clock synchronization signal. A semiconductor integrated circuit device that performs data transfer according to an effective clock edge of the reference clock. The semiconductor integrated circuit device according to claim 3,
Data transfer between the first internal module and the second internal module is performed at an operating frequency equal to the greatest common divisor of the clock frequency of the first reference clock and the clock frequency of the second reference clock. A semiconductor integrated circuit device. The semiconductor integrated circuit device according to claim 3,
A position of a valid clock edge of the first reference clock and a position of a valid clock edge of the second reference clock coincide with each other. The semiconductor integrated circuit device according to claim 3,
When the first internal module and the second internal module capture a data signal on the internal bus, the first internal module and the second internal module output to the internal bus based on the first clock synchronization signal or the second clock synchronization signal A semiconductor integrated circuit device, comprising: an interface unit that generates a bus control signal indicating validity or invalidity of the data signal and fetches the data signal in accordance with the bus control signal. The semiconductor integrated circuit device according to claim 6,
The data bus width of the first internal module is different from the data bus width of the second internal module,
The internal module with the smaller data bus width of the first internal module and the second internal module divides the data signal output from the larger internal module onto the internal bus according to the bus control signal. A semiconductor integrated circuit device characterized by being captured. The semiconductor integrated circuit device according to claim 6,
The data bus width of the first internal module is different from the data bus width of the second internal module,
The internal module with the smaller data bus width of the first internal module and the second internal module has a plurality of the interface units, and the data signal output from the larger internal module onto the internal bus Is incorporated in parallel via the plurality of interface units. A first internal module having a first module body connected to the internal bus and realizing a predetermined function; and a second module body connected to the internal bus and realizing a predetermined function. A semiconductor integrated circuit device comprising: the first internal module; and a second internal module that transfers data via the internal bus, wherein the first internal module and the second internal module are arranged between the first internal module and the second internal module. A data transfer control method for controlling data transmission,
A first clock generation step of generating a first clock synchronization signal indicating a first reference clock and a position of a valid clock edge of the first reference clock and supplying the first clock synchronization signal to the first internal module;
A second clock generation step of generating a second reference clock and a second clock synchronization signal indicating a position of a valid clock edge of the second reference clock and supplying the second clock synchronization signal to the second internal module;
The first module main body executes predetermined processing according to the first reference clock, and an effective clock edge of the first reference clock based on the first reference clock and the first clock synchronization signal. A first data transfer control step for controlling to perform data transfer according to
The second module body executes predetermined processing according to the second reference clock, and an effective clock edge of the second reference clock based on the second reference clock and the second clock synchronization signal. A data transfer control method comprising: a second data transfer control step for controlling to perform data transfer according to: An internal bus,
A plurality of internal modules connected to the internal bus and having a module body for realizing a predetermined function;
A clock generation unit that generates a reference clock and a clock synchronization signal indicating a position of a valid clock edge of the reference clock, and supplies the clock synchronization signal to at least one of the plurality of internal modules. At least one of the internal modules performs a predetermined internal process based on the reference clock and the clock synchronization signal.

Images