JP2010033314A - Bus access circuit device and bus access method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the number of system buses without decreasing processing speed. <P>SOLUTION: The bus access circuit device is provided with an access control means for controlling accesses when a master module accesses a slave module via a system bus. The bus access circuit device is further provided with: a request signal selection means which, when receiving request signals from master modules larger in number than the system buses, repeats operation of selecting any one of received request signals and selecting any one other than the selected one until the number of request signals selected by the selection operation becomes equal to the number of system buses; and a signal input/output means for transmitting signals necessary for the master module which has output the request signal selected by the request signal selection means to access the slave module, via the system bus. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a bus access circuit device and a bus access method for performing access control when a master module accesses a slave module via a system bus.

2. Description of the Related Art Conventionally, there has been known a semiconductor integrated circuit device that can significantly improve processing speed by enabling parallel access to different slave modules (see, for example, Patent Document 1). This is because when the DMAC requests access to the slave module, the bus controller outputs a bus access request signal to the bus access arbitration unit, and in response, the bus access arbitration unit enables the DMAC to access the slave module. Mediation is performed. When the CPU requests access to the slave module during DMAC access, the bus controller outputs a bus access request signal to the bus access arbitration unit, and the bus access arbitration unit By performing arbitration so that the CPU can access the slave module, a plurality of bus masters can access different slave modules.
JP 2007-188214 A

  By the way, there are a plurality of master modules that perform control processing such as a CPU (Central Processing Unit) when connecting between modules provided in LSI (Large Scale Integrated Circuit) using a bus. When there are a plurality of slave modules to be accessed by these master modules, the connection form shown in FIG. 4 is generally known in order to enable access from all the master modules to all the slave modules. In the connection form shown in FIG. 4, one master module 1, 2, 3 is connected to each of the three system buses L1, L2, L3. Each of the four slave modules 5, 6, 7, 8 is connected to bus selectors 13, 14, 15, 16 that select one of the three system buses L 1, L 2, L 3. In the case of using this connection form, the master module can perform access without causing a standby unless two or more master modules simultaneously access one slave module.

  However, in the connection form shown in FIG. 4, the same number of system buses as the master modules are required. Therefore, when the number of master modules increases, the number of system buses must be increased. When the number of system buses increases, the timing of each module is difficult to adjust when performing layout inside the LSI, and the number of repeater buffers to be inserted for timing adjustment increases, resulting in an increase in power consumption. There is a problem of end.

  On the other hand, as another connection form, a connection form shown in FIG. 5 is also known. In the connection form shown in FIG. 5, each of the three master modules 1, 2, 3 and the four slave modules 5, 6, 7, 8 is connected to the access control unit 17, and the access control unit 17 is changed from the master module to the slave module. By arbitrating access to the system, the number of system buses can be reduced, and the layout inside the LSI can be easily performed.

  However, in the connection form shown in FIG. 5, when each master module accesses the slave module, the access control unit 17 performs arbitration, and the access operations are executed in order. The master module has to wait until the access operation can be started, and there is a problem that the processing operation speed decreases.

  The present invention has been made in view of such circumstances, and an object thereof is to provide a bus access circuit device and a bus access method capable of reducing the number of system buses without reducing the processing speed. .

  The present invention is a system in which three or more master modules, a plurality of slave modules to be accessed by the master modules, and each of the slave modules are connected, and the number is less than the number of the master modules and two or more. Bus access comprising: a bus; and an access control means connected to each of the master module and the system bus, and performing access control when the master module accesses the slave module via the system bus In the circuit device, when the request signal is input from each of the master modules whose number is larger than the number of the system buses, the access control unit is configured to request any one of the input request signals. Select a signal and remove the selected request signal Request signal selecting means for repeatedly selecting one of the request signals until the number of the request signals selected by the selecting operation reaches the number of the system buses, and the request signal selecting means And a signal input / output means for transmitting / receiving a signal necessary for the master module that has output the request signal selected by the access to the slave module via the system bus.

  The present invention is a system in which three or more master modules, a plurality of slave modules to be accessed by the master modules, and each of the slave modules are connected, and the number is less than the number of the master modules and two or more. Bus access comprising: a bus; and an access control means connected to each of the master module and the system bus, and performing access control when the master module accesses the slave module via the system bus A bus access method in a circuit device, wherein when the access control means receives a request signal from each of the number of master modules greater than the number of the system buses, any of the input request signals is selected. Select one request signal and select A request signal selection step of repeatedly performing an operation of selecting any one of the request signals excluding the requested signal until the number of the request signals selected by the selection operation reaches the number of the system buses And the access control means, through which the master module that has output the request signal selected in the request signal selection step transmits / receives a signal necessary for accessing the slave module via the system bus And an input / output step.

  According to the present invention, when a signal is exchanged between the master module and the slave modules via a system bus smaller than the number of master modules, any one of the input request signals is received. The operation of selecting and selecting any one request signal from the request signals excluding the selected request signal is repeated until the number of request signals selected by the selection operation reaches the number of system buses. Since the master module that has output the selected request signal sends and receives the signals necessary for accessing the slave module via the system bus, the bus does not slow down the access operation processing speed. The number of lines can be reduced, and the power consumption of the circuit device can be reduced.

  A bus access circuit device according to an embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of the embodiment. Reference numerals 1, 2, and 3 are master modules for realizing a CPU function, a DSP (Digital Signal Processor) function, and the like. Reference numeral 4 denotes an access control unit that controls access operations of the master modules 1, 2, and 3 via the two system buses L1 and L2. Reference numerals 5, 6, 7, and 8 are slave modules to be accessed by the master modules 1, 2, and 3. Reference numerals 9, 10, 11, and 12 are bus selection units that are connected to the four slave modules 5, 6, 7, and 8, respectively, and select one of the two system buses L 1 and L 2 used for the access operation.

  Next, with reference to FIG. 1, signals exchanged between the master modules 1, 2, and 3, the access control unit 4, and the system buses L1 and L2 will be described. The REQ signal is a request signal for requesting access from the master modules 1 to 3 to the slave modules 5 to 8. The GRANT signal is a permission signal for allowing each of the slave modules 5 to 8 to permit access to the REQ signal. The ADDRESS signal is an address signal that designates an address that specifies the slave module 5 to 8 to be accessed from any one of the master modules 1 to 3. The DATA signal is a data signal of data exchanged in an access operation performed between any one of the master modules 1 to 3 and any one of the slave modules 5 to 8.

  Next, an access request operation in the access control unit 4 shown in FIG. 1 will be described with reference to FIG. FIG. 2 is a block diagram showing functional blocks for realizing the function at the time of access request of the access control unit 4 shown in FIG. First, the first selection unit 41 receives the REQ signal S1 output from the master module 1, the REQ signal S2 output from the master module 2, and the REQ signal S3 output from the master module 3. Here, the operation when the REQ signal is simultaneously output from each of the three master modules 1 to 3 will be described. When receiving the REQ signal, the first selection unit 41 selects one of the three REQ signals. This selection is performed by selecting one of the REQ signals based on the selection priority that is determined in advance.

  For example, the selection priority order is determined in the order of the master module 1, the master module 2, and the master module 3, and the master module 1 is selected in the first selection operation. In the second selection operation, the selection priority order determined in advance is switched, and the master module 3, the master module 2, and the master module 1 are arranged in this order. In the third selection operation, the priority order is switched every time the selection operation is performed, such as the order of the master module 2, the master module 1, and the master module 3. By doing so, it is possible to prevent the selected master module from being biased to one master module. Here, it is assumed that the REQ signal S1 (the REQ signal output from the master module 1) is selected.

  Next, the first selection unit 41 outputs a request selection signal S4 indicating the selection result of the REQ signal. The request selection signal S4 is a signal that can identify a master module that is to send and receive signals via the system bus L1. The request selection signal S4 is input to the second selection unit 42 and the request signal output unit 43. When the request selection signal S4 is input, the second selection unit 42 receives request signals (two of S1, S2, and S3) output from two master modules excluding the master module indicated by the request selection signal S4. Of these, one REQ signal is selected. In this selection as well as the first selection unit, the selection priority is determined, and selection is performed while changing the selection priority every time a selection operation is performed. Here, it is assumed that the REQ signal S2 (the REQ signal output from the master module 2) is selected. The second selection unit 42 outputs a request selection signal S5 indicating the selection result of the REQ signal. The request selection signal S5 is a signal that can identify a master module that is to exchange a signal via the system bus L2. The request selection signal S5 is input to the request signal output unit 44.

  Next, the request signal output unit 43 includes three REQ signals S1, S2, and S3, an ADDRESS signal S6 output from the master module 1 along with the REQ signal, an ADDRESS signal S7 output from the master module 2, and a master module. 3 is input with an ADDRESS signal S8. The request signal output unit 43 refers to the request selection signal S4 output from the first selection unit 41, and receives the REQ signal S9 (here, the master module 1) output from the selected master module (here, the master module 1). REQ signal S1) and ADDRESS signal S10 (ADDRESS signal S6) are selected and output to L1 input / output unit 45. The L1 input / output unit 45 outputs the REQ signal S9 and the ADDRESS signal S10 to the access request target slave module via the system bus L1.

  On the other hand, the request signal output unit 44 includes three REQ signals S1, S2, and S3, an ADDRESS signal S6 output from the master module 1 in accordance with the REQ signal, an ADDRESS signal S7 output from the master module 2, and a master module 3 The ADDRESS signal S8 output from is input. Then, the request signal output unit 44 refers to the request selection signal S5 output from the second selection unit 42, and receives the REQ signal S11 (here, the master module 2) output from the selected master module (here, the master module 2). REQ signal S2) and ADDRESS signal S12 (ADDRESS signal S7) are selected and output to L2 input / output unit 46. The L2 input / output unit 46 outputs the REQ signal S11 and the ADDRESS signal S12 to the access request target slave module via the system bus L2.

  Next, the L1 input / output unit 45 inputs the GRANT signal S13 output from the slave module via the system bus L1, and outputs the GRANT signal S13 to each of the response output units 47, 48, and 49. Each of the response output units 47, 48, and 49 receives the request selection signal S4 output from the first selection unit 41. The response output unit 47 outputs the GRANT signal S15 to the master module 1 when the input request selection signal S4 is a signal indicating the master module 1 and the GR1 signal S13 is output from the L1 input / output unit 45. To do. The GRANT signal S15 is not output when the request selection signal S4 is not a signal indicating the master module 1. In this example, since the master module 1 is selected by the first selection unit 41, the GRANT signal S15 is output.

  The response output unit 48 outputs the GRANT signal S16 to the master module 2 when the input request selection signal S4 is a signal indicating the master module 2 and the LANT input / output unit 45 outputs the GRANT signal S13. To do. The GRANT signal S16 is not output when the request selection signal S4 is not a signal indicating the master module 2. The response output unit 49 outputs the GRANT signal S17 to the master module 3 when the input request selection signal S4 is a signal indicating the master module 3 and the L1 input / output unit 45 outputs the GRANT signal S13. To do. The GRANT signal S17 is not output when the request selection signal S4 is not a signal indicating the master module 3.

  On the other hand, the L2 input / output unit 46 inputs the GRANT signal S14 output from the slave module via the system bus L2, and outputs the GRANT signal S14 to each of the response output units 47, 48, and 49. Each of the response output units 47, 48, and 49 receives the request selection signal S5 output from the second selection unit 42. The response output unit 47 outputs the GRANT signal S15 to the master module 1 when the input request selection signal S5 is a signal indicating the master module 1 and the GR2 signal S14 is output from the L2 input / output unit 46. To do. The GRANT signal S15 is not output when the request selection signal S5 is not a signal indicating the master module 1.

  The response output unit 48 outputs the GRANT signal S16 to the master module 2 when the input request selection signal S5 is a signal indicating the master module 2 and the GRANT signal S14 is output from the L2 input / output unit 46. To do. The GRANT signal S16 is not output when the request selection signal S5 is not a signal indicating the master module 2. In this example, since the master module 2 is selected by the second selection unit 42, the GRANT signal S16 is output. The response output unit 49 outputs the GRANT signal S17 to the master module 3 when the input request selection signal S5 is a signal indicating the master module 3 and the LANT input / output unit 46 outputs the GRANT signal S14. To do. The GRANT signal S17 is not output when the request selection signal S5 is not a signal indicating the master module 3.

  By such an operation, the REQ signal is output from the master module to the slave module, and the GRANT signal is output from the slave module to the master module.

  Next, a data access operation in the access control unit 4 shown in FIG. 1 will be described with reference to FIG. FIG. 2 is a block diagram showing functional blocks for realizing functions at the time of data access of the access control unit 4 shown in FIG. Since the first selection unit 41 and the second selection unit 42 in FIG. 3 are the same as the first selection unit 41 and the second selection unit 42 shown in FIG. 2, detailed description of the processing operation is omitted. Here, as described above, it is assumed that the master module 1 is selected by the first selection unit 41 and the master module 2 is selected by the second selection unit 42.

  Next, the data signal output unit 50 receives the DATA signal S18 output from the master module 1, the DATA signal S19 output from the master module 2, and the DATA signal S20 output from the master module 3. The data signal output unit 50 refers to the request selection signal S4 output from the first selection unit 41, and the DATA signal S21 (here, the master module 1) output by the selected master module (here, the master module 1). The DATA signal S18) is selected and output to the L1 input / output unit 45. The L1 input / output unit 45 outputs the DATA signal S21 to the data access target slave module (slave module that outputs the GRANT signal) via the system bus L1.

  On the other hand, the data signal output unit 51 receives the DATA signal S18 output from the master module 1, the DATA signal S19 output from the master module 2, and the DATA signal S20 output from the master module 3. Then, the data signal output unit 51 refers to the request selection signal S5 output from the second selection unit 42, and the DATA signal S22 (here, the master module 2) output by the selected master module (here, the master module 2). The DATA signal S19) is selected and output to the L2 input / output unit 46. The L2 input / output unit 46 outputs the DATA signal S22 to the data access target slave module (slave module that outputs the GRANT signal) via the system bus L2.

  Next, the L1 input / output unit 45 inputs the DATA signal S23 output from the slave module via the system bus L1, and outputs the DATA signal S23 to each of the data signal input units 52, 53, and 54. . Each of the data signal input units 52, 53, 54 receives the request selection signal S 4 output from the first selection unit 41. The data signal input unit 52 is a signal indicating that the input request selection signal S4 indicates the master module 1, and when the DATA signal S23 is output from the L1 input / output unit 45, the data signal S25 is sent to the master module 1. Output. The DATA signal S25 is not output when the request selection signal S4 is not a signal indicating the master module 1. In this example, since the master module 1 is selected by the first selection unit 41, the DATA signal S25 is output.

  The data signal input unit 53 is a signal indicating that the input request selection signal S4 indicates the master module 2. When the DATA signal S23 is output from the L1 input / output unit 45, the data signal input unit 53 sends the DATA signal S26 to the master module 2. Output. The DATA signal S26 is not output when the request selection signal S4 is not a signal indicating the master module 2. The data signal input unit 54 is a signal indicating that the input request selection signal S4 indicates the master module 3. When the DATA signal S23 is output from the L1 input / output unit 45, the data signal input unit 54 sends the DATA signal S27 to the master module 3. Output. The DATA signal S27 is not output when the request selection signal S4 is not a signal indicating the master module 3.

  On the other hand, the L2 input / output unit 46 inputs the DATA signal S24 output from the slave module via the system bus L2, and outputs the DATA signal S24 to each of the data signal input units 52, 53, and 54. Each of the data signal input units 52, 53, and 54 receives the request selection signal S5 output from the second selection unit 42. In the data signal input unit 52, when the input request selection signal S5 is a signal indicating the master module 1 and the DATA signal S24 is output from the L2 input / output unit 46, the DATA signal S25 is sent to the master module 1. Output. The DATA signal S25 is not output when the request selection signal S5 is not a signal indicating the master module 1.

  The data signal input unit 53 is a signal indicating that the input request selection signal S5 indicates the master module 2. When the DATA signal S24 is output from the L2 input / output unit 46, the data signal input unit 53 sends the DATA signal S26 to the master module 2. Output. The DATA signal S26 is not output when the request selection signal S5 is not a signal indicating the master module 2. In this example, since the master module 2 is selected by the second selection unit 42, the DATA signal S26 is output. The data signal input unit 54 is a signal indicating that the input request selection signal S5 indicates the master module 3. When the DATA signal S24 is output from the L2 input / output unit 46, the data signal input unit 54 sends the DATA signal S27 to the master module 3. Output. The DATA signal S17 is not output when the request selection signal S5 is not a signal indicating the master module 3.

  With this operation, the DATA signal is exchanged between the master module and the slave module.

  In the above description, an example of three master modules and two system buses is shown, but the number of master modules and system buses is not limited to this. That is, the present invention can be applied if the number of master modules is three or more, the number of system buses is smaller than the number of master modules, and two or more. In this case, the first selection unit 41, the second selection unit 42, and the request signal output shown in FIGS. 2 and 3 are arranged so that the number of selection units, request signal output units, and data signal output units is the same as the number of system buses. In addition to the units 43 and 44 and the data signal output units 50 and 51, a new selection unit, a request signal output unit, and a data signal output unit may be provided. In addition, the number of response output units and data signal input units is the same as the number of master modules, so that the response output units 47, 48, 49 and data signal input units 52, 53, 54 shown in FIGS. In addition, a new response output unit and data signal input unit may be provided.

  When a request signal is input from each of the master modules whose number is larger than the number of system buses, any one of the input request signals is selected, and the selected request signal is excluded. The operation of selecting any one of the request signals may be repeated until the number of request signals selected by this selection operation reaches the number of system buses. In this way, the present invention can be applied to the case where the number of master modules is 4 and the number of system buses is 2 or the number of master modules is 4 and the number of system buses is 3.

  As described above, when a signal is exchanged between the master module and the slave module via the system bus that is smaller than the number of master modules, any one of the input request signals is received. The operation of selecting and selecting any one request signal from the request signals excluding the selected request signal is repeated until the number of request signals selected by the selection operation reaches the number of system buses. Since the master module that has output the selected request signal sends and receives the signals necessary for accessing the slave module via the system bus, the bus does not slow down the access operation processing speed. The number of lines can be reduced, and the power consumption of the circuit device can be reduced.

  In general, a system bus such as a processor composed of an LSI is composed of an address bus and a data bus. Therefore, the number of signal lines is very large, and high-speed transmission can be performed to operate the processor at high speed. There is a need. It is very difficult to perform wiring by arranging a slave module or the like inside an LSI while maintaining a synchronous relationship between a plurality of signal lines connected to a large number of signal lines and a high-speed bus line. In order to solve this, it is necessary to insert a repeater buffer in the bus line, and it is also necessary to insert a buffer in the clock line. For this reason, the layout becomes complicated and the power consumed by the buffer increases, resulting in an increase in the power consumption of the LSI.

  In the present invention, the number of bus lines can be reduced, so that power consumption can be reduced while maintaining the ability of a processor configured with an LSI. Further, since it is not necessary to insert a repeater buffer, the circuit scale can be reduced. Furthermore, since the logic lines subject to timing adjustment can be reduced, the difficulty of adjustment work during layout can be reduced.

  As described above, the bus access circuit device according to the present invention is provided inside the LSI, and also transfers instructions and data between the processor configured by the LSI and a device such as a storage device or an input / output device. The present invention can also be applied to an external bus that performs the above, an expansion bus that transfers instructions and data between an expansion card for connecting peripheral devices and enhancing functions and a computer main body.

It is a block diagram which shows the structure of one Embodiment of this invention. It is a block diagram which shows the detailed structure of the access control part 4 shown in FIG. It is a block diagram which shows the detailed structure of the access control part 4 shown in FIG. It is a block diagram which shows the connection form of the master module and slave module by a prior art. It is a block diagram which shows the connection form of the master module and slave module by a prior art.

Explanation of symbols

  1, 2, 3 ... Master module, 4 ... Access control unit, 5, 6, 7, 8 ... Slave module, 9, 10, 11, 12 ... Bus selection unit, L1, L2,. ..System bus

Claims (2)

3 or more master modules,
A plurality of slave modules to be accessed by the master module;
Each of the slave modules is connected, less than the number of the master modules, and two or more system buses;
A bus access circuit device connected to each of the master module and the system bus, and comprising access control means for performing access control when the master module accesses the slave module via the system bus. There,
The access control means includes
When a request signal is input from each of the master modules whose number is greater than the number of the system buses, any one request signal is selected from the input request signals, and the selected request signal is selected. Request signal selection means for repeatedly selecting an operation for selecting any one of the request signals except for the number of the request signals selected by the selection operation until the number of the system buses;
A signal input / output means for performing transmission / reception of a signal necessary for the master module that has output the request signal selected by the request signal selection means to access the slave module via the system bus; A bus access circuit device. 3 or more master modules,
A plurality of slave modules to be accessed by the master module;
Each of the slave modules is connected, less than the number of the master modules, and two or more system buses;
In a bus access circuit device, comprising: an access control unit that is connected to each of the master module and the system bus, and performs access control when the master module accesses the slave module via the system bus A bus access method,
When the access control means receives a request signal from each of the master modules whose number is greater than the number of the system buses, the access control means selects any one request signal from the input request signals, Request signal selection for repeatedly selecting one of the request signals excluding the selected request signal until the number of the request signals selected by the selection operation reaches the number of the system buses Steps,
A signal input / output for transmitting / receiving signals necessary for the master module to access the slave module by the access control means that has output the request signal selected in the request signal selection step. And a bus access method.

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