JPH07282000A - Bus interface circuit and data transfer system - Google Patents

Abstract

PURPOSE:To provide the bus interface for dealing with the data transfer system to use both the edges of leading/trailing edges by using a frequency doubling circuit for generating an internal clock at the double frequency of a source clock and a flip-flop for latching input data at the trailing edge of this internal clock. CONSTITUTION:The bus interface for connecting the common bus of (n) bits for bus width and the connecting device internal bus of (n) bits for bus width is constituted by using (n) pieces of bus interface modules 3. When inputting the data from the common bus, the internal clock provided with the double frequency of the source clock matching its phase with the source clock transmitted from the output source of data is generated and supplied to the bus interface modules 3 by a control clock generating part 4. When outputting the data to the common bus, the source clock, the internal clock subjected to frequency division to a half, is outputted to the common bus corresponding to the timing of the data output.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus interface circuit and a data transfer system used in an information processing device such as a personal computer, a workstation, an office computer or the like.

[0002]

2. Description of the Related Art In recent years, in order to process a large amount of data in an information processing apparatus, high speed data transfer between connected devices has become necessary. One method of high-speed data transfer is so-called source synchronous transfer, which transfers data at a timing synchronized with a source clock supplied by an output source during data transfer. As a bus having the source synchronous transfer means, for example, "The Proposed
SBS Lt Standard Doubles The
BME 64 Transfer Rate ", Ai
EEE Micro, April 1992, Issue 6,
Pages 4 to 71 ("The Proposed SS
BLT Standard Doubles the
VME64 Transfer Rate ": IEEE
Micro, April 1992, PP64-7
BM 64 Bus described in 1) and "The
Scalable Coherent Interface and Related Standards Projects ", IEE Micro, February 1992, pp. 10-22 (" The ScalableCo ").
herent Interface and rela
ted Standards Projects ": I
EEE Micro, February 1992, P
The SCI Ibus described in P10-22) is known. According to the source synchronization protocol of the BME64 bus or the SCI bus, both the falling edge and the rising edge of the source clock are used for data transfer.

[0003]

[Problems to be Solved by the Invention]
A bus interface that supports a data transfer method that is synchronized with either the falling edge or the rising edge of the input clock cannot support a source synchronization protocol that uses both the falling edge and the rising edge of the source clock for data transfer.

It is an object of the present invention to provide a bus interface corresponding to a data transfer method that uses both falling / rising edges of a source clock for data transfer, and use both falling / rising edges of a source clock for data transfer. It is to solve problems such as increase in power consumption due to high-speed operation, increase in influence of circuit delay, and increase in influence of clock skew due to increase in speed of distributed clock.

[0005]

According to the present invention, as one of means for providing a bus interface corresponding to a data transfer method using both falling / rising edges of a source clock for data transfer, a bus to a connected device is provided. The input side circuit of the differential circuit, the clock generator and the PLL
, And a flip-flop that latches input data at the falling edge of the internal clock, and a frequency-dividing circuit that generates an internal clock having a frequency twice that of the source clock in phase with the source clock. This input side circuit can also be configured by using a flip-flop that latches the input data to the connected device at the rising edge of the internal clock. The output side circuit from the connected device to the bus has a flip-flop that latches transfer data at the falling edge of the internal clock, and an internal clock of 1
The frequency dividing circuit is configured to generate a source clock having a frequency of / 2 and alternately output both falling and rising edges in synchronization with the timing of data transfer. This output side circuit can also be configured using a flip-flop that latches the transfer data to the bus at the rising edge of the internal clock. A bus interface was constructed by combining these input side circuits and output side circuits. However, in the bus interface having such a configuration, the inside of the connected device operates at twice the frequency of the source clock, power consumption increases, and the influence of circuit delay increases. Moreover, the influence of clock skew may be increased by distributing the high-speed clock.

Therefore, according to the present invention, there is an increase in power consumption and an influence of circuit delay and clock distribution skew which occur in the bus interface corresponding to the data transfer method using both the falling edge and the rising edge of the source clock for data transfer. As one of the means for solving the problem of increase, a bus separator for converting the source synchronous bus into a bus having a bus width twice and a data transfer frequency 1/2 times is provided on the input side from the bus to the bus input module. Configured. Further, on the output side from the connected device to the bus, a bus multiplexer that transfers the transfer data at a bus width of 1/2 and a data transfer frequency of 2 at both the falling edge and the rising edge of the source clock is provided to configure a bus output module. . A bus interface is configured using these input / output modules. There are two possible bus interfaces with this configuration, one that starts data transfer from the falling edge of the source clock and one that starts data transfer from the rising edge.

[0007]

According to the present invention, it is possible to provide a bus interface corresponding to a bus using a source synchronization protocol for transferring data by using both falling and rising edges of a source clock. In addition, a bus interface configuration that solves problems such as an increase in power consumption and an increase in the influence of circuit delay and clock distribution skew that occur in a bus interface that supports a data transfer method that uses both falling and rising edges of a source clock According to the method, the data transfer frequency can be reduced to half or less inside the final stage of the bus interface. As a result, power consumption can be reduced and the effect of circuit delay can be reduced. Further, by reducing the size of the high-speed clock distribution system, it is possible to suppress an increase in the influence of clock skew.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. 1 is a system configuration diagram showing a configuration example of a bus system according to the present invention, FIG. 2 is a block diagram showing a configuration example of a bus interface according to the present invention, and FIG. 3 is a circuit showing an example of an input side circuit of the bus interface according to the present invention. 4 is a configuration diagram, FIG. 4 is a timing chart showing an example of timing specifications of an input side circuit of a bus interface according to the present invention,
5 is a circuit configuration diagram showing an example of the output side circuit of the bus interface according to the present invention, FIG. 6 is a timing chart showing an example of timing specifications of the output side circuit of the bus interface according to the present invention, and FIG. 7 is a bus interface according to the present invention. FIG. 8 is a block diagram showing an example of the configuration of FIG.
9 is a circuit configuration diagram showing an example of an input side circuit of a bus interface according to the present invention, FIGS. 10 and 11 are circuit configuration diagrams showing an example of an input side module of a bus interface according to the present invention, and FIG. 12 is a bus according to the present invention. 13 is a timing chart showing an example of timing specifications of an input side circuit of the interface, FIG. 13 is a block diagram showing a configuration example of an output side circuit of the bus interface according to the present invention, and FIG. 14 is a circuit configuration showing an example of an output side circuit of the bus interface. FIG. 15 is a circuit configuration diagram showing an example of the output side module of the bus interface according to the present invention, and FIG. 16 is a timing chart showing an example of the timing specifications of the output side circuit of the bus interface according to the present invention.

First, the configuration of the bus system according to the present invention will be described with reference to FIG.

In FIG. 1, reference numeral 1 is a bus interface for connecting a bus and devices of this embodiment, 2 is a plurality of connection devices such as a processor, a memory, various input / output systems connected to the bus of this embodiment, Reference numeral 101 (A / D) is an n-bit address / data bus to which an address signal and a data signal are multiplexed and output, 102 (SCLK) is a source clock signal line from which the source clock is output from the connection device 2, and 103 (D ) Is an n-bit data bus input to the bus interface, 104 (Q) is an n-bit data bus output from the bus interface, 105
(T) is the source clock input to the bus interface,
Source clock output from 106 (TO) bus interface, 107 (QC), 108 (QA), 109 (Q
B) is conversion data output from the bus interface, 11
0 (TI) is a source clock input to the bus interface, and 111 (DA) and 112 (DB) are data inputs to the bus interface.

FIG. 1 is a system configuration diagram showing a configuration diagram of a bus system according to the present invention. A bus system is generally configured by connecting a plurality of connection devices 2 such as a processor, a memory, various input / output systems, etc. with a common bus. In this embodiment, the address / data multiplex bus 101 and the source clock signal line 102 are defined as common bus lines.

In FIG. 1, between a plurality of connecting devices,
Source synchronous data transfer is performed using both falling / rising edges of the source clock signal line 102.

Next, a configuration example of the bus interface in this embodiment will be described with reference to FIG.

In FIG. 2, 3 is a 1-bit bus interface module, 4 is a control clock generator for generating a clock signal for controlling the bus interface module 3, and 113 is a clock signal for controlling the operation of the bus interface module 3. is there.

FIG. 2 is a block diagram showing a configuration example of a bus interface for connecting the connection device 2 and the common bus in this embodiment. The operation of each block in FIG. 2 will be described below with reference to the block diagram of FIG.

The bus interface module 3 receives the clock signal from the control clock generator 4, latches the data input from the common bus, and outputs it to the internal bus of the connected device. It also latches the data input from the internal bus of the connected device and outputs it to the common bus. By using n of the bus interface modules 3, a bus interface for connecting a common bus having a bus width of n bits and a connection device internal bus having a bus width of n bits is configured. When inputting data from the common bus, the control clock generating unit 4 generates an internal clock having a frequency twice as high as the source clock sent in phase from the output source of the data, and the bus interface module 3 Supply to. At the time of data output to the common bus, the source clock obtained by dividing the internal clock by 1/2 is output to the common bus at the timing of data output.

The bus interface shown in FIG. 2 is constructed by combining an input side interface and an output side interface.

A specific internal circuit example of the input side bus interface and its operation will be described below with reference to FIGS. 3 and 4.

First, a configuration example of the input side circuit of the bus interface will be described with reference to FIG.

In FIG. 3, reference numeral 5 denotes a flip-flop (hereinafter referred to as rising edge trigger FF) which latches input data at the rising edge of the clock pulse, 6
Is a clock frequency doubler for generating an internal clock having a frequency twice that of the source clock T, and 114 is a clock input to the rising edge trigger FF.

FIG. 3 is a circuit diagram showing a configuration example of the input side circuit of the bus interface according to the present invention. In FIG. 3, a differentiating circuit is used for the clock frequency division unit 6, but it is also possible to generate an internal clock having a frequency twice that of the source clock T in phase with the source clock T using a clock generator and a PLL. It is possible.

FIG. 4 is a timing chart showing an example of timing specifications of the input side bus interface circuit shown in FIG.

The operation of the input side bus interface will be described below with reference to FIGS. 3 and 4.

The rising edge trigger FF5 latches the data transferred in synchronization with both falling / rising edges of the source clock T. For this purpose, an internal clock 114 having a frequency twice that of the source clock T is generated by a clock frequency dividing circuit using a differentiating circuit or a clock generator and a PLL, and is used as a clock input to the rising edge trigger FF5.

In this input side bus interface example, the data 103 is latched at the rising edge of the internal clock 114, but the data 103 can be latched at the falling edge of the internal clock 114.

Although the data transfer is started from the falling edge of the source clock T in this example on the input side, the data transfer can be started from the rising edge of the source clock T.

In the case of the above configuration, since a high speed clock is distributed to n rising edge triggers FF, the clock distribution system becomes large and the influence of clock skew may increase. In addition, the internal circuit of the connected device including the bus interface is set to 2 of the source clock T.
Since it is necessary to operate at twice the frequency, there arises a problem that power consumption increases and the influence of circuit delay increases.

Next, a specific internal circuit example of the output side bus interface and its operation will be described with reference to FIGS. 5 and 6.

First, a configuration example of the output side circuit of the bus interface will be described with reference to FIG.

In FIG. 5, 7 and 8 are rising edge triggers FF, 9 is a clock frequency divider which generates a source clock output TO having a frequency of 1/2 times the internal clock TI,
115 is a clock input to the rising edge trigger FF, 1
Reference numerals 16 and 117 are signals obtained by dividing the internal clock.

FIG. 5 is a circuit diagram showing a configuration example of the output side circuit of the bus interface according to the present invention. In FIG. 5, a rising edge trigger FF8 is used for the clock frequency dividing unit 9.

FIG. 6 is a chart showing an example of timing specifications of the output side bus interface circuit shown in FIG.

The operation of the output side bus interface will be described below with reference to FIGS. 5 and 6.

The rising edge trigger FF7 latches the data from the internal bus of the connected device and outputs the data to the common bus. Further, according to the timing, both edges of falling / rising edges of the source clock output TO generated by dividing the internal clock TI by the clock dividing unit are alternately output.

In this output side bus interface example, the data 103 is latched at the falling edge of the internal clock TI, but the data 1 is latched at the rising edge of the internal clock TI.
It is also possible to adopt a configuration in which 03 is latched.

Although the data transfer is started from the falling edge of the source clock TO in this example on the output side, the data transfer can be started from the rising edge of the source clock TO.

In the output side bus interface circuit having the above-mentioned structure, the same problem as in the input side circuit occurs. That is, there is a possibility that the influence of clock skew will increase due to the increase in the size of the high-speed clock distribution system.
In addition, it is necessary to operate the bus interface circuit at twice the frequency of the source clock, which increases power consumption,
The influence of circuit delay becomes large.

Next, a bus interface that solves these problems will be described.

The internal structure of the improved bus interface which solves the problems of power consumption and clock skew will be described below with reference to the block diagram of FIG.

In FIG. 7, 10 is a 1-bit bus interface module, 11 is a control clock generator for generating a clock signal for controlling the bus interface module 10, and 118 is a clock signal for controlling the operation of the bus interface module 10. is there.

FIG. 7 is a block diagram showing a configuration example of the bus interface 1 for connecting the connection device and the bus according to the present invention. The operation of the improved bus interface will be described below with reference to the block diagram of FIG.

The bus interface module 10 outputs the input data from the common bus to the connected device internal bus having a bus width twice and the data transfer frequency 1/2 times, and the input data from the connected device internal bus to the bus width 1 /. Output to a common bus that has twice the data transfer frequency. The n bus interface modules 10 are used to form a bus interface that connects a common bus having a bus width of n bits and a data transfer frequency f to a connection device internal bus having a bus width of 2n bits and a data transfer frequency of 1 / 2f. The control clock generator 11 supplies the control clock having the same frequency as the source clocks T, TI, TO to the bus interface module 10. That is, the bus interface module 10 operates at the same frequency as the source clocks T.TI.TO.

By using the bus interface shown in FIG. 7, it is possible to handle the bus width twice and the frequency 1/2 times inside the interface of the connected device. That is, inside this interface, data transferred at high speed can be handled by a relatively low speed circuit. As a result, problems such as an increase in power consumption and an increase in the influence of circuit delay and clock skew that occur in the configuration example of FIG. 2 in which the internal circuit of the connected device including the bus interface unit is operated at a frequency twice that of the source clock. Solvable.

The bus interface shown in FIG. 7 is constructed by combining an input side interface and an output side interface.

A specific internal circuit of the improved input side bus interface and its operation will be described below with reference to FIGS. 8 to 12.

First, the configuration of the input side circuit of the improved bus interface will be described with reference to FIG.

In FIG. 8, reference numeral 12 is a bus interface input circuit.

FIG. 8 is a block diagram showing the configuration of the input side circuit of the improved bus interface. In FIG. 8, the bus interface 12 has two inputs of the source clock T and data D and each data output of QC, QA and QB. The input side bus interface 12 synchronizes a data input D transferred in synchronization with both falling / rising edges of the source clock input T with one of falling or rising edges of the source clock input T. QA
・ Output to QB. By doing this, inside the interface, the data width of the bus is doubled and the transfer frequency is 1 /
It can be treated as double. The same output as QA is output to QC earlier by a half cycle of the source clock input T. This QC can be used for address command decoding.

Next, a specific internal circuit of the input side bus interface will be described with reference to FIG.

In FIG. 9, 13/14/15 are rising edge trigger FFs, and 119 are source clock inputs 105.
Is an inverted signal of.

FIG. 9 is a circuit diagram example of an input side bus interface according to the present invention. In FIG. 9, the data transferred when the source clock input 105 falls (the rising edge of 119) is held by the rising edge trigger FF 13, and the data transferred when the source clock input 105 rises is held by the rising edge trigger FF 14. Therefore, the number of rising edge triggers FF twice the bus width is required.
Further, since the data latched when the source clock input 105 falls is output at the same timing as the data latched when the source clock input 105 rises, a rising edge trigger FF15 is further required, which is a total of three times the bus width. The rising edge trigger FF of is required.

A specific circuit example of the input side module will be described below. The input side module is defined as a macro cell such as a gate array, and the input side bus interface is constructed by combining these macro cells.

10 and 11 are examples of specific circuit diagrams of the input side module of the improved bus interface.

In FIGS. 10 and 11, inputs S (negative polarity) and R (negative polarity) are set / reset inputs of the flip-flops, respectively.

In FIG. 10, a bus interface is constructed by combining a rising edge trigger FF and a flip-flop. Further, as shown in FIG. 11, only the master part of the rising edge trigger FF and the rising edge trigger F
It is also possible to adopt a configuration in which Fs are combined.

FIG. 12 is a timing chart showing an example of timing specifications of the input side module of the bus interface according to the present invention.

The operation of the input side circuit will be described below with reference to the module circuit diagrams of FIGS. 10 and 11 and the timing chart of FIG.

First, in the example of the module circuit of FIG. 10, data is sent to the data input D by using both the falling edge and the rising edge of the source clock input T. In order to latch this data input D with the rising edge trigger FF, two signal lines of the source clock input T and the inverted signal 119 of T are used. First, by applying the inverted signal 119 of the source clock input T to the rising edge trigger FF,
A0 transferred at the falling edge of the source clock input T
Latch A1, A2 .... This is the output QC.
Since this output QC is output earlier than the outputs QA and QB by half a cycle of the source clock input T, it can be used for applications such as address / command decoding. Next, in synchronization with the rising edge of the source clock input T, B0 and B1 transferred at the rising edge of the source clock input T
・ Latch the output QC with B2 .... And QA ・ Q
B is output at the same timing.

Next, the operation of the module circuit example shown in FIG. 11 will be described. The data output of FIG. 11 is QA and Q.
B only, no QC. The data input D is shown in FIG.
Similarly to the circuit shown in 0, data is sent in synchronization with both falling / rising edges of the source clock input T.
In synchronization with the rising edge of the inverted signal 119 of the source clock input T, A0, A1, A2, ... transferred at the falling edge of the source clock input T are latched. Next, in synchronization with the rising edge of the source clock input T, B0, B1.
Latch B2 ... and output QA and QB at the same timing.

Although the data transfer is started from the falling edge of the source clock input T here, the data transfer can be started from the rising edge of the source clock input T.

The input side module as described above is defined in a macro cell such as a gate array, and by combining them, the input side circuit of the improved bus interface is constructed.

Next, a specific internal circuit of the improved output side bus interface and its operation will be described with reference to FIGS.

First, the configuration of the output side circuit of the improved bus interface will be described with reference to FIG.

In FIG. 13, 10 is a bus interface output circuit.

FIG. 13 is a block diagram showing the structure of the output side circuit of the bus interface according to the present invention. In FIG. 13, the bus interface 10 has a source clock TI.
And three inputs of data DA and DB, and two outputs of data Q and source clock TO. Data is transferred to the data inputs DA and DB of the output side bus interface 10 by using one of the falling edge and the rising edge of the source clock input TI. These data are alternately output to Q, such as DA when the source clock output TO drops and DB when it rises. By doing so, it is possible to interface the source device bus with the internal bus of the connected device having twice the data width and 1/2 the transfer frequency.

Next, a specific internal circuit of the output side bus interface will be described with reference to FIG.

In FIG. 14, 17 and 18 are rising edge triggers FF, and 120 is an inverted signal of the source clock input TI.

FIG. 14 is a circuit diagram of an output side bus interface according to the present invention. In FIG. 14, data is transferred to the data inputs DA and DB using either the falling edge or the rising edge of the source clock input TI. The rising edge trigger FF17 latches the data input to DA when the source clock input TI falls, and the rising edge trigger FF18 latches the data input to DB when the source clock input TI rises,
In order to alternately output DA and DB to Q, twice as many rising edge triggers FF as the bus width are required.

The circuit of the output side module in which the number of gates used for this output side circuit is optimized will be described below. The output side module is defined as a macro cell such as a gate array, and the output side bus interface is configured by combining these macro cells.

FIG. 15 is an example of a concrete circuit diagram of the output side module of the bus interface in the present invention.

In FIG. 15, input S (negative polarity) .R
Each (negative polarity) is a set / reset input of the rising edge trigger FF.

FIG. 16 is a timing chart showing an example of timing specifications of the output side module of the bus interface according to the present invention.

The module circuit diagram of FIG. 15 and FIG.
The operation of the input side circuit will be described with reference to the timing chart of FIG. Data is transferred to the data inputs DA and DB using the falling edge of the source clock input TI. These data inputs DA / DB are rising edge trigger FF
To alternately latch using, two signal lines of the source clock input TI and the inverted signal 120 of TI are used.
When the source clock input TI falls (TI inverted signal 12
Latches A0, A1, A2, ...
Output to Q via the state buffer. Next, when the source clock input TI rises, B0, B1, B2, ... Are latched and output to Q via a 3-state buffer.
Further, a source clock input TI with a delay is referred to as a source clock output TO. By doing this,
When the source clock output TO drops, A0, A1, A2 ...
, And B0, B1, B2, ... Can be transferred at the time of rising. By using this bus interface, it is possible to connect to an external common bus having a bus width 1/2 times and a transfer frequency 2 times that of the internal bus of the connected device. This output side module can also be realized by using a selector instead of the 3-state buffer.

Here, the data transfer is started from the falling edge of the source clock TI.TO, but the data transfer can be started from the rising edge of the source clock TI.TO.

The output side module as described above is defined in a macro cell such as a gate array, and by combining these, the output side circuit of the improved bus interface is constructed.

As described above, the improved bus interface corresponding to the source synchronization protocol for transferring data by using both the falling edge and the rising edge of the source clock is constructed by combining the macrocells, thereby reducing the power consumption of the bus system. Can be reduced and the influence of circuit delay can be reduced. Further, it is possible to suppress an increase in the influence of clock skew.

[0077]

According to the present invention, it is possible to realize a bus interface compatible with a source synchronization protocol for transferring data at both falling and rising edges of a source clock. In the present invention, as an example of the configuration of this bus interface, the input side circuit from the bus to the connection device has a frequency twice as high as the source clock in phase with the source clock using a differentiating circuit or a clock generator and a PLL. It is composed of a frequency doubler circuit that generates an internal clock and a flip-flop that latches input data at the falling edge of the internal clock. This input side circuit can also be configured by using a flip-flop that latches the input data to the connected device at the rising edge of the internal clock. In addition, the output side circuit from the connected device to the bus generates a flip-flop that latches the transfer data at the falling edge of the internal clock and a source clock having a frequency that is ½ times the frequency of the internal clock to generate the data transfer timing. In addition, a frequency divider circuit that alternately outputs both falling and rising edges is used. This output side circuit can also be configured using a flip-flop that latches the transfer data to the bus at the rising edge of the internal clock. A bus interface was constructed by combining these input side circuits and output side circuits. However, in the bus interface having such a configuration, the inside of the connected device operates at twice the frequency of the source clock, power consumption increases, and the influence of circuit delay increases. Moreover, the influence of clock skew may be increased by distributing the high-speed clock.

Therefore, in the present invention, the power consumption generated in the bus interface corresponding to the source synchronization protocol for transferring the data at both the falling edge and the rising edge of the source clock and the influence of the circuit delay and clock distribution skew are increased. As one of the means for solving such a problem, on the input side from the bus to the connected device, a bus separator for converting the source synchronous bus into a bus having a bus width twice and a data transfer frequency 1/2 is provided, and a bus input module is provided. Configured.
Further, on the output side from the connected device to the bus, a bus multiplexer that transfers the transfer data at a bus width of 1/2 and a data transfer frequency of 2 at both the falling edge and the rising edge of the source clock is provided to configure a bus output module. . A bus interface is configured using these input / output modules. There are two possible bus interfaces with this configuration, one that starts data transfer from the falling edge of the source clock and one that starts data transfer from the rising edge. With the above configuration, the data transfer frequency can be reduced to half or less inside the final stage of the bus interface. As a result, the power consumption of the bus system can be reduced and the influence of circuit delay can be reduced. Further, by reducing the size of the high-speed clock distribution system, it is possible to suppress an increase in the influence of clock skew.

[Brief description of drawings]

FIG. 1 is a system configuration diagram showing a configuration example of a bus system according to the present invention.

FIG. 2 is a block diagram showing a configuration example of a bus interface according to the present invention.

FIG. 3 is a circuit configuration diagram showing an example of an input side circuit of a bus interface according to the present invention.

FIG. 4 is a timing chart showing an example of timing specifications of an input side module of a bus interface according to the present invention.

FIG. 5 is a circuit configuration diagram showing an example of an output side circuit of a bus interface according to the present invention.

FIG. 6 is a timing chart showing an example of timing specifications of an input side module of a bus interface according to the present invention.

FIG. 7 is a block diagram showing a configuration example of a bus interface according to the present invention.

FIG. 8 is a block diagram showing a configuration example of an input side circuit of a bus interface according to the present invention.

FIG. 9 is a circuit configuration diagram showing an example of an input side circuit of a bus interface according to the present invention.

FIG. 10 is a circuit configuration diagram showing an example of an input side module of a bus interface according to the present invention.

FIG. 11 is a circuit configuration diagram showing an example of an input side module of a bus interface according to the present invention.

FIG. 12 is a timing chart showing an example of timing specifications of an input side module of a bus interface according to the present invention.

FIG. 13 is a block diagram showing a configuration example of an output side circuit of a bus interface according to the present invention.

FIG. 14 is a circuit configuration diagram showing an example of an output side circuit of a bus interface according to the present invention.

FIG. 15 is a circuit configuration diagram showing an example of an output side module of a bus interface according to the present invention.

FIG. 16 is a timing chart showing an example of timing specifications of an output side module of a bus interface according to the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Bus interface unit, 2 ... Bus connection device, 3 ... Bus interface module, 4 ... Bus interface module control clock signal generation block, 5, 7, 8, 13, 14, 15, 17, 18 ... Rising edge trigger flip-flop , 6 ... Clock frequency division unit, 9 ... Clock frequency division unit, 10 ... Bus interface module, 11 ... Bus interface module control clock signal generation block, 12 ... Bus interface input side module, 16 ... Bus interface output side module, 101 ... Address / data multiplexing line, 102 ... Source clock signal line, 103 ... Bus interface input data bus, 104 ... Bus interface output data bus, 105 ... Bus interface input source clock, 106 ... Bus Interface output source clock, 107, 108, 109 ... Bus interface output data signal, 110 ... Bus interface source clock input, 111, 112 ... Bus interface input data signal, 113, 118 ... Bus interface module input clock signal, 114, 115 ... rising edge trigger FF input clock signal, 116, 117 ... Source clock output, 119 ... Bus interface input source clock (inverted), 120 ... Bus interface source clock input (inverted).

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Mikio Yamagishi 2326 Imai-cho, Ome-shi, Tokyo Hitachi, Ltd. Device Development Center

Claims (17)

[Claims] 1. A bus interface circuit used for a system bus or the like of an information processing apparatus, wherein a clock line for inputting an input clock and n bits transferred in synchronization with both rising and falling edges of the input clock. Input data, the first holding means for latching and holding the n-bit data input at the rising edge of the input clock, and the n-bit data input at the falling edge of the input clock. And a second holding means for holding the same, and first and second output lines for outputting n-bit data from the first holding means and the second holding means, respectively. Interface circuit. 2. The third holding means according to claim 1, wherein the n-bit data output from the first holding means to the first output line is latched in synchronization with the timing of the falling edge of the input clock. And a third output line for outputting n-bit data from the third holding means. 3. The third holding means according to claim 1, wherein the n-bit data output from the second holding means to the second output line is latched in synchronization with the rising edge timing of the input clock. And a third output line for outputting n-bit data from the third holding means. 4. A bus interface circuit used for a system bus of an information processing apparatus, wherein a clock line for inputting an input clock and n bits transferred in synchronization with both rising and falling edges of the input clock. Input data for inputting data, clock generation means for generating an internal clock having a frequency twice that of the input clock, phase synchronization means for matching the phases of the input clock and the internal clock, and input to the input line A bus interface circuit comprising: holding means for latching the generated n-bit data at a rising edge of the internal clock; and an output line for outputting the n-bit data from the holding means. 5. A bus interface circuit used for a system bus or the like of an information processing apparatus, wherein a clock line for inputting an input clock and n bits transferred in synchronization with both rising and falling edges of the input clock. Input data for inputting data, clock generation means for generating an internal clock having a frequency twice that of the input clock, phase synchronization means for matching the phases of the input clock and the internal clock, and input to the input line A bus interface circuit comprising: holding means for latching the generated n-bit data at a falling edge of the internal clock; and an output line for outputting the n-bit data from the holding means. 6. A bus interface circuit used for a system bus of an information processing device, comprising a clock line for inputting an input clock and n-bit data transferred in synchronization with a rising edge of the input clock. First and second input lines for inputting, and first holding means for latching and holding the n-bit data input to the first input line in synchronization with the timing of the rising edge of the input clock. Second holding means for latching and holding the n-bit data input to the second input line in synchronization with the timing of the falling edge of the input clock, the first holding means, and the second holding means. Holding means for outputting the n-bit data respectively, and the n-bit data output to the first output line is used for the rising edge of the input clock. Selecting means for outputting the n-bit data output to the second output line at the rising edge of the inverted signal of the input clock, and a third means for outputting the n-bit data from the selecting means. An output line, an output clock generation unit that outputs a clock having the same frequency as the input clock in synchronization with the timing when the selection unit outputs n-bit data to the third output line, and the output clock generation unit. A bus interface circuit having a clock line for outputting an output clock from the means. 7. A bus interface circuit used for a system bus of an information processing apparatus, comprising a clock line for inputting an input clock and n-bit data transferred in synchronization with a falling edge of the input clock. First and second input lines to be input, and first holding means for latching and holding the n-bit data input to the first input line in synchronization with the timing of the falling edge of the input clock. Second holding means for latching and holding the n-bit data input to the second input line in synchronization with the timing of the rising edge of the input clock;
First and second output lines for outputting n-bit data from the first holding means and the second holding means, respectively.
Selecting means for outputting the n-bit data output to the output line of 1) at the timing of the falling edge of the input clock and the n-bit data output to the second output line for the rising edge of the input clock. A third output line for outputting n-bit data from the selecting means, and the same frequency as the input clock in synchronization with the timing at which the selecting means outputs n-bit data to the third output line. And a clock line for outputting an output clock from the clock generating means. 8. A bus interface circuit used for a system bus or the like of an information processing apparatus, wherein a clock line for inputting an input clock and n-bit data transferred in synchronization with a rising edge of the input clock are input. Input line, holding means for latching and holding the n-bit data input to the input line in synchronization with the timing of the rising edge of the input clock, and an output for outputting n-bit data from the holding means. Line and one of the input clocks
A clock generating means for generating an output clock having a frequency of / 2 and outputting the output clock in synchronization with the timing at which the holding means outputs n-bit data to the output line; A bus interface circuit having a clock line for outputting an output clock. 9. A bus interface circuit used for a system bus or the like of an information processing apparatus, wherein a clock line for inputting an input clock and n-bit data transferred in synchronization with a falling edge of the input clock are input. Input line, holding means for latching and holding n-bit data input to the input line in synchronization with the timing of the falling edge of the input clock, and output for outputting n-bit data from the holding means. Line and 1/2 of the input clock
A clock generating unit that generates an output clock having a doubled frequency and outputs the output clock in synchronization with the timing at which the holding unit outputs n-bit data to the output line; and an output clock from the clock generating unit. A bus interface circuit characterized by having a clock line for outputting. 10. A data transfer system used in an information processing apparatus, wherein the circuit on the input side from the common bus is used.
The bus interface circuit according to claim 6 is provided in a connecting device with a bus interface that uses the bus interface circuit according to claim 6 as an output side circuit to a common bus, and the data transfer method is a clock synchronization method. And data transfer system. 11. A data transfer system used in an information processing apparatus, wherein the input side circuit from the common bus is connected to the data transfer system.
The bus interface circuit according to claim 7 is provided in a connection device with a bus interface that uses the bus interface circuit according to claim 7 as an output side circuit to a common bus, and the data transfer method is a clock synchronization method. And data transfer system. 12. A data transfer system used in an information processing apparatus, wherein the input side circuit from the common bus is connected to the data transfer system.
A bus interface circuit according to claim 8 is provided in a connection device with a bus interface that uses the bus interface circuit according to claim 8 as an output side circuit to a common bus, and a data transfer system is a clock synchronization system. And data transfer system. 13. A data transfer system used in an information processing apparatus, wherein the input side circuit from the common bus is connected to the data transfer system.
The bus interface circuit according to claim 9 is provided in a connecting device with a bus interface using the bus interface circuit according to claim 9 as an output side circuit to a common bus, and the data transfer method is a clock synchronization method. And data transfer system. 14. A data transfer system used in an information processing apparatus, wherein the input side circuit from the common bus is connected to the data transfer system.
The bus interface circuit according to claim 6 is provided in a connection device with a bus interface using the bus interface circuit according to claim 6 as an output side circuit to a common bus, and the data transfer method is a source synchronous method. And data transfer system. 15. A data transfer system used in an information processing apparatus, wherein the input side circuit from the common bus is connected to the data transfer system.
A bus interface circuit using the bus interface circuit according to claim 7 is provided in a connection device, and the data transfer method is a source synchronization method. And data transfer system. 16. A data transfer system used in an information processing apparatus, wherein the circuit on the input side from the common bus is used.
The bus interface circuit according to claim 8 is provided in a connection device with a bus interface that uses the bus interface circuit according to claim 8 as an output side circuit to a common bus, and the data transfer method is a source synchronous method. And data transfer system. 17. A data transfer system used in an information processing apparatus, wherein the input side circuit from the common bus is connected to the data transfer system.
The bus interface circuit according to claim 9 is provided in a connection device with a bus interface that uses the bus interface circuit according to claim 9 as an output side circuit to a common bus, and the data transfer method is a source synchronous method. And data transfer system.