WO2004003758A1

WO2004003758A1 - Directional coupling bus system

Info

Publication number: WO2004003758A1
Application number: PCT/JP2003/008356
Authority: WO
Inventors: Hideki Osaka; Satoshi Isa; Toshio Sugano
Original assignee: Hitachi, Ltd.; Elpida Memory, Inc.
Priority date: 2002-07-01
Filing date: 2003-07-01
Publication date: 2004-01-08
Also published as: JPWO2004003758A1; JP4410676B2

Abstract

In a system having a board on which a memory module in which a plurality of memories are mounted and a memory controller which controls the memory module are mounted, a register is provided that is used to transfer a data signal between the memory controller and the memory module by separating them in dc mode using a main transmission line and a sub transmission line via a directional coupler and by connecting them in a first form in ac mode; to transfer a command and an address signal between the memory controller and the memory module by connecting them in the first form or in second form in dc mode and ac mode; and to transfer the command and the address signal to the plurality of memories. The directional coupler and the register are mounted in the memory module or on the board. This configuration increases the data transfer rate of the command and address busses.

Description

Description Directional connection type path system

The present invention relates to a signal transmission technique between elements such as a multiprocessor and a memory in an information processing apparatus (for example, between digital circuits constituted by CMOS or the like or a function block thereof). The present invention relates to technology for speeding up data transfer on a bus connected to a computer. In particular, the present invention relates to a system using a bus connecting a memory controller and a plurality of memory modules. Background art

In a memory system in which a plurality of devices are connected on a transmission line connecting a memory controller (hereinafter referred to as MC) and a terminating resistor, a data signal transferred in both directions between the MC and the memory uses a clock. There is a memory system using DDRSDRAM (Double Data Rate Synchronous DRAM), which has a data transfer rate twice the frequency. Hereinafter, this memory system is referred to as a DDR memory system. In this DDR memory system, the command signal indicating the state of read / write and the address signal indicating the address to be accessed, which is transferred in one direction from the MC to the memory, have the same data transfer speed as the clock frequency, That is, it has a data transfer rate of 1 Z 2 of the data signal.

One of the bus methods for realizing this DDR memory system is a method called SSTL (Stub Series Terminated Logic). Figure 24 shows the configuration when the command and address bus and data path are both SSTL. This memory system includes a board 100, a plurality of memory modules (hereinafter, abbreviated as modules) 20 on which a plurality of memories 10 are mounted, and a plurality of connectors 5 for connecting the board and the module. 0, an MC 1 having a memory control mechanism, a plurality of registers 2 for transferring command and address signals to a plurality of memories on the module 20, and a plurality of resistance elements 6 0 called stub resistors. And transmission seen from MC 1 A not-shown terminating resistor 61, which is arranged at the farthest end of the line and is connected to an appropriate terminating voltage V tt, a data path 40 comprising a plurality of wirings having branches, and an address and command bus 30 And a memory bus consisting of

For convenience of explanation, Fig. 24 shows one bus wiring, four modules and one register and four memories on each module. There are multiple paths depending on the width, modules not limited to four, and multiple devices not limited to one register and four memories on each module. The plurality of memories may be mounted on the front and back of the module. FIG. 24 shows a memory module in which a signal is transferred to a memory through a register, that is, a memory module called a registered DIMM (Dual In-line Memory Module). This: Registered DIMMs usually have a device called a PLL (Phase Locked Loop) that has the function of distributing clock signals to register 2 on module 20 and multiple memories 10. Not shown for simplicity.

In addition, a method for increasing the data transfer speed of the bus compared to the SSTL is disclosed in, for example, Japanese Patent Application Laid-Open No. 2000-2506772 (US Patent Application No. 09Z8003148). Memory Module ”. Although there is no general name for this method, it is referred to as SLT (Stub Less Terminated Logic) for convenience of description in this specification.

Figure 25 shows the configuration when the command and address bus and data bus are both SLT. The memory system includes a board 100, a plurality of modules 20, a plurality of connectors 50 for connecting the ports 100 and the modules 20, an MC 1, and a module And a plurality of registers 2 for transferring command and address signals to a plurality of memories (not shown) arranged at the farthest end of the transmission line viewed from MC 1 and connected to an appropriate termination voltage V tt It consists of a terminating resistor and a data bus 40 consisting of a one-stroke line without branches and a memory bus consisting of an address and command bus 30. As is clear from the figure, the transmission lines on the data bus 40 and the address and command bus 30 have no branches. In addition, impedance matching is performed as a lumped constant circuit near the device near memory 10 and register 2. PT / JP2003 / 008356

By taking this, signal reflection can be significantly suppressed as compared with the SLT. For this reason, it is possible to increase the data transfer speed of the path in S L も compared to the S S TL described above.

Further, a method for increasing the bus transfer rate over the SLΤ is disclosed in, for example, Japanese Patent Application Laid-Open No. 07-141,079 (US Pat. No. 5,636,042) “Non-contact path”. And Japanese Patent Application Laid-Open No. 2000-072787 (US patent application Ser. No. 09-5696976). In this specification, this transfer method is referred to as XTL (Crosstalk Transfer Logic) for convenience of explanation.

FIG. 26 shows a configuration diagram in the case where the command and address buses are the above-mentioned S STL and the data path is the XTL. The memory system includes a port 100, a plurality of modules 20, a plurality of connectors 50 for connecting the board 100 and the module 20, an MC 1, and a main transmission extending from the MC 1. A data path 40 as a line, a terminating resistor (not shown) arranged at the farthest end of the main transmission line viewed from the MC 1 and connected to an appropriate terminating voltage V tt, and a sub-transmission extending from the memory 10 A data bus 41 as a line, and a termination terminal (not shown) arranged at the farthest end of the sub-transmission line as viewed from their memories 10 and connected to an appropriate termination voltage V tt, and inductive and capacitance It is composed of a directional coupler 70 for separating the main transmission line and the sub transmission line in a DC manner and connecting them alternately by sexual coupling.

Note that this configuration merely shows one form of XTL, and the form for implementing XTL is not limited to this. The state of signal transmission in the XTL is as described in Japanese Unexamined Patent Application Publication No. 07-141799 “Non-contact bus”, but will be briefly described here.

The data signal output from MC 1 propagates on main transmission line 40. When the signal reaches the directional coupler 70, a backward crosstalk signal toward the memory 10 is generated on the sub-transmission line 41 by the function of the directional coupler 70. Normally, in the crosstalk, a forward crosstalk signal toward the terminating resistance direction on the sub-transmission line 41 is also generated, but by forming the directional coupler with a strip line, the forward crosstalk signal is generated. Can be prevented. Now, as shown in FIG. 27, the signal transmitted on the sub transmission line 41 is the NRZ transmitted on the main transmission line. Each memory 10 is reached in the state of an RTZ (Return To Zero) signal (B) having a shape obtained by differentiating the (No Return to Zero) signal (A). The RTZ signal is supplied to the memory 10 by, for example, an input circuit 4 ′ shown in FIG. The signal is detected and output at 5 (C), and is restored to the original NRZ signal (D) at the demodulation circuit 6. Since the input portion of the memory 10 is not terminated, the signal reaching the memory 10 is almost totally reflected and returns to the directional coupler 70 again. However, since the reflected wave is absorbed by a terminal resistor (not shown), multiple reflection does not occur on the sub-transmission line 41. As described above, in the XTL, the main transmission line and the sub transmission line are connected DC-separated and AC-connected via a directional coupler, and each transmission line without a branch is a distributed constant circuit. By performing impedance matching, the speed of path data transfer can be increased as compared with the SSTL and SLT described above. Disclosure of the invention

In the first conventional example, the signal is reflected at each branch point of the transmission line due to the impedance mismatch due to the branch wiring and the branch due to the transfer method using the SSTL. Stub resistors are installed to suppress signal reflection at those points, but it becomes difficult to suppress reflections as the signal frequency increases, and signal quality deteriorates due to multiple reflection of signals. As a result, there is a problem that the increase in data transfer speed is limited. On the other hand, in the second conventional example, since the transfer method is based on SLT, there is no branch such as SSTL in the transmission line, so that the signal quality can be improved as compared with SSTL. However, although there is no branch in the transmission line, impedance mismatching occurs for signals in the frequency domain where it is necessary to handle the area where impedance matching is performed as a lumped constant circuit as a distributed constant circuit. For this reason, there is a problem that the increase in the data transfer rate is limited even if this SLT is used. Further, in the third conventional example, the data bus employs a transfer method based on XTL, so that the speed of data transfer on the bus can be reduced as compared with the above-mentioned SSTL or SLT. Since the transfer method by SSTL is adopted, there is a problem that this limits the data transfer rate of the memory system overnight. JP2003 / 008356

there were. To summarize the above, in the first conventional example, the data transfer speed of both the command and address buses and the data bus is limited by the SSTL transfer method, and in the second conventional example, the data transfer speed of the data path is limited. In the third conventional example, the data transfer speed of the command and the address path is limited by the SSTL transfer method, thereby increasing the data transfer speed of the entire memory system. There is a problem that is limited.

An object of the present invention is to provide a memory system capable of speeding up data transfer.

Another object of the present invention is to provide a low-cost memory system capable of speeding up data transfer by reducing the number of command and address bus lines between a memory controller and a register.

In order to achieve the above object, the present invention provides a data bus comprising a main transmission line and a sub transmission line which are separated by direct current and connected in an alternating current manner via a directional coupler, and have a command and an address. The bus is characterized by having a register between the memory controller (MC) and the memory, and transferring signals to a plurality of memories via the register.

In the preferred example (first example) relating to the transfer of the command and the address bus, the MC and the register are connected by one-stroke wiring without branching. As a result, the data transfer rate of the command and address buses is not limited by the STLS, and the data transfer rate of the data bus is not limited by the SLT. As a result, it is possible to construct a memory system that can perform data transfer faster than before.

In a preferred example (second example) relating to the transfer of the command and the address path, a signal is transferred by a main transmission line and a sub transmission line which are separated in DC and connected in AC through a directional coupler. Things. As a result, the data transfer speed of the memory system can be increased as compared with the case where the transfer method according to the first example is used. Further, in a preferred example (third example) relating to the transfer of the command and the address path, the MC and the first register are connected one-to-one by a plurality of wirings without branching, Similarly, multiple wiring without branch between registers T / JP2003 / 008356

Signals are transferred in a one-to-one connection, and their registers are mounted on a port or module, and the signals are transferred to a plurality of memories via the registers. As a result, with respect to the command and the address path, it is possible to speed up data transfer as compared with the case where the transfer method according to the second example is used. In this case, the data transfer rate of the entire memory system is limited by the data transfer rate of the data bus. That is, the data transfer rate of the memory system is the same as that of the transfer method according to the second example, and the data transfer rate of the memory system is higher than that of the transfer method of the first example. Is possible.

Further, in order to achieve another object of the present invention, the data bus is a transfer method using a main transmission line and a sub transmission line which are separated in direct current and connected in alternating current via a directional coupler. , The command and address buses have a register between the MC and the memory, and transfer signals to a plurality of memories via the register. In addition, the transfer rate of the data signal on the data bus (the first data rate) The command and address signals are multiplexed (MUX) in the MC, and the second data transfer rate of the command and address signals transferred to the register is the same as the first data transfer rate. Or by doubling the speed and demultiplexing (DEMUX) in the register, so that the third command and address signal transferred from the register to multiple memories can be obtained. The chromatography data transfer rate, and Toku徵 that urchin configured by a 1/2 of the first data transfer rate. This makes it possible to reduce the number of command and address bus lines on the board to a minimum of 12 or 1Z4. In this case, the number of output units corresponding to the reduced number of wirings is not required in the MC, and the number of poles and the chip area of the MC are reduced, so that the manufacturing cost of the MC can be reduced. Further, in a memory that occupies most of the devices constituting the memory system, the data transfer speed of the command and the address signal may be the same as the conventional one, so that there is an effect that the cost is not increased by this. BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is a diagram illustrating a configuration of a memory path system according to the first embodiment.

FIG. 2 shows a memory bus system according to the first embodiment when there are no empty slots. They are a side view (a) and a circuit diagram (b).

FIG. 3 is a side view (a) and a circuit diagram (b) when there is an empty slot in the first embodiment.

FIG. 4 is a diagram illustrating a configuration of a memory path system according to the second embodiment.

FIG. 5 is a side view (a) and a circuit diagram (b) when there is no empty slot in the second embodiment.

FIG. 6 is a side view (a) and a circuit diagram (b) when there is an empty slot in the second embodiment.

FIG. 7 is a diagram illustrating a configuration of a memory bus system according to the third embodiment.

FIG. 8 is a side view (a) and a circuit diagram (b) when there is no empty slot in the third embodiment.

FIG. 9 is a side view (a) and a circuit diagram (b) when there is an empty slot in the third embodiment.

FIG. 10 is a diagram showing a configuration of a memory path system according to the fourth embodiment.

FIG. 11 is a side view (a) and a circuit diagram (b) of the fourth embodiment when there is no empty slot.

FIG. 12 is a side view (a) and a circuit diagram (b) of the fourth embodiment when there is an empty slot.

FIG. 13 is a side view (a) and a circuit diagram (b) of the fifth embodiment when there is no empty slot.

FIG. 14 is a side view (a) and a circuit diagram (b) of the fifth embodiment when there is an empty slot.

FIG. 15 is a side view (a) and a circuit diagram (b) of the sixth embodiment when there is no empty slot.

FIG. 16 is a side view (a) and a circuit diagram (b) of the sixth embodiment when there is an empty slot.

FIG. 17 is a diagram showing the configuration of the memory bus system according to the seventh embodiment.

FIG. 18 is a diagram illustrating signal multiplexing and demultiplexing.

FIG. 19 is a circuit diagram of 2: 1 multiplexing and 1: 2 demultiplexing of a signal. FIG. 20 is a diagram showing the configuration of the memory bus system according to the eighth embodiment. FIG. 21 is a diagram showing the configuration of the memory path system according to the ninth embodiment. FIG. 22 is a circuit diagram of the signal for 4: 1 multiplexing and 1: 4 demultiplexing.

FIG. 23 is a diagram showing the configuration of the memory bus system according to the ninth embodiment. FIG. 24 is a diagram showing a memory path system in the first conventional example.

FIG. 25 is a diagram showing a memory path system in a second conventional example.

FIG. 26 is a diagram showing a memory path system in a third conventional example.

FIG. 27 is a diagram illustrating a signal transmitted through the directional coupler.

FIG. 28 is a diagram illustrating a receiver for an RTZ signal. BEST MODE FOR CARRYING OUT THE INVENTION

The first embodiment will be described with reference to the configuration diagram of FIG. FIG. 1 shows components and wiring constituting the memory bus. The board 100 is a board on which components constituting the memory system are mounted, and the MC 1 having a memory control mechanism is mounted on the port 100. Reference numeral 20 denotes a module on which a plurality of memories 10 are mounted. The memory is, for example, a DRAM. Module 20 has terminals for power and ground, and signal terminals for data signals, command and address signals, and clock signals. FIG. 1 shows one bus wiring, four modules 20 and one register 2 and four memories 10 on each module. The number of a plurality of bus lines according to the width, the number of modules 20, the number of registers and memories mounted on each module 20, and the like are not limited thereto. The plurality of memories 10 may be mounted on the front and back of the module 20. This is the same including the following embodiments.

Reference numeral 40 denotes a data bus extending from the MC 1 as a main transmission line, and a data bus 41 extending as a sub transmission line extending from the memory 10 via a directional coupler 70 surrounded by a round dotted line; DC separated and AC 'connected. Reference numeral 70 in FIG. 1 denotes one of the directional couplers formed on the board 100. The directional coupling line has two parallel lines having a finite length, that is, a main coupling line and a sub coupling line. Consists of tracks. Board 100 is a directional coupler that works in the same way for data signals to other memories. , But these are not shown for simplicity. The far end of the data path 40 of the main transmission line is matched and terminated by a terminating resistor (not shown). The data path 41 as a sub-transmission line is connected to a data signal terminal of each module 20 via a connector 50, and the other end is matched and terminated by a resistor (not shown). 30 is a command and address path. The command and address path 30 is connected from the MC 1 to each module 20 by a single-stroke line without branch, and is arranged at the farthest end of the transmission line viewed from the MC 1 and has an appropriate termination voltage V tt. Are matched and terminated by a not-shown resistor connected to.

Although not shown in FIG. 1 as in the conventional example, a clock signal is wired from MC 1 to each module 20. Conventionally, in the above-described Registered DIMM, the clock signal is distributed from the MC 1 to a device called a PLL (not shown) on each module 20, and a device called a register 2 on the module 20 is passed through the device. And a clock is distributed to each memory 10. In this case, since the clock signal is a special signal, the clock signal may be transmitted by the same method as the command for each module 20 and the address bus 30 or may be transmitted by a completely different method. In this embodiment, 2 is referred to as a register (similarly in the following embodiments). However, when a clock signal is included in 30, it is assumed that register 2 has a function equivalent to the above-described PLL. .

Further, in this embodiment (similarly in the following embodiments), there is no limitation on the method of transferring the command and the address signal on the module and the master signal from the register 2 or PLL to each memory 10. If there is no problem in operation, a conventional transfer method as shown by module 20 in FIG. 24 may be used, or a transfer method in which one-stroke wiring without branch and its end are matched and terminated. But it's fine. Further, if possible, a transfer method in which the data is transmitted from the register 2 or PLL to each memory 10 on a one-to-one basis may be adopted. That is, in the present invention, the transfer method from the register or PLL to each memory does not matter. This is the same as in the following embodiments.

The transfer method of the data bus 40 corresponds to the above-described XTL, and the transfer method of the command and address bus 30 corresponds to the above-described SLT. In this case, SSTL does not limit the data transfer rate for the command and address paths. For the data bus, the data transfer rate is not limited by SLT. However, the number of terminals of the module or connector is increased by about 20% from the number of terminals of the first conventional example. In other words, at present, the number of terminals of modules and connectors is about 1 Z4, including command and address signals and power and ground terminals that also serve as an electrical shield for them. By changing the path to SLT, each of these signals needs to be introduced and derived in the module, requiring twice as many terminals as the command and address buses. However, when viewed as a whole, the total number of terminals only increases by about 20%, and this increase is of little concern.

Next, the case where there is no empty slot in the memory module 20 and the case where there is an empty slot in the memory path system according to the first embodiment will be described with reference to FIGS. 2 and 3, (a) and (b) are a side view and a circuit diagram relating to the command and address bus corresponding to FIG.

Fig. 2 shows the case where there is no empty slot, and Fig. 3 shows the case where there is an empty slot. Elements having the same functions as those in FIG. 1 are denoted by the same reference numerals. In FIG. 2 (b) and FIG. 3 (), the module 20 and the connector 50 are indicated by dotted lines to improve visibility. Note that the wiring connection is the same as in Fig. 1, but the explanation will focus on the parts not explicitly shown in Fig. 1.

The command and address path 30 is drawn from MC 1 and is matched and terminated by the resistor 61 at the farthest end. MC 1 and each register 2 are connected by a signal wiring 30 without branch. In Fig. 3 (b), there are no devices such as register 2 memory in the vacant third slot, and multiple wirings without branching for command and address signals between the second and fourth slots. A dummy memory module 21 has been inserted for connection.

As described above, in the first embodiment, a special dummy memory module is required when there is an empty slot, but the input / output signal is assumed to be the conventional NRZ signal in the register. A memory system that can speed up data transfer because it does not need to have a dedicated interface for XTL that handles RTZ signals and can use the existing registers as they are. System can be constructed at low cost.

A second embodiment will be described with reference to the configuration diagram of FIG. The difference from the first embodiment is that the transfer method of the command and address path 30 is XTL in the second embodiment.

The command and address bus 30 as a main transmission line and the command and address bus 31 as a sub-transmission line are separated DC and connected AC through a directional coupler 70. Command and address bus signals are transferred from the MC 1 to each register 2 on the module 20 via the directional coupler 70. Pod 100 is equipped with a directional coupler that performs the same function for commands and address signals to other registers and for data signals to other memories. Therefore, it is not shown in the figure.

Further, similarly to the first embodiment, a PLL (not shown) dedicated to the clock signal may be provided on the module 20.However, devices such as the register 2 and the PLL in the second embodiment include: It has the function of detecting the input XTL RTZ signal and restoring the NRZ signal, and transmitting the restored signal to each memory. For example, the receiver is realized by the receiver 4 'shown in FIG.

The transfer method of the data bus 40 corresponds to XTL, and the transfer method of the command and address path 30 corresponds to XTL. For this reason, in the second embodiment, the command and address buses are not limited by the SLT data transfer speed, so that the data transfer can be performed at a higher speed than in the first embodiment. Further, the number of terminals of the module @ connector can be the same as that of the first conventional example.

Next, in this embodiment, the case where there is an empty slot will be described with reference to FIGS. 5 and 6, which are a side view (a) and a circuit diagram (b) of a command and an address bus corresponding to FIG. . Fig. 5 shows the case where there is no empty slot, and Fig. 6 shows the case where there is an empty slot.

The command and address bus 30 as the main transmission line is drawn from the MC 1 and is matched and terminated at the farthest end by the resistor 61. Command and address signals are transferred between the MC 1 and each register 2 via the directional coupler 70 and the connector 50. Command and address path as sub-transmission line 3 1 All sides are matched-terminated with resistors 62. Here, “forward” refers to the direction in which signals flow through the main transmission line. In the vacant third slot shown in FIG. 6B, the command and address buses as the auxiliary transmission lines have the open ends at the connector 50 opposite to the terminating resistor 62. However, even if the slot is not empty, the input part of the register 2 is not terminated, so it is effectively an open end, and the state does not change. Similarly, since the data path is also an XTL transfer method, other slots are not affected even if there is an empty slot.

As described above, in the second embodiment, no special control or parts are required even when an empty slot exists. Further, as described above, the number of terminals of the module and the connector can be made the same as that of the first conventional example. It can be built at low cost. In addition, in this memory system, the main transmission line on the board and the sub transmission line on the module are separated in a DC manner by a directional coupler. It is possible to add, so-called hot-swap.

A third embodiment will be described with reference to the configuration diagram of FIG. In the third embodiment, the command and the signal of the address path 30 are in a point-to-point transfer (Point to Point, hereinafter referred to as P2P) method. 30 is connected from the MC 1 to the first register 2 on the module 20 by a plurality of one-to-one wires, and the registers 2 are similarly connected by a plurality of one-to-one wires.

The transfer method of the data bus 40 is equivalent to XTL, while the transfer method of the command and address bus 30 is P2P as described above. P2P is a transfer method capable of maximizing the data transfer speed among the above-mentioned SSTL, SLT, and XTL. This is because the signal is attenuated even in the XTL method, but the signal is hardly attenuated in the P2P method. In other words, in XTL, the signal transmitted from the main coupling line to the sub coupling line by the directional coupler means that the signal propagating on the main transmission line loses energy in terms of the law of conservation of energy. Therefore, the signal attenuates little by little when passing through multiple directional couplers. There is almost no signal attenuation except for the unavoidable factor due to dielectric loss due to the dielectric material constituting the diode.

Therefore, in the third embodiment, the data transfer speed of the command and address path 30 can be higher in principle than the data transfer speed of the data bus 40. However, since the data transfer rate of the memory system is ultimately determined by the data transfer rate of the data bus 40 using the XTL transfer method, the data transfer rate is the same as that of the memory system in the second embodiment. It can only be increased up to the data transfer speed. By the way, the number of terminals of the module and the connector is increased by about 20% from the number of terminals of the first conventional example, for the same reason as in the first embodiment. Almost no problem.

Next, in the present embodiment, the case where there is an empty slot will be described with reference to FIGS. 8 and 9 which are a side view (a) and a circuit diagram (b) of a command and an address bus corresponding to FIG. I do. Fig. 8 shows the case where there is no empty slot, and Fig. 9 shows the case where there is an empty slot.

The command and address bus 30 is derived from MC1 and? Connected to the first register 2 with 2?. At this time, the command and address bus 30 are matched and terminated by the resistor 61 near the receiver 4 of the register 2 or inside the register. The first register 2 has not only the function of transferring command and address signals to memory as a conventional register, but also the function of receiving the signal output from the MC and buffering it in the second register 2. I have. Note that the driver from the register to each memory is not shown in the figure for simplicity. Similarly, in the registers after the second register, not only the function of transferring the command and address signal to the memory as the conventional register but also the signal output from the register in the preceding stage is received, and the received signal is transferred to the register in the subsequent stage. It has the function of buffering in the evening.

If there is an empty slot as shown in Fig. 9 (b), the module with the memory must be inserted in order starting from MC1. In addition, in the register cascade-connected to the farthest end from the MC, control is performed so that the above-described function of buffering the register in the subsequent stage is not activated.

As described above, in the third embodiment, if there is an empty slot, 2003/008356

14

It is necessary to insert the modules mounted with the memory cells in order from the closest to the MC 1, but it is possible to construct a memory system capable of speeding up the data transfer of the memory system as in the second embodiment.

The fourth embodiment will be described with reference to the configuration diagram of FIG. In the fourth embodiment, the P2P method is used for the command and address path 30 as in the third embodiment, but the registers are mounted on the board 100 instead of the module 20. The difference is that they are done.

The transfer method of the data path 40 is equivalent to XTL, while the transfer method of the command and address path 30 is P2P as in the third embodiment. Therefore, also in the fourth embodiment, the data transfer speed of the command and address bus 30 can be higher in principle than the data transfer speed of the data path 40. However, for the same reason as in the third conventional example, the speed can be increased only to the same data transfer speed as the memory system in the second embodiment. By the way, in the fourth embodiment, unlike the third embodiment, the command and the address signal need only be introduced in the module and need not be derived, so the number of terminals in the module and the connector is smaller than that in the third embodiment. It can be the same as the number of terminals of the conventional example of 1.

Next, in this embodiment, the case where there is an empty slot will be described with reference to FIGS. 11 and 12 which are a side view (a) and a circuit diagram (b) of the command and address bus corresponding to FIG. explain. Fig. 11 shows the case where there is no empty slot, and Fig. 12 shows the case where there is an empty slot.

The command and address path 30 is derived from MC 1 and connected to the first register 2 by P 2 P. At this time, the command and address bus 30 is matched and terminated by the resistor 61 near the receiver 4 of the register 2 or inside the register. The first register 2 has not only the function of transferring command and address signals to memory as a conventional register, but also the function of receiving the signal output from the MC and buffering it in the second register 2. I have. Similarly, in the registers after the second register, not only the function of transferring the command and address signal to the memory as the conventional register but also the signal output from the previous register and the subsequent register are received. It has the function of buffering to the register. Empty slot as shown in Fig. 12 (b) In the case where there is a socket, unlike the third embodiment, the modules equipped with the memories do not need to be inserted in order from the MC 1. This is because the registers are connected to P 2 P on Pod 100, not via a module. However, in the registers that are cascaded from the MC to the farthest end, control is performed so that the above-mentioned function of buffering to the subsequent register is not activated. In addition, the registers for the empty slots are controlled so that the function of transferring command and address signals to the memory as in the conventional register is not activated.

As described above, in the fourth embodiment, even when there is an empty slot, no special parts are required, and the number of terminals of the module and the connector can be made the same as in the first conventional example. Accordingly, it is possible to construct a low-cost memory system capable of speeding up the data transfer of the memory system as in the second embodiment. The fifth embodiment is the same as the first embodiment in that XTL is used for the data path and SLT is used for the command and address paths, but the method of terminating the command and address bus is different.

In the fifth embodiment, the case where there is an empty slot will be described with reference to the side view (a) and the circuit diagram (b) of FIGS. 13 and 14, which are the command and address bus corresponding to FIG. explain. Fig. 13 shows the case where there is no empty slot, and Fig. 14 shows the case where there is an empty slot.

The command and address path 30 is drawn from the MC 1 and is matched and terminated in the termination dedicated module 22. At this time, the terminating resistor 6 1 may be mounted near the register 2 on the terminating module 2 2, or may be mounted at the end of the bus wiring as shown by the terminating module 22. . The wiring of the command and address bus 30 in the terminal only module 22 may be the same as that of the normal module 20, but in that case, some wiring will be redundant depending on the mounting position of the terminal resistor. Therefore, it does not become an ideal matching termination. For this reason, as shown in the terminal-only module 22, the wiring of the command and address bus in the terminal-only module is less reliable if the redundant wiring after the connection with the terminal resistor is removed. It is advantageous in terms of signal quality. By the way, in the fifth embodiment, since the terminal only module 22 is provided, if there is an empty slot, the first embodiment is used. PT / JP2003 / 008356

16

Instead of the need for a dummy module such as that described above, normal modules must be inserted in order starting from MC1 and the end-only module 22 must be inserted in the slot next to the last slot.

As described above, in the fifth embodiment, since a special dummy memory module as in the first embodiment is not required, a memory system capable of speeding up data transfer is conventionally provided. It can be constructed at a lower cost than the first conventional example.

The sixth embodiment is the same as the first embodiment in that XTL is used for the data signal and SLT is used for the command and address signals, but the method of terminating the command and address signals is different.

In the sixth embodiment, the case where there is an empty slot will be described with reference to FIGS. 15 and 16 which are the side view (a) and the circuit diagram (b) of the command and address bus corresponding to FIG. Will be explained. Fig. 15 shows the case where there is no empty slot, and Fig. 16 shows the case where there is an empty slot.

The command and address path 30 is drawn from MC 1 and is matched and terminated by an active resistance element 63 mounted inside the register 2 on the last module 20 connected to MC 1. The active resistance element 63 is controlled so that only the element in the register 2 farthest from the MC 1 is activated, and the active resistance elements in the other registers are not activated. The active resistive elements inside these non-activated registers are indicated by dotted lines in FIGS. 15 (b) and 16 (b). By the way, in the sixth embodiment, when there is an empty slot, a normal module as in the first embodiment is no longer necessary, but ordinary modules are inserted in order from the MC 1. Need to be Further, in the present embodiment, in the last module connected to the MC 1, a part of the wiring beyond the register 2 becomes redundant, so that it does not become an ideal matching termination. Therefore, it is possible to further improve the signal quality by providing a terminal-only module in which the redundant wiring section is removed. As described above, in the sixth embodiment, not only the special dummy memory module as in the first embodiment is not required, but also the active resistance element 63 is provided inside the register 2. This eliminates the need for a terminal-only module as in the fifth embodiment. It can be constructed at a lower cost than the fifth embodiment.

The seventh embodiment will be described with reference to the configuration diagram of FIG. The seventh embodiment is the same as the first embodiment in that the XTL is used for the data bus and the SLT is used for the command and address buses, but the command and address bus data between the MC and the register are used. The difference is that the transfer speed is doubled. In the conventional DDR memory system, the data transfer speed of the command and address bus is 1/2 of the transfer speed of the data bus, but this data transfer speed only needs to be satisfied in the memory, and between the MC and the register. There is no problem even if the command and address bus data transfer rates are higher than before. At this time, the MC 1 has a function to multiplex (MUX) the command and address signal 30 twice as much as the conventional one, as shown in Fig. 18 (a). 8 As shown in (b), it has a function to demultiplex the multiplexed command and address signal (D EMUX) and transfer the command and address signal of the conventional data transfer rate to each memory. . In this embodiment, as shown in FIG. 17, compared with the first embodiment, the number of wires of the command and address bus 30 is at least one, that is, the total number of terminals of the module and the connector is The number can be substantially the same as that of the first conventional example.

The multiplexing (MUX) and demultiplexing (DEMUX) functions can be realized by using a 2: 1 multiplexer 7 and a 1: 2 demultiplexer 8, for example, as shown in FIG. Furthermore, the number of output units corresponding to the reduced number of command and address bus lines is not required in the MC, so the number of MC poles and the chip area are reduced, so that the manufacturing cost of the MC can be reduced. I can do it. Further, at this time, in the memory occupying most of the devices constituting the memory system, the data transfer speed of the command and the address signal may be the same as the conventional one, so that there is an effect that the cost does not increase due to this.

As described above, in the seventh embodiment, a memory system capable of speeding up data transfer of the memory system can be constructed at a lower cost as in the first embodiment.

An eighth embodiment will be described with reference to the configuration diagram of FIG. In the eighth embodiment, XTL is used for the data bus and XT is also used for the command and address bus, as in the second embodiment. It is the same in that L is used, but differs in that the command and address path data transfer speed is doubled compared to the past. In other words, the data path for the data path and the command and address buses are both set to the same data transfer rate, but since both have the same transfer method, it is possible in principle to have the same signal quality. At this time, the MC 1 has a function of multiplexing the command and the address signal 30 twice the conventional one, and the register 2 on each module demultiplexes the multiplexed command and the address signal, It has a function to transfer commands and address signals of the conventional data transfer speed to each memory. The multiplexing and demultiplexing functions can be realized by using a 2: 1 multiplexer 7 and a 1: 2 demultiplexer 8 as shown in FIG. 19, for example. Requires the circuit shown in FIG. 28 for receiving the RTZ signal transferred by the XTL and restoring it to the original NRZ signal. As shown in FIG. 20, in the present embodiment, the number of wires of the command and address bus 30 is at least 12, that is, the total number of terminals of the module and the connector is smaller than that of the first embodiment, as compared with the second embodiment. Can be reduced as compared with the conventional example. Further, as in the seventh embodiment, the number of output units corresponding to the reduced number of command and address paths is not required in the MC, so that the number of MC poles and the chip area are reduced. MC manufacturing costs can be reduced. Further, at this time, in the memory which occupies most of the devices constituting the memory system, the data transfer speed of the command and the address signal may be the same as the conventional one, so that there is an effect that the cost does not increase.

As described above, in the eighth embodiment, a memory system capable of speeding up the data transfer of the memory system can be constructed at a lower cost as in the second embodiment.

The ninth embodiment will be described with reference to the configuration diagram of FIG. The ninth embodiment is the same as the third embodiment in that XTL is used for the data bus and P2P is used for the command and address buses, but the data transfer speed of the command and address bus is the same as that of the third embodiment. The difference is that it is doubled or quadrupled. The P2P transfer method enables faster transfer than XLT, and is equivalent to XLT, which has twice the data transfer speed, even if the data transfer speed is four times that of conventional P2P. Signal quality can be ensured There is a potential. At this time, the MC 1 has a function of multiplexing the command and address signal 30 twice or four times the conventional value, and the register 2 on each module stores the multiplexed command and address signal. It has the function of demultiplexing and transferring commands and address signals at the conventional data transfer rate to each memory. The functions of the multiplexing and demultiplexing are as described above, for example, as shown in FIG. 19 described above, such as 2: 1 multiplexer 7 and 1: 2 demultiplexer 8, and as shown in FIG. , 4: 1 multiplexer (a) and 1: 4 demultiplexer (b). In this embodiment, as shown in FIG. 21, the number of wires of the command and address bus 30 can be reduced to at least 1/2 or 1/4 as compared with the third embodiment. That is, the total number of terminals of the module and the connector can be made substantially equal to or less than that of the first embodiment. Also, as in the eighth embodiment, the number of output units corresponding to the reduced number of command and address bus lines is not required in the MC, so that the number of MC poles and the chip area are reduced, so the MC is reduced. Manufacturing cost can be reduced. Furthermore, at this time, in the memory that occupies most of the devices constituting the memory system, the data and data transfer rates of the command and the address signal can be the same as before, so that there is an effect that the cost does not increase due to this. .

As described above, in the ninth embodiment, a memory system capable of speeding up data transfer of the memory system can be constructed at a lower cost as in the second embodiment.

The tenth embodiment will be described with reference to the configuration diagram of FIG. The tenth embodiment is the same as the fourth embodiment in that XTL is used for the data bus and P 2 P is used for the command and address buses. The difference is that the speed is doubled or quadrupled. The difference from the ninth embodiment is that the mounting locations of the register 2 are the module 20 and the board 100, respectively.

In this embodiment, as shown in FIG. 23, similarly to the ninth embodiment, the number of wires of the command and address bus 30 can be reduced to 1 Z 2 or 1/4 at a minimum. The number of output units corresponding to the reduced number of command and address bus wires is Since it becomes unnecessary in MC, the number of MC poles and the chip area are reduced, so that the manufacturing cost of MC can be reduced. In addition, at this time, in the memory that occupies most of the devices constituting the memory system, the data and data transfer rates of the command and the address signal can be the same as before, so that there is no effect that the cost increases due to this. is there. On the other hand, the total number of terminals of the module and the connector is the same as that of the first conventional example because the transfer speed of the command and address bus between the register 2 and the memory 10 is the same as the conventional one.

As described above, in the tenth embodiment, a memory system capable of speeding up the data transfer of the memory system can be constructed at a lower cost as in the second embodiment.

In the above embodiment, the case where the directional coupler is configured as the transfer line in the node has been described. However, the case where some or all of the directional couplers are mounted in the form of parts is also described. Can be easily applied.

In the above embodiment, the case where the directional coupler is mounted on the port has been described. However, the present invention can be easily applied to an example in which some or all of the directional couplers are mounted on the module. Further, other than the above-described embodiment, the present invention can be easily applied to an embodiment in which the transfer speed of the command and the address bus is doubled or quadrupled compared to the conventional example.

Further, for the preferred embodiment described above with reference to FIG. 18, and more generally for a first data rate in the data signal, the memory controller multiplexes the command and address signals, The second data transfer rate in the command and address signal transferred to the register is made the same as or n times the first data transfer rate, demultiplexed in the register, and transferred from the register to multiple memories The third data transfer rate of the command and address signals may be 1 / n of the first data transfer rate. This can be easily configured by using the n: 1 multiplexer and the l: n demultiplexer in the examples shown in FIGS. Here, n is an integer.

For paths that control the data transfer rate of conventional memory systems, the data transfer rate can be increased. A memory system capable of speeding up can be realized. In addition, the data transfer speed of the command and address bus between the MC and the register has been doubled or quadrupled compared to the past, and the number of these wires has been reduced. An inexpensive memory system is obtained. Industrial applicability

The memory system according to the present invention can be applied to a memory system capable of speeding up data transfer as a whole system in order to increase the data transfer speed of the command and address paths.

Claims

The scope of the claims

1. In a port equipped with a memory module on which a plurality of memories are mounted and a memory controller for controlling a plurality of the memory modules,

The transfer of data signals between the memory controller and the memory module is performed by a first method in which a main transmission line and a sub-transmission line are separated DC and connected AC through a directional coupler. The transfer of the command and the address signal between the memory controller and the memory module is performed by the first method or the second method connected in a DC and AC manner, and the command and the address signal are transferred. A board for transferring the data to a plurality of the memories, wherein the directional coupler and the register are mounted on the memory module or the port.

2. A port equipped with a memory module on which a plurality of memories are mounted and a memory controller for controlling a plurality of the memory modules,

The transfer of data signals between the memory controller and the memory module is performed by a first method in which a main transmission line and a sub-transmission line are separated DC and connected AC through a directional coupler. The transfer of the command and the address signal between the memory controller and the memory module is performed by the first method or the second method connected in a DC and AC manner, and the command and the address signal are transferred. A register for transferring the data signal to the plurality of memories, the directional coupler is mounted on the port, and the register is mounted on the memory module, and the data signal with the directional coupler is provided. A memory bus system, comprising:

3. In a memory module mounted on a board having a memory controller, the transfer of a data signal between the memory controller and the memory module is performed by a main transmission line and a sub transmission line via a directional coupler in a DC manner. The command and the address signal are transferred between the memory controller and the memory module in the first mode that is separated and connected in an alternating manner. The second method is used, and the command and the address signal are A memory module comprising a register for transferring data to a plurality of memories, wherein the directional coupler and the register are mounted on the memory module.

4. In a port equipped with a memory module having a plurality of memories and a memory controller for controlling the plurality of memory modules,

The transfer of the data signal between the memory controller and the memory module is performed by a first method in which the main transmission line and the sub transmission line are separated by direct current and connected by alternating current via a directional coupler. The transfer of the command and the address signal between the memory controller and the memory module is performed by the first method or the second method connected in a DC and AC manner, and the command and the address signal are transferred. A register for transferring an address signal to the plurality of memories; the directional coupler and the register being mounted on the port; an interface of the data signal with the directional coupler; A memory bus system comprising an interface for register and command and address signals.

5. The memory module of claim 2,

The memory module according to the second aspect, wherein the transfer of the command and the address signal between the memory controller and the register is performed by the second method connected by a plurality of single-stroke wiring without branch.

6. The memory module of claim 3,

The memory module according to claim 2, wherein the transfer of the command and the address signal between the memory controller and the register is performed by the second method connected by a plurality of one-stroke wirings without branch.

7. The memory module of claim 2,

The transfer of command and address signals between the memory controller and the register is performed by the first method.

8. The memory module of claim 3,

The memory module according to claim 1, wherein the transfer of the command and the address signal between the memory controller and the register is performed by the first method.

9. The memory module of claim 2,

Transfer of command and address signals between the memory controller and the register Are connected one-to-one by a plurality of non-branching wirings between the memory controller and the first register, and similarly, a plurality of non-branching wirings are also provided between the registers after the first register. 2. The memory module according to the second method, which is connected one-to-one.

10. The memory module of claim 3,

The transfer of the command and the address signal between the memory controller and the register is performed in such a manner that the memory controller and the first register are connected one-to-one by a plurality of wirings without branching, and the first and subsequent registers are connected. The memory module according to the second method, wherein the registration is performed in a one-to-one manner by a plurality of non-branching wirings.

1 1. The memory module of claim 4,

The transfer of command and address signals between the memory controller and the register is performed by connecting the memory controller and the first register in a one-to-one manner by a plurality of wirings without branches. The memory module according to the second method, wherein the registers after the register are similarly connected in a one-to-one manner by a plurality of wirings having no branch.

1 2. The memory module of claim 5,

Maintains an electrical connection between the memory controller and the terminating resistor of the command and address signal to be inserted when there is an empty slot into which the memory module having a plurality of memories cannot be inserted. A plurality of command and address wirings for performing the operation, and wherein a device such as the memory is not mounted.

13. The memory module of claim 6,

Between the memory controller and the terminating resistor of the command and address signal, and between the memory controller and the data to be inserted when there is an empty slot into which the memory module having a plurality of memories is not inserted. A plurality of command and address wirings for maintaining electrical connection between terminal resistances of signals and data wirings therein, and a device such as the memory is not mounted. Memory module.

14. The memory module of claim 5,

If there is an empty slot, a plurality of the memory modules are inserted in order from the slot close to the memory controller so that there is no empty space, and the next slot after the last slot inserted as such is inserted. And a plurality of resistors for matching and terminating a plurality of non-branch one-stroke commands and address wiring for connecting between the memory controller and the plurality of registers. Terminal-only memory module.

15. The memory module of claim 6,

When there is an empty slot, a plurality of the memory modules are inserted in order from the slot close to the memory controller so that there is no empty space, and the slot next to the last slot inserted as such is inserted. A plurality of resistors for matching and terminating a plurality of one-stroke non-branch commands and address wiring for connecting between the memory controller and the plurality of registers, and the first method. And a resistor for matching and terminating the data line as a main transmission line in (1).

1 6. The memory module of claim 5,

When there is an empty slot, a plurality of the memory modules are inserted in order from the slot close to the memory controller so that there is no empty space, and a terminating resistor is provided as an active element inside each of the registers on the memory module. A memory module mounted, wherein only the active element farthest from the memory controller is activated and the command and address signals are matched and terminated.

17. The memory module of claim 6, wherein

When there is an empty slot, a plurality of the memory modules are inserted in order from the slot near the memory controller so that there is no empty space, and a terminating resistor is provided inside each of the registers on the memory module. Only the active element at the farthest end from the memory controller is activated, the command and address signals are matched and terminated, and the main transmission line of the data signal in the first method is matched and terminated. A terminal-only memory module having a terminating resistor.

18. The terminal-only memory module according to claim 14, 15 or 17, wherein the memory controller does not have a redundant wiring portion after the terminal resistor as viewed from the memory controller.

1 9. The memory module of claim 8,

A termination-only memory module comprising a resistor for matching and terminating a plurality of main transmission lines for the command and address signals and a plurality of main transmission lines for the data signal.

20. In the register according to claim 16 or 17,

A register in which a terminating resistor is mounted as an active element, and only the active element farthest from the memory controller is activated to match and terminate the command and address signals.

2 1. At each Registrar on Claim 9, 10 or 11,

At the receiving end of the signal, a resistor element is mounted near or inside the register, and a plurality of the command and address signals connected one-to-one are matched and terminated. A first function of transferring the data to the other memory connected to the memory controller, and the first function is provided in the register serially connected to the farthest end from the memory controller. A second function not to be activated; a transfer function of the command and the address signal to the empty slot when the register is mounted on the port and an empty slot exists; A register having a function of stopping the operation.

22. The memory controller for controlling the memory module according to claim 16 or 17.

It has a function of controlling the register so that only the active element inside the register at the farthest end from the memory controller is activated and the command and address signals are matched and terminated. Memory controller.

23. A memory controller for controlling the memory module according to claim 9, 10, or 11,

21. The second function according to claim 21, wherein the register is provided for the register connected in cascade to a farthest end from the memory controller. A memory controller having a control function for stopping a transfer function of the command and address signal to the empty slot when the slot is mounted on the port and an empty slot exists.

24. In a memory path system having a memory module on which a plurality of memories are mounted and a board on which a memory controller for controlling the memory module is mounted,

The transfer of the data signal between the memory controller and the memory module is performed by a first method in which the main transmission line and the sub transmission line are separated by direct current and connected by alternating current via a directional coupler. The transfer of the command and the address signal between the memory controller and the memory module is performed by the first method or the second method that is connected in a DC and AC manner. A register for transferring an address signal to the plurality of memories, and multiplexing the command and the address signal by the memory controller with respect to a first data transfer rate in the data signal; Increase the second data transfer rate in the command and address signal transferred to the register by the same or twice as the first data transfer rate Speeding up, demultiplexing in the register, and setting the third data transfer rate of the command and address signals transferred from the register to the plurality of memories to 1 2 of the first data transfer rate A memory path system characterized by:

25. The memory module according to any one of claims 2 to 19, wherein the command and address signal are multiplexed by the memory controller with respect to a first data transfer rate of the data signal. Then, the second data transfer speed of the command and the address signal transferred to the register is increased to the same or twice as the first data transfer speed, and demultiplexed in the register. The register having a function of setting a third data transfer speed of a command and an address signal transferred from the register to a plurality of memories to 1/2 of the first data transfer speed is mounted. And a memory module.

26. For the first data transfer rate of the data signal, the memory controller multiplexes the command and the address signal, and the command and the address transferred to the register are multiplexed. The second data transfer rate in the address signal is increased to be the same as or twice as high as the first data transfer rate, demultiplexed in the register, and the second data transfer rate of the command and address signal transferred from the register to the plurality of memories. 3. A register having a function of setting the data transfer rate of 3 to 1 Z 2 of the first data transfer rate.

27. The register according to claim 20, wherein a command and an address signal are multiplexed by a memory controller with respect to a first data transfer rate in the data signal, and a second data and a signal in the command and address signal transferred to the register are multiplexed. The data transfer rate of the first or second data transfer rate is increased to the same or twice as high as that of the first data transfer rate, demultiplexed in the register, and the third command and address signals transferred from the register to the plurality of memories. A register having a function of setting the overnight transfer rate to one of the first data transfer rates.

2 8. In claim 7 or 8,

The command and the address signal are multiplexed by the memory controller with respect to the first data transfer rate of the data signal, and the second data transfer rate of the command and the address signal transferred to the register is set to the first data transfer rate. The third data transfer rate of command and address signals transferred from a register to multiple memories is demultiplexed at the same or twice as high as the transfer rate. A register in a memory board having a function of setting the speed to 1Z2.

2 9. The register according to claim 21,

The command and address signals are multiplexed by the memory controller with respect to the first data transfer rate in the data transfer signal, and the second data transfer rate in the command and address signals transferred to the register is changed. The third data transfer rate of command and address signals transferred from the register to a plurality of memories by demultiplexing at the same or twice as high as the first data transfer rate and demultiplexing at the register. A register having a function of setting the first data transfer rate to 1 or 2;

3 0.

A command transferred to the register by multiplexing the command and the address signal with the memory controller with respect to a first data transfer rate in a data signal. And the second data transfer rate in the address signal is made the same or twice as fast as the first data transfer rate, demultiplexed in the register, and commands and addresses transferred from the register to a plurality of memories. A memory controller having a function of setting a third data transfer rate of a signal to 1 2 of the first data transfer rate.

31. The memory controller according to claim 22, wherein

The command and address signal are multiplexed by the memory controller with respect to a first data transfer rate of the data signal, and a second data transfer rate of the command and address signal transferred to the register is set to the first data transfer rate. The third data transfer rate of command and address signals transferred from the register to a plurality of memories is demultiplexed at the same or twice the data transfer rate of the first register. A memory controller with a function to set the data transfer rate to 1 Z 2.

3 2. In claim 7 or 8,

The memory controller multiplexes the command and address signals with respect to the first data transfer rate in the data signal, and sets the second data transfer rate in the command and address signals transferred to the register to the second data transfer rate. The third data transfer rate of command and address signals transferred from the register to a plurality of memories is demultiplexed in the register to be the same or twice as high as the data transfer rate of the first. A memory controller in a memory board on which the register having the function of reducing the data transfer rate to 1/2 is mounted.

33. The memory controller of claim 23,

The memory controller multiplexes the command and address signal with respect to the first data transfer rate of the data signal, and sets the second data transfer rate of the command and address signal transferred to the register to the first data transfer rate. The data transfer speed is the same as or twice as high as the data transfer speed of the third register, and the third data transfer speed of command and address signals transferred from the register to the plurality of memories is demultiplexed in the register. A memory controller having a function of setting the data transfer rate to 1 2.

3 4. A memory module having a plurality of memories, a memory controller connected to the memory of the memory module via a bus, and a data controller connected to the memory controller via the bus. In a memory bus system for transferring signals and commands or addresses, in order to transfer data signals between the memory controller and the memory module. Directly by a main transmission line and a sub transmission line via a directional coupler. A first bus connection that is separated and connected in an alternating manner;

A second connection path for DC and AC connection for transferring a command or address signal between the memory controller and the memory module;

A memory bus system, comprising: a register for transferring a command or an address signal transferred via the second connection path to the plurality of memories.

35. The memory bus system of claim 34,

A memory bus system, comprising: a board to which a plurality of the memory modules are connected via a connector, wherein the directional coupler and the register are mounted on the board.

36. The memory bus system according to claim 34, wherein a plurality of said memory modules comprise a port connected via a connector, and said directional coupler and said register are mounted on said memory module. And a memory bus system.

37. The memory bus system of claim 34, wherein

A memory path system comprising: a port to which a plurality of the memory modules are connected via a connector; the directional coupler mounted on the port; and the register mounted on the memory module.

38. A memory module equipped with a plurality of memories, which can be connected to a memory controller by a bus and transfers data signals and command or address signals between the memory controllers via the bus.

A first bus connection path, which is dc-separated and ac-connected by a main transmission line and a sub-transmission line via a directional coupler to transfer a data signal to and from the memory controller;

A second connection path for direct and alternating connection for transferring command or address signals to and from the memory controller;

A memory module comprising: a register for transferring a command or an address signal transferred via the second connection path to the plurality of memories.

39. A board connected via a connector to a memory module equipped with a plurality of memories, the path connected to the memory of the memory module, and the data transferred to the memory module via the bus. A directional coupler for transferring a data signal between the memory controller and the memory module at a port for connecting a memory module having an overnight signal and a memory controller for issuing a command or an address; A first bus connection path which is separated in DC and connected in AC by a main transmission line and a sub transmission line via

A memory module connection board having a register for transferring a command or an address signal transferred via the second connection path to the plurality of memories.

40. A board connected via a connector to a memory module equipped with a plurality of memories and a register for temporarily storing a command and an address signal to be transferred to the memory, wherein the memory of the memory module In a memory module connection port having a bus to be connected, a data signal transferred to the memory module through the path, and a memory controller that issues a command or an address,

A first path connection path which is dc-separated and ac-connected by a main transmission line and a sub-transmission line via a directional coupler to transfer a data signal between the memory controller and the memory module; ,

A port for connecting a memory module equipped with.

41. In any one of claims 34 to 40,

The second connection path is configured by a plurality of single-stroke wirings without branching.

42. A memory module having a plurality of memories mounted thereon, and a memory controller connected to the memory of the memory module via a bus, and transferring a data signal, a command, or an address via the bus. In memory systems,

In order to transfer a data signal between the memory controller and the memory module, A first bus connection path that is separated DC and connected AC by a main transmission line and a sub transmission line via a directional coupler;

A register for transferring a command or an address signal transferred via the second connection path to the plurality of memories;

Also, by multiplexing (MUX) the command and address signals with the memory controller for the first data transfer rate of the data signals, the command and address signals transferred to the register are multiplexed. The second data transfer rate in the above is made the same as or n times as large as the first data transfer rate, and demultiplexing (DEMUX) is performed in the register, whereby the command transferred from the register to the plurality of memories is executed. And a third data transfer rate of the address signal is set to l Zn of the first data transfer rate.