JP3543541B2 - Signal transmission equipment - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a technology for transmitting signals between components (integrated circuits are typical) mounted in a device such as a workstation or a personal computer, and particularly to a technology effective for high-speed signal transmission.
[0002]
[Prior art]
FIG. 3 shows an example of a memory circuit used in a current workstation or personal computer.
[0003]
Reference numeral 30 denotes a memory module on which a plurality of memory LSIs 31 are mounted. Reference numeral 32 denotes a memory controller, which controls the memory LSI 31, transmits write data to the memory LSI 31, receives read data from the memory LSI 31, and the like.
[0004]
In some memory controllers 32, a part for controlling the memory LSI 31 and a part for transmitting write data and receiving read data are implemented by separate integrated circuits.
[0005]
Here, the memory LSI is assumed to be a clock synchronous type memory. Examples of the clock synchronous memory include an SDRAM (Synchronous Dynamic Random Access Memory).
[0006]
The memory controller is mounted on a motherboard 33, and the memory module 30 is mounted on a mother board by a connector.
[0007]
In FIG. 3, the number of memory modules mounted on the motherboard is eight, but the number of modules is determined at any time according to the system scale, specifications, user's purpose, and the like.
[0008]
The simple circuit operation of this memory circuit is as follows. A control signal or a write data signal output from the memory controller passes through a signal wiring 35 on the motherboard, a connector 34, a contact 36 on the memory module, and a wiring 37 on the memory module to the memory LSI 31 on each module. It is reported. Further, in the case of data reading, the data is input from the memory LSI 31 to the memory controller 32 through the wiring 37 on the module, the contact 36, the connector 34, and the wiring 35 on the motherboard.
[0009]
Such a wiring 35 is called a memory bus. FIG. 3 shows only one of the plurality of memory buses.
[0010]
A clock signal is supplied to the SDRAM in addition to the control signal and the data signal, but a clock wiring is not shown in FIG. The clock wiring is distributed to a memory controller or a memory LSI in a memory module directly from a clock source or from a frequency dividing and distribution destination.
[0011]
There is a single-phase clock system using a flip-flop for a signal transmission line between integrated circuit components such as in a memory system.
[0012]
This technique is described in detail, for example, on pages 356 to 360 of the basics of VLSI system design circuit and implementation (Maruzen Publishing, 1995).
[0013]
FIG. 2 shows the simplest example of the single-phase clock system. FIG. 2 shows a transmission circuit in which an output circuit and an input circuit are connected 1: 1. Here, the circuit block 21 includes a flip-flop 24 and an output circuit 26, and the circuit block 22 includes an input circuit 27 and a flip-flop 25. Reference numeral 23 denotes a transmission line for transmitting a signal output from the circuit block 21 to the circuit block 22.
[0014]
To the flip-flops 24 and 25, a clock that is directly or distributed and frequency-divided is input from a clock source. Although not shown in FIG. 2, the input signal of the flip-flop 24 is generated in the circuit block 21, and the output of the flip-flop 25 is generally input to another circuit in the circuit block 25. It is a target.
[0015]
In the above description, the input signal of the flip-flop 24 is generated in the circuit block 21. However, the input signal may be generated in another circuit block and directly input to the flip-flop. Similarly, the output of the flip-flop 25 is not limited to the input circuit in the circuit block 22 and may be directly wired to an input circuit in another circuit block.
[0016]
[Problems to be solved by the invention]
The basic operation of the circuit shown in FIG. 2 is as follows.
[0017]
It is assumed that a clock is supplied to the flip-flops 24 and 25. The flip-flop 24 outputs the data latched by the clock of the previous cycle in synchronization with the clock, transmits the data to the input section of the output circuit 26, and outputs the data to the transmission line 23 from the output section. The data transmitted through the transmission line 23 is transmitted through the input circuit 27 to the data input section of the flip-flop 25, and the data is latched in synchronization with the clock.
[0018]
In the case of a single-phase clock system, the clocks input to the flip-flops are designed to be in phase with each other. Techniques for adjusting the phase include adjusting the signal wiring length from the clock source or its distribution destination, frequency division destination to the clock input section of each circuit block, and adjusting the capacitive load of the clock signal wiring to reduce the wiring delay. The method of matching is widely used.
[0019]
In this single-phase clock system, a technique widely used as a method for efficiently transmitting a signal is a transmission method in which the signal is latched on the receiving side in a cycle next to a cycle in which the signal is output. In this method, the cycle time tcycle must satisfy the following equation.
[0020]
t cycle> t delay (max) + t pd (max) + t setup (max) + t skew (max)
here,
t delay (max) is the clock access time of the circuit block 21, that is, the time from when a clock is input to the circuit block 21 until data is output from the circuit block 21,
t pd (max) is a propagation time until a signal output from the circuit block 21 is input to the circuit block 22;
t setup (max) is a setup time of the circuit block 22, that is, a time during which a logical value (High or Low) of a signal input to the circuit block 22 must be determined prior to a clock input to the circuit block 22. ,
Finally, t skew is the skew between the clocks input to the circuit blocks 21 and 22, respectively.
[0021]
The expression (max) in the equation means the maximum value in consideration of variations in temperature, process, and the like.
[0022]
In the memory circuit shown here, when the connection wiring between the circuit blocks (here, the memory controller and the memory module) is long, the above-described propagation time and tpd have large values. For example, when the connector pitch is 400 mil (about 1 cm) and the number of memory modules is 16, tpd is 3 to 4 ns.
[0023]
Assuming that tpd (mux) is 4 ns, when the number of cycles is 33 MHz, the ratio of tpd to the cycle and 30 ns is only about 10%, and t cycle> t delay (max) + t pd (max) + t setup (max) + t skew (max)
It is possible to satisfy
[0024]
However, for example, when the number of cycles is increased to 250 MHz, the cycle is 4 ns, which is the same as tpd (max), and this system cannot be realized no matter how much the speed of the circuit block is increased. Even if it is not up to 250 MHz, the speeding up of t delay (max), t setup (max), t skew (max) is largely due to the miniaturization of the device, and in reality, even if the number of cycles around 100 MHz
t cycle <t delay (max) + t pd (max) + t setup (max) + t skew (max)
, And further speeding up is impossible by design.
[0025]
When considering realization of high speed, there is a method of examining securing of a window in addition to the delay calculation as described above. In the case of delay calculation, we are examining the possibility of signal transmission with the clock phase of the output circuit and the input circuit matched, but if the window is taken into account, offset adjustment is added to the clock phase This enables further higher speed.
[0026]
Adding the offset adjustment to the clock phase means, for example, in the case of FIG. 3, shifting the phase of the clock supplied to the memory module earlier or later than the clock supplied to the memory controller. Say.
[0027]
For example, if the delay time at the time of writing is earlier than the delay time at the time of reading, the method using the above-described delay time determines the cycle according to the delay time at the time of reading, but takes into account the window. In this case, the read data can be output earlier by shifting the phase of the clock supplied to the memory LSI earlier. As a result, in the memory controller, the clock synchronization timing of the memory LSI and the clock synchronization of the next cycle of the memory controller. Since the time until the timing can be extended, a time longer than the delay time at the time of reading may be secured in some cases. In other words, when considering window time, instead of the above formula, the window time t window,
t window = t cycle + t OH-t delay (max)
Design using.
[0028]
t OH is the data output hold time, which is the time from when the next clock is input to the output circuit block that is outputting a signal until the output is switched to data (of that cycle). This time is equal to or greater than tdelay (min), the minimum value of tdelay.
[0029]
Based on the value of t window obtained in this way, the following expression should be satisfied.
[0030]
t window> tpd (max-min) + t setup (max) + t hold (max)
Here, tpd (max-min) is the difference between the maximum value and the minimum value of tpd. In the case of FIG. 3, the maximum value is the propagation between the module farthest from the memory controller and the memory controller. Time and the minimum is the propagation time between the nearest module and the memory controller. That is, t delay (max-min) is a quantity representing a difference in propagation time depending on the position of the memory module.
[0031]
This window time is examined for each of writing and reading data to and from the memory module.
t window> tpd (max-min) + t setup (max) + t hold (max)
Is satisfied, the offset value of the clock phase should be set in each window width t window-tpd (max-min) so that the setup time and the hold time can be secured.
[0032]
Although this method can achieve a slight increase in speed, the value of tpd (max-min) cannot be ignored as the size of the device, for example, in the memory circuit shown in FIG. 3, increases as the number of mounted modules increases. Is still difficult.
[0033]
In other words, as the high-speed transmission is required, the influence of the difference between the signal propagation time from the memory controller to the near-end memory module and the signal propagation time from the memory controller to the far-end memory module increases, Difficulties arise in high-speed design of systems.
[0034]
A similar problem occurs between circuits that transmit and receive signals in synchronization with a clock regardless of the memory system. For example, a similar problem occurs in a processor bus in a multiprocessor system using a plurality of microprocessors. Can occur.
[0035]
An object of the present invention is to solve these problems in a system that exchanges signals in synchronization with a clock signal.
[0036]
SUMMARY OF THE INVENTION It is an object of the present invention to provide a signal transmission device capable of reducing signal transmission / reception failure due to a delay in signal propagation time between circuits.
[0037]
Other objects of the present invention will be clarified in the following detailed description.
[0038]
[Means for Solving the Problems]
To achieve the above objectives,
A clock output circuit for outputting a clock signal, a first circuit for outputting a first signal, a plurality of second circuits for receiving the first signal, and the plurality of second circuits arranged A signal transmission device comprising: a substrate to be mounted; a first wiring for transmitting the clock signal; and a second wiring for transmitting a signal from the first circuit to the second circuit.
The first wiring is wired from the clock output circuit and connected in series with the plurality of second circuits, and the second wiring is wired from the first circuit and connected in series with the plurality of memory modules. And the first and second wirings are connected to the second circuit.
[0039]
By doing so, the relative relationship between the distance that the clock signal reaches an arbitrary second circuit and the distance that the first signal output from the first circuit reaches the second circuit is: The distance can be substantially the same regardless of the mounting position of the second circuit. When the second circuit latches the first signal in synchronization with the clock signal, the distance between the circuits of the first signal The influence of the propagation delay time can be suppressed.
[0040]
Further, each of the first and second wirings is folded at a position farther from the first circuit than the second circuit, and returns to the second circuit closest to the first circuit. Layout,
A part of the second circuit is connected to a position where the first wiring and the second wiring are folded back, and the remaining second circuit is connected to a position after the folding position of the first and second wirings. The connection can reduce the load density.
[0041]
Further, a clock output circuit for outputting a clock signal, a first circuit for outputting a first signal and receiving a second signal, and receiving the first signal and outputting the second signal A plurality of second circuits, a substrate on which the plurality of second circuits are arranged and mounted, a first wiring for transmitting the clock signal, and a signal from the first circuit to the second circuit And a third line for transmitting a signal from the second circuit to the first circuit.
The first wiring is wired from the clock output circuit, is connected in series with the plurality of second circuits,
The second and third wirings are wired from the first circuit, are connected in series to the plurality of memory modules,
The second wiring is laid back at a position farther from the first circuit than the second circuit, and is laid out so as to return from the first circuit to the nearest second circuit;
Each of the first and third wirings is folded at a position farther from the first circuit than the second circuit, and after returning to the second circuit closest to the first circuit, Laid out to reach the first circuit,
In the first wiring and the second wiring, a part of the second circuit is connected up to a folded position of the first wiring and the second wiring, and the remaining second circuit is connected to the second wiring. Connecting the first and second wirings after the return position,
In the third wiring, the part of the second circuit connected to the first wiring up to the return position of the first wiring is connected after the return position of the third wiring, The remaining second circuit is connected up to the third wiring return position.
[0042]
By doing so, the relative relationship between the distance that the clock signal reaches an arbitrary second circuit and the distance that the first signal output from the first circuit reaches the second circuit, and The distance until the second signal output by the second circuit in synchronization with the clock signal reaches the first circuit, and the clock signal when the second circuit outputs the second signal is the first signal. The relative relationship with the distance to reach the circuit can be substantially the same regardless of the mounting position of the second circuit, and the second circuit can synchronize the first signal with the clock signal. When latching and when the first circuit latches the second signal, the effect of the propagation delay time between the first and second signals can be suppressed.
[0043]
A first output circuit for outputting a first signal; a second output circuit for outputting a second signal; a first receiving circuit for receiving a third signal; and a receiving circuit for receiving a fourth signal. A first circuit block having a second receiving circuit, a third receiving circuit for receiving the first signal, a fourth receiving circuit for receiving the second signal, and a third signal. A plurality of second circuit blocks each having a third output circuit for outputting the signal and a fourth output circuit for outputting the fourth signal, wherein the first signal, the second signal, and the third signal are provided; Then, a first wiring, a second wiring, a third wiring, and a fourth wiring for transmitting the fourth signal between the first circuit block and the second circuit block are respectively connected to the first wiring. Fold at the position of the second circuit block farthest from the circuit block or at a position farther from the position Then, for the first signal and the third signal, a part of the second circuit block is connected on the wiring from the first circuit block to the turnback position, and the other The second circuit block is connected on the wiring before the folded point, and the first signal is transmitted from the first circuit block to the folded position with respect to the second signal and the fourth signal. The second circuit block is connected on a line ahead of the turning point, and the other second circuit blocks are connected to the turning position from the first circuit block. The second receiving circuit latches the fourth signal in synchronization with the third signal, and further the fourth receiving circuit latches the fourth signal in synchronization with the first signal. Latch configuration, and the memory module side We may output a timing signal for receiving data at the memory controller side when outputting data.
[0044]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.
[0045]
In this embodiment, an example of a memory bus of a memory system will be described. As described above, the present invention is applicable to buses of all levels requiring high-speed signal transmission such as workstations and personal computers, that is, signal wirings such as a system bus (processor bus), a memory bus, and a peripheral bus shown in FIG. Is also applicable. It goes without saying that the present invention is not limited to the memory system.
[0046]
One embodiment (first embodiment) of the present invention will be described.
FIGS. 4, 6 and 1 show the wiring and connection between the memory controller and the memory module, and FIGS. 28 to 31 and 35 show details of the memory controller. Details are shown in FIGS. 21, 40, and 41. 13 to 16, FIGS. 18 to 20, and FIGS. 22 to 25 show modifications of the mounted system.
[0047]
First, the basic connection of the board wiring pattern, the board wiring, and the connector of the present embodiment will be mainly described with reference to FIG.
[0048]
The memory controller 32 has output circuits 11 and 12 and input circuits 13 and 14.
[0049]
Among them, the output circuit 11 and the input circuit 13 are circuits for clock signals, the output circuit 12 and the input circuit 14 are circuits for data signals, the wiring 15 is a clock wiring for transmitting a clock, and the wiring 16 is a data writing circuit. The wiring and wiring 17 are data reading wirings.
[0050]
Reference numerals 34A to 34F denote connectors to which a memory module or the like described later on which a memory element or the like is mounted is connected.
[0051]
The memory controller 32, the wirings 15, 16, 17 and the connectors 34A to 34F are mounted on a board (motherboard) as shown in FIG.
[0052]
The transmission lines 15A, 15B, 16A, and 17A are wirings drawn to the module when the memory controller 32 is mounted on a board (module) different from the motherboard. Even when the memory controller 32 is mounted on the motherboard, it may be drawn as needed depending on the layout on the motherboard, but is not always necessary.
[0053]
The connectors 34A to 34F are mounted in a line on the motherboard as shown in FIG. The wirings 15 to 17 extend from the memory controller 32 so as to sequentially intersect with the respective connectors 34A to 34F, turn back (U-turn) at the end of the connector farthest from the memory controller 32, and again from the connector 34F to the connector 34A. They are laid out so as to intersect sequentially. In FIG. 4, black circles (•) indicate connection portions between the wirings 15 to 17 and the connectors 34A to 34F.
[0054]
The clock wiring 15 and the data writing wiring 16 are connected to the connectors 34A to 34C... 34E by the turn-back positions of the respective wirings, and are connected to the connectors 34F to 34D to 34B after the turn-back positions.
[0055]
The data read wiring 17 is connected in a reverse relationship to the clock wiring 15 and the data write wiring 16. That is, the wirings 17 are connected to the connectors 34B to 34D... 34F by the turn-back position, and are connected to the connectors 34E to 34C to 34A after the turn-back position.
[0056]
By alternately arranging the wirings, the load applied to the wiring becomes uniform.
[0057]
In FIG. 4, the clock signal line 16, the write data signal line 17, and the read data signal line 18 are shown one by one. It goes without saying that it is good.
[0058]
The memory module 30 is mounted on the connectors 34A to 34F. Examples of the memory module are shown in FIGS. As shown in FIG. 18, a plurality of memory LSIs are mounted on the memory module 30. The memory LSI is preferably a clock synchronous memory, for example, an SDRAM. An SDRAM is a memory that fetches a control signal and an address signal or writes and reads data in synchronization with a clock.
[0059]
In the memory module 30, as shown in FIG. 19, the data line is such that the contact 36 of the module and the pin of the SDRAM are connected 1: 1. As shown in FIG. 20, the control signal / address signal is connected between the contact 36 of the module and the pins of the plurality of SDRAMs. FIG. 20 shows an example in which signals are distributed to all SDRAMs. However, a case where signals are distributed from one contact 36 to a part of the SDRAM on the module, for example, a plurality of CASs (Column Address Strobes) in one module This is the case when a signal is input.
[0060]
In addition, as shown in FIG. 22, when the buffer circuit 61 enters between the contact 36 and the SDRAM, or when the resistance enters the data signal line as shown in FIG. 23, the control signal / address signal line as shown in FIG. In some cases, both the buffer circuit 61 and the resistor 60 may enter as shown in FIG.
[0061]
The resistors inserted in FIG. 23 and the like are resistors for impedance matching between the wiring on the motherboard and the wiring on the memory module. For details, refer to Japanese Patent Application No. 5-334631 filed earlier by the present applicant. (Japanese Patent Application Laid-Open No. 7-202947) and Japanese Patent Application No. 7-26495 (Japanese Patent Application Laid-Open No. 7-283836).
[0062]
FIG. 21 shows a circuit in which one SDRAM of the memory module 30 is noted and all other circuits are omitted. The SDRAM of FIG. 21 shows a type in which an input circuit and an output circuit are separated. The SDRAM has an input circuit 50 for capturing a clock, an input circuit 51 for capturing data, and an output circuit 52 for outputting data.
[0063]
The current SDRAM is an input / output type in which an input part of an input circuit and an output part of an output circuit are common in an LSI, which will be described later. The operation will be briefly described below, taking as an example a pin specification of a type separated from the output section of the circuit.
[0064]
The SDRAM 31 synchronizes with a clock fetched by the input circuit 50, fetches data with the input circuit 51, or outputs data from the output circuit 52, and writes or reads data in synchronization with the clock signal. are doing.
[0065]
Normally, in the memory system of the present embodiment, the above-described memory module 30 is realized by being connected to all or a part of the connector 34.
[0066]
Hereinafter, a processing example of writing data to the memory module 30 in the memory system in which the memory module 30 illustrated in FIG. 21 is connected to each connector of the motherboard illustrated in FIG. 4 will be described.
[0067]
The memory controller 32 outputs write data and a clock signal from the output circuits 12 and 11, respectively. The clock signal may be transmitted when writing processing is performed, or may be constantly output.
[0068]
The output clock signal is transmitted through the clock wiring 15, transmitted to the connectors in the order of the connectors 34A, 34C,..., 34E, 34F,..., 34D, 34B, and returns to the memory controller again. Since the write data is connected to the connectors in the same order as the clock wiring, the write data is transmitted to each connector in the same order.
[0069]
The SDRAM 31 of the memory module 30 connected to an arbitrary connector 34 takes in data from the previous input circuit 51 in synchronization with the clock signal received by the input circuit 50.
[0070]
When the memory controller reads data, the memory controller 32 issues a control signal including a clock signal and an address for reading data. Similarly to the above-described writing, the control signal output from the memory controller 32 is received by the SDRAM 31.
[0071]
The SDRAM 31 outputs the corresponding data from the output circuit 52 to the data read wiring 17 in synchronization with the clock signal received by the input circuit 50.
[0072]
The data read wiring 17 is connected to the connector in the reverse order of the data write data. Assuming that the memory module is connected to the connector 34, the data output from the output circuit 52 by the SDRAM 31 is transmitted from the connector 34A to the connection points between the connectors 34C,..., 34E, 34F,. And get to the memory controller. The clock signal used when SDRAM 31 outputs data is used for synchronizing data output by connector 34A. The clock signal returns from the connector 34A to the memory controller through the connection points with the connectors 34C,..., 34E, 34F,.
[0073]
The memory controller 32 takes in the data read by the receiving circuit 14 in synchronization with the clock signal returned via the clock wiring received by the receiving circuit 13.
[0074]
Until the read data reaches the memory controller 32 from the memory module 30 and the clock signal reaches the memory controller 32 from the position of the memory module 30, the read data follows substantially the same distance. It is not necessary to be aware of the difference in delay between circuits.
[0075]
In this manner, the time (distance) for the clock signal and the write data signal to reach an arbitrary memory module can be substantially adjusted regardless of the connection position of the memory module. Further, the time until the read data arrives from the memory module and the time from when the clock signal returns to the memory controller from the position of the memory module can be substantially matched.
[0076]
Thus, irrespective of the position of the memory module, the sum of the propagation time at the time of writing data and the propagation time at the time of reading becomes a substantially constant value.
t window> tpd (max-min) + t setup (max) + t hold (max)
In, the value of tpd (max-min) can be reduced and the margin of the window can be secured.
[0077]
In other words, as mentioned earlier, time
t window-tpd (max-min)
, The time longer than the setup time and the hold time can be easily taken.
[0078]
Note that, as shown in FIG. 4, a connector connection method in which the connection between the connector and the wiring is alternately set before and after the return position of the wiring is an example.
[0079]
In the clock wiring 15, a portion from the output circuit 11 to the connector 34F (farthest from the memory controller) is a "going portion", and a portion from the connector 34F to the input circuit is a "returning portion". Also, the part from the output circuit 12 to the connector 34F is a “going part”, the remaining part (that is, the part returning to the memory module side ahead of the going part) is a “return part”, and the read data Regarding the wiring, the portion from the connector 34F to the input circuit 14 is referred to as a “return portion”, and the remaining portion (ie, the portion from the connector 34A to the connector 34F before the return portion) is referred to as a “going portion”. Then, the connector may be connected according to the following rules.
[0080]
(1) When the clock wiring is connected to the connector at the "going part",
・ The wiring for write data is connected to the connector at the “going part”,
• Wire the read data at the “return part”.
[0081]
(2) When the clock wiring is connected to the connector at the "return part",
・ Write data wiring is connected to the connector at the “return part”.
• Wire the read data at the “going part”.
[0082]
In order to further improve the accuracy, the wiring layout may be performed in consideration of the following.
[0083]
(1) Match the wiring length of the wiring 15 from the output circuit 11 to the input circuit 50 in the module with the wiring length of the wiring 16 from the output circuit 12 to the input circuit 51 in the module, or adjust the wiring load.
[0084]
(2) The wiring length of the wiring 16 from the output circuit 12 to the input circuit 51 in the module and the wiring length of the wiring 17 from the output circuit 52 to the input circuit 14 in the module are matched between the modules, and the wiring load is reduced. Match.
[0085]
Increasing the accuracy of adjusting the wiring length or the wiring load has the effect of increasing the value of t window-tpd (max-min).
[0086]
As a means for offsetting the phase of the clock,
(1) A method in which a circuit for causing a propagation delay, for example, a delay circuit, is provided on any one of a memory controller and clock wiring distributed to each memory module. This circuit may be placed on all the wirings, or may be placed on only one of the signals.
[0087]
(2) A method in which the delay circuit function of (1) is provided on the clock transmission source, or on the distribution / division source side. At this time, it is better to make the delay adjustable by an external pin. For this purpose, several delay circuits are built in these clock sources, and a method of selecting them from the outside or preparing a plurality of delay circuits and determining how many of those circuits are used by the external circuit. There is a method to specify from.
[0088]
Further, in the wiring connecting the memory controller and the connector, when connecting a clock signal or a data signal to the connector, rather than connecting only the “going part” or the “return part (or the return part)”, “ It is better to disperse and connect to the “going part” and the “return part (or return part)”. This is because the load due to the connection to the connector can be dispersed, and the drop in the effective impedance of the signal wiring can be suppressed.
[0089]
The following are the effects of suppressing the drop of the impedance.
[0090]
(1) When the output of the output circuit is switched, it is possible to suppress a drop in signal amplitude transmitted to the memory module first.
[0091]
In particular, in the case of a small-amplitude signal, the signal amplitude of the first wave output from the output circuit due to a drop in impedance is reduced, and as a result, the noise margin of the input signal is reduced, which prevents a malfunction from occurring.
[0092]
(2) The quality for various uses can be improved.
[0093]
Depending on how the user uses the memory module, the module may be fully mounted on all connectors, or the module may be mounted on some connectors and other connectors may be left empty. In this way, when the usage changes, in order to guarantee the performance in all states, the performance margin can be secured by reducing the characteristics of the device, in this case, the amount of change in the effective impedance of the wiring, Quality can be improved.
[0094]
As shown in FIG. 4, a method of connecting to a connector that maximizes these effects is a method of alternately connecting a “going part” and a “returning part (or return part)”.
[0095]
Further, as a method of suppressing the drop of the impedance, there is a method of using a signal wiring in which the impedance of the wiring 15, 16, or 17 is lower than the impedance of the module. For example, it is set to around 50Ω (for example, 40 to 60Ω).
[0096]
By mounting the module, the effective impedance is reduced to 20 to 40Ω, and this value is almost the same whether the wiring is 50Ω or 75Ω. That is, in this case, the difference in impedance before and after mounting the module can be reduced by using the wiring of 50Ω.
[0097]
In the present embodiment, an example in which four circuits 11 to 14 are provided in one circuit block 32 has been described. However, it is needless to say that the scope of the present invention is not limited by the configuration. May be divided into a plurality of circuit blocks. However, the configuration having four circuits in one circuit block 32 is superior in terms of performance and manufacturing cost.
[0098]
Considering the current configuration of the memory controller, it is also desirable to separate only the output circuit that outputs the clock signal into another circuit block.
[0099]
Further, in this embodiment, an example is shown in which both data writing to the memory module and reading of data from the memory module are applied, but the clock distribution of the present invention is used only for data writing, and Conventional techniques can also be applied. Such an eclectic configuration with the conventional technology may be acceptable, and alternative examples of the circuit configuration are the same in the following embodiments.
[0100]
FIG. 6 shows an example in which a terminating resistor is added to the wirings 15 to 17 in the embodiment shown in FIG. In FIG. 6, reference numerals 40 to 45 represent terminating resistors. Of course, the terminating resistor is connected to the terminating power supply.
[0101]
FIG. 6 shows an example in which both ends are terminated. In order to perform the termination more effectively, it is preferable to terminate at both ends. However, when the direction of the signal is only one side, for example, in the case of a control signal line or an address signal line, the termination may be one side. At that time, the termination point is preferably on the opposite side of the output circuit.
[0102]
Although the resistance value of the terminating resistor is often terminated at the impedance of the transmission line, it is preferable to terminate at the effective impedance value of the transmission line in order to make it more effective. However, even if this value is not strictly adjusted, there is an effect of termination even if there is a deviation of about ± 20Ω.
[0103]
In FIG. 1, matching resistors (46, 47, 48, 49) for impedance matching between the wirings are inserted between the branch wirings (15A, 15B, 16A, 17A) and the wirings (15, 16, 17). Here is an example. The matching resistor is inserted for the purpose of reducing the amplitude of the signals on the wirings 15 to 17 and matching the impedance between the wirings to suppress signal reflection at the branch point of the wiring.
[0104]
The matching resistance is described in detail in Japanese Patent Application No. 5-334631 (Japanese Patent Application Laid-Open No. Hei 7-202947) and Japanese Patent Application No. Hei 7-26495 (Japanese Patent Application Laid-Open No. Hei 7-283836) previously filed by the present applicant. .
[0105]
This resistor has an effect of suppressing reflection at a branch point in signal propagation from the branch wiring to the main wiring. This resistance value is preferably set to a value obtained by subtracting half the impedance value of the wiring (15, 16, 17) from the impedance value of the branch wiring (15A, 15B, 16A, 17A). However, in a case where the effective impedance of the main wiring is reduced by mounting the memory module on the main wiring, the effective impedance value of the main wiring may be used instead of the impedance value of the main wiring.
[0106]
It is desirable that the reference resistance value is in the range of about 0.5 to 1.5 times the previously obtained value. However, even if it is about twice, it is effective in increasing the speed by reducing the amplitude.
[0107]
When the matching resistors (46, 47, 48, 49) shown in FIG. 1 are provided as described above, it is desirable that the memory module side also has resistors as shown in FIGS. It is desirable that this resistor also has a value that achieves impedance matching between the wiring in the memory module and the wiring (15, 16, 17) on the motherboard, and realizes a low amplitude signal on the wirings 15 to 17. The method of determining the resistance value of this resistor is the same as that of the matching resistors 46 to 49 described above. At that time, the branch wiring is calculated as the wiring in the memory module.
[0108]
Next, another embodiment (Embodiment 2) of the present invention is shown in FIG. What has been clarified in the above embodiments can be applied to the following embodiments, and will not be repeated. Clarify only the differences.
[0109]
In the present embodiment, the clock signal output from the memory controller is separated into a read clock and a write clock, and the direction of transmission of the clock signal is changed between the same clock wiring 15 at the time of reading and at the time of writing. This is a transmission method. Here, the output circuit for the write clock is 11, the output circuit for the read clock is 11 A, and the receiving circuit for receiving the clock for reading the read data by the memory controller is 13. Reference numerals 12 and 14 denote a circuit 12 for outputting data and a circuit 14 for receiving data, respectively.
[0110]
Although not shown in FIG. 5, it is desirable that the memory controller 32 has a logic circuit for controlling each output so that both the output circuits 11 and 11A do not operate and be used.
[0111]
As in the first embodiment, the portion of the clock wiring 15 from the output circuit 11 toward the connector 34F (farthest from the memory controller) is referred to as the "going portion" and the end of the "going portion", that is, from the connector 34F. The portion going to the connector 34A is the “return portion”, the portion of the data wiring 16 from the output circuit 12 to the connector 34F is the “going portion”, and the remaining portion (that is, the memory module side ahead of the going portion). If the "return part" is defined as the "return part", the connector may be connected according to the following rules.
[0112]
(1) When the clock wiring is connected to the connector at the "going part",
・ Connect the data wiring to the connector at the “going part”.
[0113]
(2) When the clock wiring is connected to the connector at the "return part",
・ Connect the data wiring to the connector at the “return part”.
[0114]
By doing so, the same effect as that of the first embodiment can be achieved by reducing the data signal wiring by half, that is, from two sets of write-only wiring and read wiring to one set of common writing and reading. I can do it.
[0115]
The output part of the output circuit for the write clock signal and the input part of the input circuit for the read clock may be connected inside or outside the circuit block (integrated circuit or component). (FIG. 5 shows an example of connection within a circuit block.)
Further, the second embodiment is an example in which a memory LSI mounted on a memory module is common to I / O, that is, applied to a type having an input / output circuit having both an input circuit and an output circuit. In this embodiment, the circuit in the module to be used has a configuration shown in FIG. 26 in comparison with FIG. 21 of the first embodiment. An output circuit 51 for outputting data and the like and a receiving circuit 52 for receiving the data are connected.
[0116]
FIG. 7 shows a type in which the memory controller 32 is connected to the wirings 15 and 16 via the branch wirings 15A to 16A in the second embodiment (the same type as FIG. 6 of the first embodiment), and FIG. This is a type in which matching resistors 46 to 48 are interposed between the branch wirings 15A to 16A and the wirings 15 and 16 (the same type as FIG. 1 of the first embodiment).
[0117]
Next, a third embodiment will be described. Although the first and second embodiments have been described with respect to the bidirectional signal such as the data signal, the unidirectional transmission of the address signal or the control signal is shown in FIGS. 9 to 11. As described above, this can be easily achieved by eliminating the path in which the clock returns to the memory controller. This can be applied to only a line used only for writing a data signal.
[0118]
In this case, two types of clocks, that is, a data clock and another signal clock, are supplied to each memory module. However, an address signal and a control signal may be captured using a data clock circuit. . At this time, when there are two clocks as in the second embodiment, the SDRAM can fetch the address signal and the control signal using the write-only clock. The circuit in the memory module at this time is of the type shown in FIG. 27 in comparison with FIG. 21 in the first embodiment.
[0119]
FIG. 12 shows a fourth embodiment as an application of the second embodiment. A method is provided that allows a clock signal to be propagated in only one direction, as in the first embodiment, when a memory controller common to I / O is used.
[0120]
That is, a clock signal is output from the output circuit 11, and a write data signal is output from the output circuit 12. At this time, the switch 90 connects the input / output circuit (divided into the output circuit 12 and the input circuit 14 in the figure) and the transmission line 16A. By doing so, the clock signal and the data signal can be transmitted to the memory module on the connector from the memory controller 32 to the connectors 34A to 34F via substantially equal wiring lengths.
[0121]
At the time of reading, the switch 90 connects the input / output circuit and the transmission line 16B, and latches the data transmitted from 16B by the clock transmitted from 15B. By doing so, the clock control method shown in the first embodiment can be used for a circuit having a data line common to I / O.
[0122]
In the first to fourth embodiments described so far, the clock for fetching data generally has a different phase from the clock inside the memory controller. That is, in order to use the read data further in the memory controller, it is necessary to switch the clock (here, switch from the return clock to the internal clock) so that the read data can be controlled again by the clock in the memory controller. Therefore, a retiming circuit, for example, a FIFO (First-in First-out) circuit may be provided before the input circuit 14. Further, the memory controller may have a means for determining which cycle of the internal clock should be latched based on the magnitude of the phase shift between the clock transmitted through the wiring 15 and the internal clock.
[0123]
Further, by using a wiring length, a delay circuit, and the like to match the phases of the output clock and the returning clock, data can be easily captured.
[0124]
FIG. 35 shows an example in which one embodiment of the retiming circuit is provided in the memory controller 32. The retiming circuit includes at least a D-type latch circuit 25A and a flip-flop circuit 25B. The D-type latch circuit 25A passes the input data when the input clock is High (or Low), passes the data when the input clock is switched to Low (or High), and changes the clock to High (or Low) again. Has the function to hold up to.
[0125]
The return clock, 2φ ′ positive logic or non-logic is input as a clock to the D type latch circuit 25A, and the internal clock of the memory controller 32, 2φ positive logic or negative logic is input to the flip-flop circuit 25B. Input as a clock.
[0126]
Which of these clocks to use is uniquely selected depending on the magnitude of the phase difference between the clock 2φ inside the memory controller 32 and the returned clock 2φ ′.
[0127]
For example, if the magnitude of the phase difference between 2φ and 2φ ′ is shifted by exactly half a phase, a 2φ ′ negative logic clock is input to the D-type latch circuit 25A in order to correct the deviation, A 2φ positive logic clock is input to the flip-flop circuit 25B.
[0128]
When the magnitude of the phase difference between 2φ and 2φ ′ is exactly the same, a 2φ ′ positive logic clock is input to the D-type latch circuit 25A, and the 2φ positive logic clock is input to the flip-flop circuit 25B. Clock is input.
[0129]
Further, as another embodiment, when the respective phases match, the flip-flop circuit 25B becomes unnecessary, so that the output of 25A may be directly transmitted to the inside of the memory controller.
[0130]
When a clock for operating the memory module is supplied to each of the memory modules via a separate wiring in addition to the clock output from the memory controller 32, the above-described retiming circuit may be provided on the memory module side.
[0131]
FIG. 36 shows an embodiment in which the retiming circuit shown in FIG. 35 is applied to the circuit of FIG. FIG. 36 shows an example in which the clock φ is output not from the memory controller but from the clock distribution circuit before the connector 34A. Although the clock supply method shown in FIG. 1, that is, the clock φ may be supplied from the memory controller, the clock access time of the memory controller is generally faster than the clock access time of the memory LSI. For this reason, reading becomes more severe than writing. For this reason, the clock output circuit is moved from the inside of the memory controller to the position before the connector 34A, the clock phase is brought forward, and the time required for writing and reading is adjusted.
[0132]
Although the present embodiment has been described by taking the second embodiment shown in FIG. 12 as an example, it goes without saying that the present embodiment can be applied to other embodiments. FIG. 36 shows an example in which the PLL (Phase Locked Loop) 70 (A) with the frequency dividing circuit 71 is outside the memory controller. The clock signal supplied from the clock signal transmission circuit 360 via the clock distribution circuit 361 and the like is divided. Needless to say, the PLL 70 (A) may be inside the memory controller.
[0133]
FIG. 37 shows a fifth embodiment of the present invention. In this embodiment, the transmission lines 15 and 16 are laid out over the two connector rows 34A to 34F and 34G to 34M.
[0134]
In the embodiment described above, an example is shown in which the connector row connected on “outgoing wiring” and the connector row connected on “return wiring” are the same. The connector row (34A to 34F in the example shown) connected on the “going wiring” is different from the connector row (34G to 34M in the example shown) connected on the “return wiring”. As a result, the number of transmission lines laid out under the connector is reduced by half (from "going wiring" and "return wiring" to either "going wiring" or "return wiring"). In addition, the layout can be simplified and the number of signal wiring layers on the substrate can be reduced.
[0135]
FIG. 37 shows an example in which the transmission lines 15 and 16 are connected to all connectors, but may be connected to some connectors, for example, every other connector.
[0136]
Of course, in the figures shown before FIG. 37, the connector is connected to either the “outgoing wiring” or the “return wiring”, but even if there is a connector that is not connected to either of the wirings. Good. For example, two wires are laid out in parallel, and wires connected to even-numbered connectors, ie, 34B, 34D,..., 34F, and wires connected to odd-numbered connectors, ie, 34A, 34D,. And may be divided into
[0137]
Further, the embodiment shown in FIG. 37 can be applied not only to the embodiment shown in FIG. 36 and also to the embodiment shown in FIG. 12 based on FIG. 36 but also to other embodiments.
[0138]
Next, a sixth embodiment will be described. In the first to fifth embodiments, when the memory controller 32 receives the data read from the memory module 30, the data is received in synchronization with the clock signal output from the memory controller 32 and received through the wiring 15. In the sixth embodiment, a configuration is adopted in which a signal serving as a trigger for determining a timing for receiving data output from a memory module is issued from the memory module that outputs the data. The details will be described below.
[0139]
FIG. 46 shows a sixth embodiment.
[0140]
The memory controller 161 includes a clock output circuit 171, a clock-synchronous output circuit 172, an input circuit 181, and an input circuit 182 that synchronizes with a signal captured by the input circuit 181.
[0141]
The output circuit 172 and the input circuit 182 are data circuits.
[0142]
Further, the transmission lines 114 to 117 are wirings that are drawn depending on the case where the memory controller is modularized or depending on the layout on the motherboard, and are not always present, and the present invention is not limited by the presence or absence of the wirings. Absent.
[0143]
In the following embodiment, an example is shown in which these four circuits are configured by one circuit block, but these circuits may be separated into a plurality of circuit blocks.
[0144]
The wiring 110 is a clock necessary for a signal output from the memory controller 161 to be captured on each of the memory modules mounted on the connectors 140 to 145, and is a wiring for a signal output from the memory controller 161. is there.
[0145]
The wiring 111 is a wiring for transmitting a trigger signal (return clock) necessary for taking in the data read from the memory on the memory module by the memory controller, and this trigger signal is output from the read memory. .
[0146]
This trigger signal is different from the clock output from the memory controller, and only one pulse is output for one read data.
[0147]
Further, it is preferable that the trigger signal is delayed from the data by, for example, the setup time of the memory controller, so that the read data can be taken in by the memory controller. Further, in order to satisfy the hold time of the memory controller, it is desirable that the output of the memory hold data longer than the hold time of the memory controller after the trigger signal is output.
[0148]
In FIG. 46, the clock signal and the data signal in the memory circuit are focused one by one, and all the other circuits are omitted. Therefore, only one set of each of these input circuits and output circuits is shown. Needless to say, the number does not limit the present invention.
[0149]
Each wiring and connector are connected at the positions indicated by black circles (•).
[0150]
That is, in the example of FIG. 46, the clock signal output from the memory controller is transmitted on the signal transmission line 110 to the connectors 140, 142,. The data write signal wiring 112 is also connected to the connector in the same order as the clock wiring.
[0151]
The data read wiring 113 and the trigger signal wiring 111 output from the memory are connected to the connector in the reverse order of the data write data. That is, the data write wiring is connected from the memory controller to 141, 143,...
[0152]
By doing so, the sum of the propagation time at the time of writing data and the propagation time at the time of reading becomes uniform regardless of the position of the memory module.
[0153]
At this time, it is desirable to design such that the clock signal wiring, the trigger signal wiring and the data write wiring, or the read wiring have the same propagation time.
[0154]
When there is a connector that does not have a memory module, there is a method of suppressing a change in effective impedance due to a change in the number of mounted modules by mounting a load equivalent to that of the memory module as a dummy.
[0155]
In FIG. 46, one embodiment of the both ends is shown. However, as shown in FIG. 47, a signal that propagates in only one direction, such as the wirings 110 and 112, may be a one-side end. As a result, the number of components to be mounted can be reduced, and the current consumption can be reduced. When the lengths of the wirings 114 to 117 are sufficiently short, for example, when the propagation time of these wirings is about 1/6 or less of the rise time or fall time of the signal waveform, the resistors 150 to 153 can be removed. It is. However, in this case, since the signal amplitude in the bus 110 becomes large, it is desirable to review the signal amplitude itself output from the output circuit, such as lowering the amplitude. This example is shown in FIG.
[0156]
Further, the present circuit can be applied to a small-amplitude circuit disclosed by the applicant in Japanese Patent Application No. 5-334631 (Japanese Patent Application Laid-Open No. 7-202947). That is, the resistors 150 to 153 have an effect of suppressing reflection at a branch point in signal propagation from the branch wirings 114 to 117 to the main wiring 110. This resistance value is preferably set to a value obtained by subtracting the impedance of the main wiring from the impedance value of the branch wiring. However, when the effective impedance of the main wiring is reduced by mounting the memory module on the main wiring, a smaller value than the above value may be used.
[0157]
It is desirable that the reference resistance value is in the range of about 0.5 to 1.5 times the previously obtained value.
[0158]
Next, a seventh embodiment will be described below. It should be noted that what has been clarified in the above-described embodiment is also applicable to the following embodiments, and will not be described repeatedly. Clarify the differences.
[0159]
In the sixth embodiment, an example is shown in which the input circuit and the output circuit of the memory controller 161 and the memory module 162 are separated from each other, but FIG. In this case, one embodiment is shown. The input / output circuit is described, for example, by using a memory controller shown in the drawing. An output section of the output circuit 172 and an input section of the input circuit 182 are connected in a circuit block 161 (for example, an integrated circuit), and terminals of the circuit block are provided. Is a circuit that is not separated and serves as a common terminal.
[0160]
In this case, the switch 190 is inserted, and the switch is connected to the circuit block transmission line 161 side when writing data and to the transmission line 117 side when reading data.
[0161]
As a result, the same effects as those of the first embodiment can be applied to a system having an input / output circuit. 50 is an example in which the circuit of FIG. 49 is terminated on one side, as in FIG. 47, and FIG. 51 is an example, in which the insertion resistance is deleted, as in FIG.
[0162]
The circuit diagrams shown in FIGS. 53 and 54 focus on one memory in the memory module. FIG. 53 is a circuit diagram of a module applied to the embodiment shown in FIG. For clock input, the output circuit 171 is a circuit for outputting a trigger signal serving as a return clock, the output circuit 172 is a circuit for outputting read data, and the input circuit 182 is a circuit for inputting write data. FIG. 54 shows an example of a circuit in which a data signal is output and input by an input / output circuit.
[0163]
In general, there is one input circuit 181 for inputting a clock signal, and one input circuit 181 captures write data, a control signal, and an address signal with a clock input by this circuit.
[0164]
The other embodiment shown in FIG. 52 is an example in which “outgoing wiring” and “return wiring” are passed through different connector rows. By doing so, the “outgoing wiring” and the “returning wiring” can be laid out in the same layer on the substrate wiring, and the present invention can be realized without increasing the number of substrate layers.
[0165]
The circuit diagram shown in FIG. 55 is a circuit showing in detail the output circuit and the input circuit of the clock signal and the data signal of the memory controller in the present invention.
[0166]
The flip-flops 191D and 191S operate in synchronization with the internal clock, and the flip-flop 191L operates in synchronization with a trigger signal from the memory received by the input circuit 181.
[0167]
As a result, the write data output from the memory controller is output in synchronization with the internal clock of the chip, and the data read from the memory is received by the trigger signal while securing the setup and hold time, and the next flip-flop is output. Retiming to the internal clock (the phase is adjusted to the internal clock).
[0168]
By doing so, the exchange of signals from the memory controller to the processor bus can be performed in phase with the internal clock.
[0169]
In the present embodiment, the flip-flop 191S used for retiming is shown as an example of one stage. However, the number of stages is not limited to one stage. The phase of the clock can be realized by taking the phase between the internal clock and the trigger signal, or by using a multiple clock of the internal clock in a plurality of stages.
[0170]
Next, the improvement of the clock signal transmission in the present invention will be described. In the foregoing embodiment, the clock signal will operate under the same load as the data signal. However, for example, in order to transfer data at 100 HMz, the clock cycle must be 10 ns (frequency is 100 MHz) and the data cycle is 20 ns (cycle is 50 MHz). Must. Therefore, a method for more stably supplying a clock according to the present invention will be described below.
[0171]
First, the frequency (period) of the clock is made the same as that of a signal such as data. Then, a clock which is twice the input clock is generated in the module or the memory LSI, and the SDRAM signal is fetched and output is controlled in synchronization with the generated clock.
[0172]
A similar function is also provided on the memory controller side.
[0173]
In addition, the method of doubling is used. In order to stabilize the duty to around 50%, it is preferable to use a PLL to quadruple the frequency, then divide the frequency by 2 to return to double. In general, N may be a natural number, multiplied by 2 (N + 1), and divided by N + 1.
[0174]
These are shown in FIGS. 28 to 34. FIG.
[0175]
In FIG. 28, a clock φ having a frequency 0.5 times the clock 2φ is generated by using a PLL (Phase Locked Loop) 70 with a frequency dividing circuit 71, and the clock is output from the memory controller 32 using the output circuit 11. I do. In addition, a signal is output from the output circuit 12 in synchronization with the original clock 2φ.
[0176]
FIG. 29 shows an embodiment in which a PLL (Phase Locked Loop) 70 with a frequency dividing circuit 71 is located ahead of the output circuit 11. According to this method, the present invention can be applied to the memory controller 32 having no PLL (Phase Locked Loop) 70 with the frequency divider 71.
[0177]
In FIG. 30, the clock φ ′ received by the receiving circuit 13 is doubled in frequency using a PLL (Phase Locked Loop) 70 with a frequency divider 71 to generate a clock 2φ ′, and the clock 2φ ′ is used to generate a clock 2φ ′. The signal received at 14 is latched by flip-flop 25. Here, the clock to be latched is 2φ ′, not the clock 2φ supplied inside the memory controller. Although 2φ and 2φ ′ have the same frequency, 2φ ′ is a clock generated from φ ′, which is a clock that has returned from the memory controller and has returned, and generally has a different phase.
[0178]
FIG. 31 shows an embodiment in which a PLL (Phase Locked Loop) 70 with a frequency dividing circuit 71 is located before the receiving circuit 13. According to this method, the present invention can be applied to a memory controller having no PLL (Phase Locked Loop) 70 with a frequency dividing circuit 71.
[0179]
FIG. 32 shows an embodiment of the clock output circuit and the input / output circuit. A clock φ having half the frequency of the internal clock 2φ is generated by a PLL (Phase Locked Loop) 70 with a frequency dividing circuit 71, and the clock is output from the memory controller by the output circuit 11. The clock φ ′ returned to the memory controller is received by the input circuit 13, and a clock 2φ ′ having a double frequency is generated by a PLL (Phase Locked Loop) 70 with a frequency dividing circuit 71. Data output from the output circuit 12 is output in synchronization with the clock 2φ, and data received by the reception circuit 14 is received in synchronization with the clock 2φ ′.
[0180]
FIG. 33 shows an embodiment in which a PLL (Phase Locked Loop) 70 with a frequency dividing circuit 71 is provided before the output circuit 11 and before the input circuit 13 as in FIG.
[0181]
FIG. 34 shows an embodiment in which a PLL (Phase Locked Loop) 70 with a frequency dividing circuit 71 is used for a memory module. In order to supply φ ′ transmitted on the memory bus to the synchronous memory 31, for example, the clock pin of the SDRAM, the PLL with the frequency dividing circuit 71 ( Using a Phase Locked Loop (70) 70, the frequency is doubled to generate a clock 2φ ', which is supplied to the memory 31.
[0182]
In the examples shown in FIGS. 32 and 33, an example of an I / O circuit type memory controller having both a receiving circuit and an output circuit has been shown. However, in FIGS. It is applied to an I / O separated type memory controller having separate terminals. The difference between FIG. 38 and FIG. 39 is the difference between the case where the PLL circuit is inside the memory controller and the case where it is outside, like the difference between FIG. 32 and FIG.
[0183]
Further, a memory module shown in FIG. 40 is provided for an I / O separated type memory module. This is an application example of the I / O separation type with respect to FIG. 34 of the I / O circuit type.
[0184]
The present invention also relates to a memory module having a register type buffer (FIG. 42) and a memory having a simple buffer (a buffer used as an intermediate buffer and not latching, also referred to as a through type or a bus driver). It is also applicable to the module (FIG. 43).
[0185]
Also, the present invention is naturally effective when a resistor is inserted on the memory module side as well as the embodiment of the present invention which has been clarified so far. With this resistor, not only the amplitude can be reduced, but also impedance matching can be achieved, and reflected noise can be prevented.
[0186]
41 shows an embodiment in which a resistor is added to FIG. 40, and FIGS. 44 and 45 show one embodiment in which a resistor is added to FIGS. 42 and 43, respectively.
[0187]
13 and 14 show a state of a board on which an embodiment of the present invention is realized. FIG. 13 shows a state in which a memory controller 32 is directly mounted on a motherboard, and a memory module 30 in which a memory IC (SDRAM) 31 is mounted on a daughter board is mounted on the motherboard via a connector 34.
[0188]
FIG. 14 is an example in which the memory controller 32 is mounted on a daughter board and modularized. 15 and 16 show an example in which the memory IC 31 is directly mounted on a motherboard without using a connector.
[0189]
Some of the embodiments described above can also be used to connect a cache memory to a processor. Further, as shown in FIG. 17, in a workstation or a personal computer, there are various buses such as a processor bus, a memory bus, and a peripheral bus. In the present invention, the connection between the memory module and the memory module has been described as an example. However, the present invention is not limited to the memory bus, but is effective regardless of whether other connectors are used, whether or not a connector is used, and whether or not a module is used. Needless to say. Further, the present invention can be applied to a multi-module in which a plurality of LSIs are contained in one package, instead of being mounted on a board.
[0190]
【The invention's effect】
According to the present invention, it is possible to perform a design capable of high-speed signal transfer even in a system such as a memory system in which the signal propagation time is long and the delay time differs depending on the module position.
[Brief description of the drawings]
FIG. 1 is a diagram showing a connection relationship and a wiring pattern between a memory controller and a memory module in an application example of the first embodiment of the present invention.
FIG. 2 is a diagram showing a conventional single-phase clock system signal transmission device.
FIG. 3 is a diagram showing a mounting structure and a circuit of a conventional memory system.
FIG. 4 is a diagram showing a connection relationship and a wiring pattern between a memory controller and a memory module according to the first embodiment of the present invention.
FIG. 5 shows a connection relationship and a wiring pattern between a memory controller and a memory module according to a second embodiment of the present invention. FIG. 11 is a diagram illustrating an example in which the direction of a clock signal is inverted between a read time and a write time when the present invention is applied to a common input / output circuit.
FIG. 6 is a view showing a connection relationship and a wiring pattern between a memory controller and a memory module according to an application example of the first embodiment of the present invention.
FIG. 7 is a diagram showing a connection relationship and a wiring pattern between a memory controller and a memory module in an application example of the second embodiment of the present invention.
FIG. 8 is a diagram showing a connection relationship and a wiring pattern between a memory controller and a memory module in an application example of the second embodiment of the present invention.
FIG. 9 shows a connection relationship and a wiring pattern between a memory controller and a memory module according to a third embodiment of the present invention. The figure which shows the example applied to the unidirectional signal transmission.
FIG. 10 is a view showing a connection relationship and a wiring pattern between a memory controller and a memory module in an application example of the third embodiment of the present invention.
FIG. 11 is a diagram showing a connection relationship and a wiring pattern between a memory controller and a memory module in an application example of the third embodiment of the present invention.
FIG. 12 is a diagram showing a connection relationship and a wiring pattern between a memory controller and a memory module according to a fourth embodiment of the present invention.
FIG. 13 is a diagram showing a mounting structure when the present invention is applied to a memory system.
FIG. 14 is a diagram showing a mounting structure when the present invention is applied to a memory system.
FIG. 15 is a diagram showing a mounting structure when the present invention is applied to a memory system.
FIG. 16 is a diagram showing a mounting structure when the present invention is applied to a memory system.
FIG. 17 is a block diagram of an information processing system.
FIG. 18 is a diagram showing an outer shape of a memory module.
FIG. 19 is a diagram showing data signal wiring on a memory module.
FIG. 20 is a diagram showing address / control / clock signal wiring on a memory module.
FIG. 21 is a diagram showing an input / output separated type SDRAM circuit on a memory module.
FIG. 22 is a diagram showing signal connections when a buffer circuit is inserted on the address / control / clock signal wiring on the memory module.
FIG. 23 is a diagram showing signal connection when a resistor is inserted on a data signal wiring on a memory module.
FIG. 24 is a diagram showing signal connection when a resistor is inserted on an address / control / clock signal wiring on a memory module.
FIG. 25 is a diagram showing signal connections when a buffer circuit and a resistor are inserted on the address / control / clock signal wiring on the memory module.
FIG. 26 is a diagram showing an input / output common type SDRAM circuit on a memory module.
FIG. 27 is a diagram showing an address / control / clock signal input circuit of the SDRAM on the memory module;
FIG. 28 is a diagram showing a clock output circuit of the memory controller in which the PLL circuit is inside the memory controller.
FIG. 29 is a diagram showing a clock output circuit of a memory controller in which a PLL circuit is provided outside the memory controller;
FIG. 30 is a diagram showing a clock input circuit of the memory controller in which the PLL circuit is inside the memory controller.
FIG. 31 is a diagram showing a clock input circuit of a memory controller in which a PLL circuit is provided outside the memory controller;
FIG. 32 is a diagram showing an input / output common type memory controller in which a PLL circuit is provided inside the memory controller;
FIG. 33 is a diagram showing an input / output common type memory controller in which a PLL circuit is provided outside the memory controller;
FIG. 34 is a diagram showing clock input in a memory module having a PLL circuit.
FIG. 35 is a diagram showing a memory controller including a retiming circuit.
FIG. 36 is a diagram showing a memory system of the present invention using the retiming circuit of the present invention.
FIG. 37 is a diagram showing a fifth embodiment of the present invention.
FIG. 38 is a diagram showing a clock output circuit of an input / output separated memory controller in which a PLL circuit is provided inside the memory controller;
FIG. 39 is a diagram showing a clock output circuit of an input / output separated memory controller in which a PLL circuit is provided outside the memory controller;
FIG. 40 is a diagram showing a clock input in a memory module having an input / output separated SDRAM circuit.
FIG. 41 is a diagram showing a clock input in a memory module having an insertion resistor and an input / output separated SDRAM circuit.
FIG. 42 is a diagram showing a memory module having a register type buffer circuit and an input / output common SDRAM circuit;
FIG. 43 is a diagram showing a memory module having a through type buffer circuit and an input / output common SDRAM circuit;
FIG. 44 is a diagram showing a memory module having an insertion resistor, a through-type buffer circuit, and an input / output common type SDRAM circuit.
FIG. 45 is a view showing a memory module having an insertion resistor, a register type buffer circuit, and an input / output common type SDRAM circuit;
FIG. 46 is a diagram showing a sixth embodiment of the present invention.
FIG. 47 shows a modification of the sixth embodiment of the present invention. The figure which shows the bus structure of one end.
FIG. 48 is a view showing a modification of the sixth embodiment of the present invention.
FIG. 49 is a diagram showing a seventh embodiment of the present invention.
FIG. 50 is a view showing a modification of the fourth embodiment.
FIG. 51 is a view showing a modification of the fourth embodiment.
FIG. 52 is a diagram showing a retiming circuit;
FIG. 53 is a view showing one embodiment of a memory module circuit connected to the sixth embodiment;
FIG. 54 is a view showing one embodiment of a memory module circuit connected to the seventh embodiment;
FIG. 55 shows an eighth embodiment of the present invention.
[Explanation of symbols]
11, 11A, 12, 26 ··· output circuit, 13, 14, 27 ··· receiving circuit
24, 25 Flip-flop
25A-D type latch circuit, 25B-flip-flop circuit
15-17, 15A-15D, 23, 35, 37 ... transmission line
21, 22 ... Circuit block
30 memory module, 31 memory LSI, 32 memory controller
33 .. Motherboard, 34 .. Connector, 36 .. Contact point of module
38 Mark indicating contact between transmission line and connector
40 to 45-Terminating resistor (including terminal power supply)
46-49 ・ ・ Matching resistance
60 resistance
61. ・ Buffer circuit
70..PLL circuit 71..Division circuit
90 ・ ・ Switch circuit

Claims (20)

A first circuit block including a first output circuit that outputs a first signal and a first receiving circuit that receives a second signal;
A plurality of second circuit blocks each including a second receiving circuit that receives the first signal and a second output circuit that outputs the second signal;
In a signal transmission device having a wiring connecting the first circuit block and the second circuit block,
The first circuit block includes a third output circuit that outputs a third signal;
And a third receiving circuit for receiving the third signal.
The second circuit block has a fourth receiving circuit that receives the third signal,
The wiring includes a first wiring for transmitting the first signal, a second wiring for transmitting the second signal, and a third wiring for transmitting the third signal.
Laying back the first wiring, the second wiring, and the third wiring at positions farther from the second circuit farthest from the first circuit block;
When any one of the plurality of second circuit blocks and the third wiring are connected between the first circuit block and the turnback position, any one of the plurality of second circuit blocks is connected to the third wiring. Connecting the first wiring up to a folded position from the first circuit block,
When the connection position between the third wiring and any one of the plurality of second circuit blocks is ahead of the turnback position, the connection between any of the plurality of second circuit blocks and the second wiring is performed. Connect before the turn-back position,
When any one of the plurality of second circuit blocks and the third wiring are connected between the first circuit block and the folded position, any one of the plurality of second circuit blocks and the third wiring are connected to each other. Connecting the second wiring before the folded position,
When any one of the plurality of second circuit blocks is connected to any of the plurality of second circuit blocks before any of the plurality of second circuit blocks, the third wiring is connected to the second wiring block. Connecting between the first circuit block and the folded position,
The second receiving circuit latches the first signal in synchronization with the third signal received by the fourth receiving circuit,
The first receiving circuit latches the second signal in synchronization with the third signal received by the third receiving circuit,
The signal transmission device according to claim 2, wherein the second output circuit outputs the second signal in synchronization with the third signal received by the fourth reception circuit. The signal transmission device according to claim 1,
The signal transmission device according to claim 1, wherein the first, second, and third wirings include a terminating resistor. In the signal transmission device according to any one of claims 1 and 2,
A first branch wiring for transmitting the first signal between the first output circuit and the first wiring, a first branch wiring between the second receiving circuit and the second wiring; A second branch line for transmitting the third signal between the third output circuit and the third line; and a third branch line for transmitting the third signal between the third output circuit and the third line. A fourth wiring for transmitting the third signal between a receiving circuit and the third wiring,
The first branch wiring has a first resistance element,
The second branch wiring has a second resistance element,
The third branch wiring has a third resistance element,
The signal transmission device according to claim 4, wherein the fourth branch wiring has a fourth resistance element. The signal transmission device according to claim 3,
The resistance value of the first resistance element is in a range of half to twice a value obtained by subtracting a half value of the impedance of the first wiring from the impedance value of the first branch wiring, and The resistance value of the second resistance element is in a range from half to twice a value obtained by subtracting a half value of the impedance of the second wiring from the impedance value of the second branch wiring. The resistance value of the element is in a range of half to twice a value obtained by subtracting a half value of the impedance of the third wiring from the value of the impedance of the third branch wiring. A signal transmission device, wherein a resistance value is in a range of half to twice a value obtained by subtracting a half value of the impedance of the third wiring from the impedance value of the fourth branch wiring. A first circuit block having a first transmitting / receiving circuit including a first transmitting circuit for outputting a first data signal and a first receiving circuit for receiving a second data signal;
A second circuit block including a second receiving circuit that receives the first data signal and a second transmitting / receiving circuit that includes a second transmitting circuit that outputs the second data signal;
In a signal transmission device having a wiring connecting the first circuit block and the second circuit block,
A third transmission / reception circuit including a third output circuit that outputs a third clock signal and a third reception circuit that receives a fourth clock signal;
A fourth transmission circuit that outputs the fourth clock signal;
The second circuit block includes a fourth receiving circuit that receives the third clock signal and the fourth clock signal,
The wiring includes a first wiring for transmitting the first and second data signals between the first transmitting and receiving circuit and the second transmitting and receiving circuit, a third transmitting and receiving circuit, and the fourth receiving circuit. And a second wiring for transmitting the third and fourth clock signals between the fourth transmission circuit and the fourth reception circuit.
The first and second wirings are laid back at a position farther from the first circuit block than the second circuit block farthest from the first circuit block;
When any one of the plurality of second circuit blocks and the first wiring are connected between the first transmission / reception circuit and the turn-back position of the first wiring, the plurality of second circuit blocks are connected. And connecting the second wiring between the third transmission / reception circuit and the turn-back position of the second wiring,
When any of the plurality of second circuit blocks is connected to the first wiring before the first wiring is folded, any one of the plurality of second circuit blocks is connected to the second wiring. Connecting the folded back position of the second wiring first,
The second receiving circuit latches the first data signal in synchronization with the third clock signal, and the second output circuit latches the second data signal in synchronization with the fourth clock signal. Output a signal,
The signal transmission device according to claim 1, wherein the first receiving circuit latches the second data signal in synchronization with the fourth clock signal. The signal transmission device according to claim 5,
The signal transmission device according to claim 1, wherein the first and second wirings include a terminating resistor. The signal transmission device according to claim 5 or 6,
There is a third wiring for transmitting first and second signals between the first transmitting / receiving circuit and the first wiring, and between the third transmitting / receiving circuit and the second wiring. There is a fourth wiring for transmitting third and fourth signals, and a fifth wiring for transmitting a fourth signal between the fourth output circuit and the second wiring,
The third wiring has a first resistance element,
The fourth wiring has a second resistance element,
The signal transmission device according to claim 5, wherein the fifth wiring has a third resistance element. The signal transmission device according to claim 7,
The resistance value of the first resistance element is in a range from half to twice a value obtained by subtracting a half value of the impedance of the first wiring from an impedance value of the third wiring; The resistance value of the resistance element is in a range from half to twice the value obtained by subtracting half the impedance value of the second wiring from the impedance value of the fourth wiring, and the resistance value of the third resistance element is: A signal transmission device, wherein the value is in a range of half to twice a value obtained by subtracting a half value of the impedance of the second wiring from a value of an impedance of the fifth wiring. It has a first output circuit for outputting a first signal, a first receiving circuit for receiving the first signal, and a first input / output circuit for outputting a second signal and receiving a third signal. A first circuit block;
A plurality of second circuit blocks each including a third receiving circuit that receives the first signal, a fourth receiving circuit that receives the second signal, and a third output circuit that outputs a third signal. Have
A first wiring for transmitting the first signal and a second wiring for transmitting the second signal and the third signal, respectively, a second circuit furthest from the first circuit block; Or at a position further distant from the position, and laid out so as to return to the first circuit block again,
When any one of the plurality of second circuit blocks is connected to the first wiring between the first transmission circuit and the turn-back position of the first wiring, the plurality of second circuit blocks are connected. And connecting the second wiring between the first transmission / reception circuit and the turn-back position of the second wiring,
When any of the plurality of second circuit blocks is connected to the first wiring before the first wiring is folded, any one of the plurality of second circuit blocks is connected to the second wiring. Connecting the folded back position of the second wiring first,
The second wiring and the first input / output circuit are connected so that the second signal is transmitted in the same direction as the first signal, and the third signal is transmitted in the opposite direction to the first signal. A switch circuit with a switch function is inserted between them,
The third output circuit outputs a third signal in synchronization with the first signal;
The signal transmission device, wherein the first input / output circuit latches a third signal in synchronization with the first signal. The signal transmission device according to claim 9,
A signal transmission device, wherein the first wiring or the second wiring is terminated on one side or both sides. In the signal transmission device according to any one of claims 9 and 10,
There is a third wiring for transmitting a first signal between the first output circuit and the first signal wiring, and a second signal is provided between the switch circuit and the second signal wiring. A fourth wiring for transmitting a third signal, and a fifth wiring for transmitting a third signal between the switch circuit and the second signal wiring. The signal transmission device according to claim 11,
The third wiring has a first resistance;
The fourth wiring has a second resistance,
The signal transmission device according to claim 5, wherein the fifth wiring has a third resistor. The signal transmission device according to claim 12,
The resistance value of the first resistor is in a range of half to twice a value obtained by subtracting half the impedance value of the first wiring from the impedance value of the third wiring, and The value is in the range of half to twice as large as the value obtained by subtracting half the value of the impedance of the first wiring from the value of the impedance of the fourth wiring, and the resistance value of the third resistance is equal to the value of the fifth wiring. A signal transmission device characterized by being in a range of half to twice a value obtained by subtracting half of the impedance of the second wiring from the value of the impedance. The signal transmission device according to claim 12,
A signal transmission device, wherein a first input / output circuit receives a third signal in synchronization with a signal obtained by doubling a signal received by a first reception circuit. The signal transmission device according to claim 14,
A signal transmission device comprising: a phase adjustment circuit for converting a phase of a third signal received by a first input / output circuit into a signal that can be controlled in synchronization with the first signal. A first output circuit that outputs a first signal, a second output circuit that outputs a second signal, a first reception circuit that receives a third signal, and a second reception circuit that receives a fourth signal. A first circuit block having two receiving circuits;
A third receiving circuit for receiving the first signal, a fourth receiving circuit for receiving the second signal, a third output circuit for outputting a third signal, and outputting the fourth signal A plurality of second circuit blocks having a fourth output circuit,
A first wiring for transmitting the first signal, the second signal, the third signal, and the fourth signal between the first circuit block and the second circuit block; A wiring, a third wiring, and a fourth wiring,
Laying out the first, second, third, and fourth wirings at a position of a second circuit block furthest from the first circuit block or at a fold position farther from the position,
When any one of the second circuit blocks is connected to a wiring from the first circuit block to a position where the first wiring is turned back, any one of the second circuit blocks is connected to a third wiring. On the wiring ahead of the return position of the fourth wiring and on the wiring ahead of the return position of the fourth wiring,
In a case where any of the second circuit blocks is connected to the wiring ahead of the turn-up position of the first wiring, one of the second circuit blocks is connected to the first wiring from the first circuit block. 3 on the wiring up to the return position of the wiring and on the wiring from the first circuit block to the return position of the fourth wiring,
When any one of the second circuit blocks is connected to the wiring from the first circuit block to the turn-back position of the first wiring, any one of the second circuit blocks is connected to the second wiring From the turn-back position of the above on the wiring,
In a case where any of the second circuit blocks is connected to the wiring ahead of the turn-up position of the first wiring, one of the second circuit blocks is connected to the first wiring from the first circuit block. Connect on the wiring up to the folded position of the wiring of 2,
The fourth receiving circuit latches a second signal in synchronization with the first signal;
The fourth transmission circuit outputs a fourth signal in synchronization with the first signal;
A signal transmission device, wherein the second receiving circuit latches a fourth signal in synchronization with a third signal. In the signal transmission device according to claim 15 or 16,
The signal transmission device according to claim 1, wherein the first, second, third, and fourth wirings include a terminating resistor. The signal transmission device according to any one of claims 15 to 17,
A first branch wiring for transmitting a first signal between the first output circuit and the first wiring; a second branch wiring between the second output circuit and the second wiring; A second branch line for transmitting a signal; a third branch line for transmitting a third signal between the first receiving circuit and the third line; A fourth branch wiring for transmitting a fourth signal between the fourth wiring and the fourth wiring;
The first branch wiring includes a first resistor;
The second branch wiring includes a second resistor;
The third branch wiring includes a third resistor,
The signal transmission device according to claim 1, wherein the fourth branch wiring includes a fourth resistor. The signal transmission device according to claim 18,
The resistance value of the first resistance element is in a range of half to twice a value obtained by subtracting a half value of the impedance of the first wiring from the impedance value of the first branch wiring, and The resistance value of the second resistance element is in a range from half to twice a value obtained by subtracting a half value of the impedance of the second wiring from the impedance value of the second branch wiring. The resistance value of the element is in a range of half to twice a value obtained by subtracting a half value of the impedance of the third wiring from the value of the impedance of the third branch wiring. A signal transmission device, wherein a resistance value is in a range of half to twice a value obtained by subtracting a half value of the impedance of the third wiring from the impedance value of the fourth branch wiring. The signal transmission device according to any one of claims 1, 5, 9, and 15,
The first circuit block is a memory controller,
The signal transmission device, wherein the second circuit block is a memory module.

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