JP2002007308A - Memory bus system and connecting method for signal line - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an inexpensive substrate and a memory cell, for which high level impedance matching is not required by accelerating the operating speed of a memory bus. SOLUTION: The memory bus system is constituted by serially connecting a memory control element 1 and memory cells 2a, 2b and 2c through signal lines. The signal lines between the memory control element 1 and the memory cell 2a, between the memory cells 2a and 2b and between the memory cells 2b and 2c are connected by point-to-point. The signal lines, have no branch and there is no mutual crossing between the signal lines.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a memory bus system in which a memory control element and a plurality of storage elements are connected in series, and more particularly to a method for connecting signal lines between elements.

[0002]

2. Description of the Related Art Conventionally, in the design of a memory bus such as this type of SDRAM, connections between elements are usually made as shown in FIG. 7, and a plurality of storage elements are connected to a memory controller (memory control element). In such a case, the wiring form cannot be made point-to-point (hereinafter expressed as 1: 1). That is, there is always a branch point of the wiring on the signal wiring, and a change in the characteristic impedance due to the branch point causes signal reflection, and a delay time (hereinafter, referred to as a media delay) due to the wiring increases. The media delay becomes more noticeable as the operation speed of the memory is increased.
FIG. 8 shows a waveform of a signal reaching the storage element via the memory bus. Since there is a branch in the wiring, the media delay increases as indicated by A in the figure.

In FIG. 7, there are two directions, that is, a case where the data signal 5 is transmitted from the memory control element 31 to the storage elements 32a to 32c and a case where the data signal 5 is transmitted from the storage elements 32a to 32c to the memory control element 31. On the other hand, the clock signal 4 is transmitted from the memory control element 31 to the storage elements 32a-3
It is only transmitted in one direction to 2c. These two conditions limit the media delay. For example, FIG. 9 shows that one memory control element and one storage element
4 is a graph showing an allowable value of media delay when operating at MHz. The straight line and the straight line indicate the relationship between the media delay (clock delay) of the clock signal 4 and the media delay (data delay) of the data signal 5 during the write operation. It is. The straight line and the straight line indicate the relationship between the media delay of the clock signal 4 (clock delay) and the media delay of the data signal 5 during the read operation (data delay). This is an operable condition. Since the clock is common, the conditions under which this memory bus operates are a straight line,
, Are narrow areas (hatched portions).

[0004]

In order to solve the above-mentioned problems in the prior art, a RAMBUS memory shown in the block diagram of FIG. 10 has been put to practical use. This RAM
In the BUS memory, in order to avoid reflection distortion due to branching, where the storage elements are concentrated, the impedance including the branch wiring and the terminal capacitance of the storage element is matched to realize a wiring having no reflection equivalently. . However,
In order to realize this, the substrate is expensive because a high degree of characteristic impedance matching is required, and the storage element itself is also expensive in order to suppress variations in the impedance characteristics of the terminals of the storage element.

An object of the present invention is to provide an inexpensive substrate and a storage element which can increase the operation speed of a memory bus and do not require high-level impedance matching.

[0006]

According to the present invention, there is provided a method for connecting signal lines in a memory bus system, comprising the steps of: connecting a memory control element and a plurality of storage elements in series by signal lines; A signal line is connected 1: 1 between the memory control element and the first-stage storage element and between the storage element and the next-stage storage element.

The signal lines may include signal lines for address signals, data signals, address latch and data write clock signals, data read clock signals, address control signals, write request signals, and read request signals.

A memory bus system according to the present invention is a memory bus system comprising a memory control element and a plurality of storage elements connected in series by a signal line, between the memory control element and the first storage element and between the storage element and the next storage element. The signal lines between the storage elements in the stages are connected 1: 1.

The signal lines may include address signal, data signal, address latch and data write clock signals, data read clock signals, address control signals, write request signals, and read request signals.

Each storage element distributes an input signal line to processing within the element itself and transmits the signal to the next-stage storage element, and sends it out. And an addition circuit for transmitting the signal to the element.

The data signal includes a data signal which is separated into a write data signal and a read data signal.

The number of storage elements includes those within the number of address spaces of the memory control elements.

With the configuration described above, since there is no branch of the signal wiring, there is no reflection distortion or increase in delay, the operation speed of each signal can be increased, and the data transfer capability of the memory can be increased. In addition, high-level impedance matching is not required, and an inexpensive substrate and storage element are realized.

[0014]

Next, embodiments of the present invention will be described with reference to the drawings. (First Embodiment of Signal Line Connection Method) FIG. 1 is a flowchart of a first embodiment of a signal line connection method of a memory bus system according to the present invention.

In the method of connecting signal lines of the memory bus system, when a memory control element and a plurality of storage elements are connected by signal lines, as shown in FIG. A signal line is connected 1: 1 between an arbitrary storage element and the next storage element (step S
1) Each element is formed so as to be connected in series.

Here, the signal lines to be connected include address signals, data signals, address latch and data write clock signals, data read clock signals, address control signals, write request signals, and read request signals. Contains lines.

Since the signal lines between the storage elements are connected at a ratio of 1: 1, the operation speed of each signal can be increased without the occurrence of reflection distortion and delay increase due to no branching of the signal wiring. Data transfer capacity can be increased. Also, there is no need for advanced impedance matching. (First Embodiment of Memory Bus System) FIG. 2 is a block diagram of a first embodiment of the memory bus system of the present invention, and FIG. 3 is an internal block diagram of the storage elements 2a to 2c of FIG. FIG. 4 shows a wiring diagram of the memory bus system of FIG.

The memory bus system according to the first embodiment comprises:
1. A memory bus system to which the signal line connection method of FIG. 1 is applied. As shown in FIG. 2, an address signal 3 and a write clock signal 4 between a memory control element 1 and a storage element 2a.
a, the read clock signal 4b, the data signal 5, and the control signals 6a to 6c are connected at a ratio of 1: 1. The signals are connected to the storage element 2b and further to the storage element 2c via the storage element 2a. Have been. The write clock signal 4a output from the memory element 2c at the farthest end from the memory control element 1 is the read clock signal 4a of the memory element 2c itself.
b.

Referring to FIG. 3, an address signal 3, a write clock signal 4a, a read clock signal 4b, a data signal 5, an address control signal 6a, a write request signal 6b, and a read request signal 6 are applied to the storage elements 2a to 2c.
c (hereinafter, 6a to 6c are referred to as control signals) through an internal buffer 7a for inputting from the outside, and a distribution circuit 11 controls a signal path used inside the storage element and a storage element 2a to 2c at the next stage. It is divided into an external buffer 7b for transmitting a signal to the memory control element 1. Control signal 6
In the address latch register 8a, the write data latch register 8b, and the read data latch register 8c, which are monitored by the signals of the control circuit 12 by a to 6c,
Address signal 3 and data signal 5 are latched by write clock signal 4a or read clock signal 4b. The latched address signal 3 and data signal 5 exchange data with the memory cell 10 according to the signal of the control circuit 12. The address control signal 6a is composed of several signals, and when transmitted to the next-stage storage elements 2a to 2c, 1
Is connected to the external buffer 7b via an addition circuit 13 for adding the data. The selection circuit 9 connected to the data signal 5 transmits a signal for transmitting data from the memory cell 10 to the memory control element 1 via the write data latch register 8c and a write data signal 5 from an external storage element.
Switching is performed by the control circuit 12.

Hereinafter, the operation of this embodiment will be described.

The write clock signal 4a is output from the memory control element 1 and received by the internal buffer 7a in the storage element 2a. The received write clock signal 4a is distributed by the distribution circuit 11 to the internal storage element 2a and the next-stage storage element 2b.
Distributed for transmission to The internal clock signal is used by the address latch register 8a and the write data latch register 8b for latching the address signal 3 and the data signal 5. The external clock signal is transmitted to the next storage element 2b via the external buffer 7b. Similarly, the write clock signal 4a transmitted from the storage element 2b to the storage element 2c and output from the storage element 2c at the farthest end is input to the terminal of the read clock signal 4b, and is distributed via the internal buffer 7a. At 11, the clock signal is divided into an internal clock signal and an external clock signal. The internal clock signal is used by the read data latch register 8c for latching the data signal 5. The external clock signal is transmitted to the storage element 2b via the external buffer 7b, and further transmitted to the storage element 2a and the memory control element 1 in the same manner.

Next, the address control signal 6a will be described. The address control signal 6a is composed of several signal lines. This number is determined by the number of storage elements. When the number of storage elements is N, the number of signals is logarithm 2 base.
(N) The above is required. In this embodiment, the storage element is 3
Therefore, n = 2. Address control signal 6a
Outputs “00” in binary from the memory control element 1. In the storage element 2a receiving this "00", this signal is sent to the address latch register 8a, and the storage element 2a
Before transmission to the “b”, the adder 13 adds “1” to “0”.
In the storage element 2b, the addition circuit 13 adds "1", sends "10" to the storage element 2c, and repeats adding "1" each time it is transmitted to the next storage element. This address control signal 6a is sent to the control circuit 12 and the address latch register 8a, and is used as a code for identifying the storage elements 2a to 2c. The address signal 3 is used to address the addresses of all the memory cells 10 of the storage elements 2a to 2c. Can be specified.

Next, the operation of the memory bus will be described.

The address signal 3 output from the memory control element 1 is input to the storage element 2a and divided by the distribution circuit 11 into an internal address signal and an external address signal. The internal address signal is sent to the control circuit 12 and the address latch register 8a. If the address sent here is in the memory cell 10, the address is latched by the address latch register 8a, and the write request signal 6b or the read request signal 6c sent to the control circuit 12 causes
It is determined whether the operation is a write operation or a read operation.

The input / output terminals of the data signal line 5 normally maintain high impedance, and the transmission direction of the data signal 5 is determined by the write request signal 6b or the read request signal 6c.

Write request signal 6 from memory control element 1
b, the signal transmission path of the data signal 5 is immediately transferred from the memory control element 1 to the storage elements 2a and 2a.
b, switching to the direction of the storage element 2c,
, A write data signal 5 is transmitted, and in the target storage element, data is transmitted from the write data latch register 8b to the memory cell 10.

When the read request signal 6c is received from the memory control element 1, the signal transmission path of the data signal 5 is immediately transferred from the storage element 2c to the storage element 2b and the storage element 2c.
a, the direction is switched to the memory control element 1, and the read data 5 is transmitted from the memory cell 10 to the memory control element 1 through the read data latch register 8c in the target storage element.

In the memory bus system according to the present embodiment, since there is no branch of the signal wiring, the operation speed of each signal can be increased without reflection distortion and delay increase, and the data transfer capability of the memory can be increased. In addition, there is no need for advanced impedance matching, and furthermore, as shown in the wiring diagram of FIG. In addition, since wiring can be performed so that there is no intersection between signal lines, a low-layer and inexpensive substrate can be realized. (Second Embodiment of Memory Bus System) FIG. 5 shows a block diagram of a second embodiment of the memory bus system of the present invention, and FIG. 6 shows an internal block diagram of the storage elements 22a to 22c of FIG. .

In this embodiment, in the memory bus system of FIGS. 2 and 4, the data signal 5 is separated into a write data signal 5a and a read data signal 5b. Since the data signal is separated into the write signal 5a and the read signal 5b, the switching time between write and read can be reduced, and a further high-speed memory bus system can be constructed. (Other Embodiments of Memory Bus System) In the memory bus systems of the first and second embodiments, three storage elements are used, but the number of storage elements is the address space of the memory control element 1. It is possible to connect storage elements up to minutes.

[0030]

As described above, according to the present invention, since the signal lines between the elements are connected at a ratio of 1: 1, there is no reflection distortion or increase in delay due to the branching of the signal lines. It is possible to increase the element capability to the limit, that is, to increase the data transfer capability, and also to eliminate the need for advanced impedance matching and to perform wiring without intersection of each signal line. There is an effect that an inexpensive substrate can be realized.

[Brief description of the drawings]

FIG. 1 is a flowchart of a first embodiment of a method for connecting signal lines of a memory bus system according to the present invention.

FIG. 2 is a block diagram of a first embodiment of the memory bus system of the present invention.

FIG. 3 is an internal block diagram of storage elements 2a to 2c in FIG. 2;

FIG. 4 is a wiring diagram of the memory bus system of FIG. 2;

FIG. 5 is a block diagram of a second embodiment of the memory bus system of the present invention.

FIG. 6 is an internal block diagram of storage elements 12a to 12c in FIG.

FIG. 7 is a block diagram of a first conventional example of a memory bus system.

FIG. 8 is a waveform diagram of a signal reaching a storage element via a memory bus.

FIG. 9 is a graph showing an example of an allowable value of a media delay when a memory control element and a storage element are operated at 100 MHz.

FIG. 10 is a block diagram of a second conventional example of a memory bus system.

[Explanation of symbols]

1, 21 memory control element 2a, 22a storage element 2b, 22b storage element 2c, 22c storage element 3 address signal 4 clock signal 4a address signal and write data signal clock signal 4b read data signal clock signal 5 data signal 5a write Data signal 5b Read data signal 6a Address addition control signal 6b Write request signal 6c Read request signal 7a Internal buffer 7b External buffer 8a Address signal latch register 8b Write data signal latch register 8c Read data signal latch register 9 Select circuit 10 Memory Cell 11 Distribution circuit 12 Memory control circuit 13 Addition circuit 14 Clock source 15 Termination circuit A Media delay increase

Claims (7)

[Claims] 1. A method of connecting a signal line of a memory bus system in which a memory control element and a plurality of storage elements are connected in series by a signal line, the method comprising: connecting between a memory control element and a first storage element and between a storage element and a next storage element; A method for connecting signal lines of a memory bus system, wherein signal lines between storage elements are connected point-to-point. 2. The signal line includes an address signal, a data signal,
2. The method of connecting a signal line of a memory bus system according to claim 1, including a signal line for an address latch and a data write clock signal, a data read clock signal, an address control signal, a write request signal, and a read request signal. 3. A memory bus system in which a memory control element and a plurality of storage elements are connected in series by a signal line, between the memory control element and a first storage element and between a storage element and a next storage element. A memory bus system, wherein the signal lines are connected in a point-to-point manner. 4. The signal line includes an address signal, a data signal,
4. The memory bus system according to claim 3, further comprising signal lines for an address latch and a data write clock signal, a data read clock signal, an address control signal, a write request signal, and a read request signal. 5. A distribution circuit for distributing and transmitting an input signal line to processing inside the element and transmission to a next-stage storage element, and a distribution circuit for adding 1 to an input address control signal, and 5. The memory bus system according to claim 4, further comprising an addition circuit for transmitting the data to the stage storage element. 6. The memory bus system according to claim 4, wherein the data signal is separated into a write data signal and a read data signal. 7. The memory bus system according to claim 3, wherein the number of storage elements is within the number corresponding to the address space of the memory control element.