JPH08335871A - Semiconductor device - Google Patents

Abstract

PURPOSE: To facilitate the impedance adjustment by reducing the number of elements required for impedance matching in a high-speed interface. CONSTITUTION: In a semiconductor device 6, a variable impedance 7 is provided between a power supply terminal 37 and an input/output signal line 4 (in parallel with the input/output signal line 4) or in the input/output signal line 4 (in series to the input/output signal line). The variable impedance 7 consists of plural impedance elements 29 to 31 connected in parallel and switching transistors TRs (switching means) 32 to 34 for switching between validation and invalidation of impedance elements 29 to 31. The output signal of a register (first selection circuit) 35 which receives an external input signal 36 is applied to gates of switching TRs 32 to 34 to select the impedance value of the variable impedance 7. Thus, the number of elements such as fixed resistors required on the outside of the semiconductor device 6 is reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of an interface section of a semiconductor device connected to an input / output signal line.

[0002]

2. Description of the Related Art Under recent circumstances, where the demand for higher speed semiconductor devices is increasing, the speed of devices inside semiconductor devices is increasing and the structure of interfaces outside semiconductor devices is being increased. Also,
Various proposals have been made to speed up the operation of semiconductor devices.

FIG. 6 is a block diagram showing the basic configuration of the entire system that has been conventionally proposed. As shown in the figure, the external input / output signal line 1 can be regarded as an aggregate of a large number of characteristic impedances Z0, Z1, ..., Zn. Then, the termination potential Vtt is applied from the two power supply terminals 3 via the resistor 2 for matching the characteristic impedance of the external input / output signal line 1. External input / output signal line 1
When a semiconductor device (SIMM) is connected to the above to configure a system, each semiconductor device 6 is connected to a branch wiring (stub) 4 of the external input / output signal line 1. In that case, fixed resistors 5 are loaded in series or in parallel on these branch wirings 4 in order to avoid impedance mismatch.

[0004]

By the way, when a system is constructed using semiconductor devices, the load characteristics of the interface seen from each semiconductor device are the operating frequency, the characteristic impedance of input / output signal lines on the system, and the branching. It varies depending on the difference in various factors such as the length of wiring used for wiring.

However, in the above-mentioned conventional technique, impedance matching on these interfaces is performed by a fixed resistor attached to an input / output signal line outside the semiconductor device. Under these conditions, it is difficult to adopt a configuration in which the impedance is changed and matched according to the usage conditions, and when the usage conditions or the system configuration changes, the impedance mismatched state is used. Further, when the speed of each semiconductor device is increased, the operating frequency becomes higher, and the upper limit of the change range is further expanded, and this problem becomes more serious.

Although various configurations have been proposed for these input / output interfaces, there are differences in the input / output levels of the system, the signal line, and the semiconductor device. It is necessary to make different designs individually. In that case, if there is a difference in the input / output level of the interface, there is also a problem in that the value of the fixed resistance element of the input / output signal line must be changed.

The present invention has been made in view of the above problems, and an object thereof is to arrange a variable impedance for changing the impedance value of an input / output signal line inside a semiconductor device, thereby providing the entire system. Another object of the present invention is to provide a semiconductor device capable of matching impedance without increasing the occupied area of the semiconductor device.

[0008]

To achieve the above object, the basic solution provided by the present invention is to arrange a matching load, which is conventionally arranged outside a semiconductor device, inside each semiconductor device. In addition, the matching load can be changed after the system is configured.

Specifically, the means taken by the invention of claim 1 is as follows.
In a semiconductor device connected to an external device via an input / output signal line having a predetermined impedance, a variable impedance connected in series or in parallel to the input / output signal line and having a variable impedance value, and the variable impedance And an impedance changing means for changing the impedance value of 1.

The means taken by the invention of claim 2 is as follows:
In the above, the variable impedance is connected in series to an impedance element connected in parallel with each other, and at least one impedance element of the impedance elements is connected in series to determine whether the at least one impedance element is electrically valid or invalid. And a switching means for individually switching.

The means taken by the invention of claim 3 is as follows:
In the above, the switching means is a switching transistor that is switched on / off in response to a signal to the gate, and the impedance changing means receives the first control signal to control on / off of each switching transistor. Is a first selection circuit for selecting the impedance value of the variable impedance.

The means taken by the invention of claim 4 is as follows.
In the above, the semiconductor device is a synchronous DRAM, and the first control signal is the synchronous DRAM.
And a mode set signal which is inputted into the semiconductor device through one of the address input signal line and the existing input signal line. , Synchronous DRAM
It is configured by the mode register circuit of the memory section.

The means taken by the invention of claim 5 is as follows:
In the above, the variable impedance is constituted by a single transistor having a switch characteristic.

The means taken by the invention of claim 6 is as follows:
In the above, the switching means is a fuse, and the impedance changing means is configured to give a signal for cutting the fuse.

The means taken by the invention of claim 7 is claim 3
Or 4, a signal detection circuit for detecting a signal on the input / output signal line and a signal on the input / output signal line and a reference signal are input to the impedance changing means, and the phases of both signals are compared to obtain a phase difference signal. And a phase comparison circuit for generating a signal, and the first selection circuit is connected to the phase comparison circuit and configured to control the switching state of each switching means according to the phase difference signal.

The means taken by the invention of claim 8 is claim 7
In the setting, the minimum value of the impedance value that the variable impedance can take is set as an initial value, and the impedance value is increased by the minimum unit that can be changed in order from the initial value of the impedance value according to the phase difference signal from the phase comparison circuit. Setting signal output means for outputting a signal is further provided, and the impedance is raised to perform self-alignment until the phase difference between the signal on the input / output signal line and the reference signal is almost not detected by the phase comparison circuit. It is configured to take.

The measure taken by the invention of claim 9 is as follows.
Alternatively, in 8, the signal detection circuit is configured by an input buffer including a differential amplifier interposed between the input / output signal line and the phase comparison circuit.

In a semiconductor device connected to an external device via an input / output signal line having a predetermined impedance, output means connected in series to each other on the input / output signal line. A plurality of output transistors each having a plurality of output transistors, and a second selection circuit that receives a second control signal from the outside of the semiconductor device and controls activation / deactivation of each of the output transistors. Is configured to variably control the current driving capability of the output transistor.

According to a tenth aspect of the present invention, the means according to the tenth aspect further comprises a transfer gate provided between the gate of at least one output transistor among the plurality of output transistors and an input signal line. By connecting the output signal of the second selection circuit to the transfer gate, the connection of the output transistor to the input signal is controlled by the second selection circuit.

According to a twelfth aspect of the present invention, there is provided means according to any one of the first, second, third, and fourth aspects, in which a plurality of output transistors having output terminals connected in series with each other on the input / output signal line and a semiconductor device are provided. A second selection circuit that receives a second control signal from the outside and controls the operation / non-operation of each of the output transistors is further provided, and the current drive capability of the entire output transistor is increased by the second selection circuit. It is configured to variably control.

According to a thirteenth aspect of the present invention, the transfer gate provided in the twelfth aspect is further provided between the gate of at least one output transistor of the plurality of output transistors and the input signal line. By connecting the output signal of the second selection circuit to the transfer gate, the connection of the output transistor to the input signal is controlled by the second selection circuit.

[0022]

According to the invention of claim 1, the variable impedance connected to the input / output signal line is provided inside the semiconductor device, and the impedance value of the variable impedance is changed by the impedance changing means. Therefore, by making the impedance value of the variable impedance changeable within the range estimated from the usage condition range of the semiconductor device, different loads can be designed or product types can be prepared depending on the interface and system configuration. It becomes easy to obtain impedance matching without it. That is, it is possible to make the configuration of the semiconductor device common by adapting to the transmission line that constitutes the input / output signal line. Further, it becomes possible to reduce the load when configuring the system.

According to the second aspect of the invention, the impedance element is switched between valid and invalid for the impedance value of the entire variable impedance by the switching action of the switching means. Therefore, it becomes very easy to select the impedance value of the variable impedance.

According to the invention of claim 3, the ON / OFF of the switching transistor is switched according to the output signal of the first selection circuit and the impedance value of the variable impedance is selected, so that the system inside the semiconductor device is configured. After that, it becomes easy to adjust the impedance value in consideration of the operating frequency of the interface used and the characteristic impedance.

According to the invention of claim 4, synchronous DR
The impedance value of the variable impedance is selected by using the mode set signal input from the existing signal line of AM and the mode register. That is, it is possible to configure an interface that does not include a set signal except when the mode of each of the existing semiconductor devices is basically required, and that does not increase the number of input / output terminals of the semiconductor device. Therefore, it is possible to maintain high speed and to easily and easily form a small area.

According to the invention of claim 5, impedance matching can be achieved by utilizing the switch characteristic of a single transistor. Therefore, by simplifying the configuration, the area occupied by the semiconductor device is greatly reduced. be able to.

According to the sixth aspect of the invention, after the system is constructed, the fuse is cut off by the impedance changing means according to the impedance value, and the impedance value of the variable impedance is selected and fixed. Therefore, impedance matching can be achieved easily and stably.

According to the seventh, eighth or ninth aspect of the present invention, the matching is maintained with respect to the transmission / reception of the input / output signals when the power of the system is turned on, and at least the signal propagation speed is delayed by the mismatch of the characteristic impedance between the interface and the semiconductor device. It is possible for the semiconductor device itself to select a unique load.

According to the tenth or eleventh aspect of the present invention, it is possible to respond to changes in the input / output potential level of the interface each time, and the types of these input / output interfaces can be made variable between the semiconductor devices after the power is turned on. It becomes possible. Further, it becomes possible to eliminate the impedance loaded in series on the input / output signal line.

According to the twelfth or thirteenth aspect of the invention, in addition to the operation of the tenth or eleventh aspect of the invention, impedance matching can be achieved without increasing the occupied area of the entire system.

[0031]

Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1) FIG. 1a shows an external input / output signal line in the case of configuring the entire system according to the embodiment 1, an input / output circuit of a memory module branched from the external input / output signal line, and It is a figure which shows the structure of the variable impedance concerned. In the configuration shown in FIG. 1a, the variable impedance 7 is connected in series to the output signal line 11 of the output transistors 9, 10 of the semiconductor device. In FIG. 1 a, the configuration of the external input / output signal line 1 is the same as the configuration described in FIG. 6 in the above-mentioned conventional example.
The same applies to each semiconductor device (SIMM) 6 connected via a branch wiring (stub) 4 which is an input / output signal line introduced into the semiconductor device. Here, as a feature of the present invention, as representatively shown only for the semiconductor device 6 at the left end portion of FIG. 1A, a variable impedance 7 is provided in the branch wiring 4 inside the semiconductor device 6.
The fixed resistor 5 as shown in FIG. 6 is not arranged outside the semiconductor device 6. And the branch wiring 4
The output terminals of the output transistors 9 and 10 which are the signal output sections of the semiconductor device 6 and the input buffer 11 which is the input signal section of the semiconductor device 6 are connected to the variable impedance 7 of the semiconductor device. Output transistor 9,
The output terminals 10 and the input buffer 11 are provided in series with each other. Further, the variable impedance 7 is configured such that its impedance value can be selected and changed under the control of an impedance control circuit 8 which is an impedance changing means.

FIG. 1b is a diagram showing only the configuration in the vicinity of the signal input / output section of the semiconductor device 6 when the variable impedance 12 is connected in parallel to the output signal line 4, and the branch wiring 4 which is the input / output signal line is shown. It is used in an interface configured to apply the potential Vtt through the power supply terminal 3 when a signal is not output or input. Then, as shown in FIG. 1B, the variable impedance 12 is configured such that its impedance value can be selected and changed under the control of the impedance control circuit 13.

Next, FIGS. 2a to 2d show an example of the configuration of the variable impedance.

FIG. 2a is a diagram showing in detail one configuration example of the variable impedance 7 in the configuration shown in FIG. 1a.
As shown in the figure, fixed impedance values Rs1, Ts
2, a plurality of impedance elements 14, 1 having Rs3
5, 16 are connected in parallel with each other. Then, each impedance element 14, 15, 16 has a switching transistor 17, which serves as switching means for individually switching between valid and invalid of each impedance element 14, 15, 16.
18 and 19 are respectively connected in series, and the output signal of the impedance control circuit 8 which is the first selection circuit is applied to the gates of the switching transistors 17, 18 and 19. That is, the impedance control circuit 8 receives an external signal which is the first selection signal and outputs a signal, and this signal causes each transistor 1
By controlling the on / off of 7, 18, and 19, the impedance elements 14, 15, and 16 are electrically switched between valid and invalid, and the impedance value as a whole is variable. There is.

FIG. 2b is a diagram showing in detail one configuration example of the variable impedance 12 in the configuration shown in FIG. 1b. Also in this case, each impedance element 20, 21,
22 in series with switching transistors 24, 2
5 and 26 are connected to the impedance control circuit 1
The output signal of 3 is applied to each switching transistor 24, 2
The impedance value of the variable impedance 12 is selected and changed by inputting it to the gates of 5, 26. 2c and 2d are respectively shown in FIG.
b, a single transistor 27, 28 having a switching characteristic is provided in place of each impedance element and the switching transistor shown in FIG. 2a, and an example in which only the transistors 27, 28 have a variable impedance characteristic is shown.

FIG. 3 shows an example in which the impedance control circuit is composed of a register 35 in the structure of the variable impedance 12 shown in FIG. 2b. That is, the output signal of the register 35 is set by the external input signal 36 which is the first control signal, and the switching transistors 32 and 3 are set.
By switching ON / OFF of 3, 34, it is configured to select an electrically effective one of the impedance elements 29, 30, 31 connected in parallel with each other.

If the external input / output signal 36 is input at the time of mode setting via the address terminal in the synchronous DRAM and the register 35 is a mode register, the synchronous DRAM may be used. In this case, since the existing pins and the existing mode set sequence in the synchronous DRAM are used, it is easy to put them into practical use, and impedance matching can be perfectly achieved according to the usage conditions, so that high-speed signal transmission is possible. Become.

In the present embodiment, the switching means for switching the electrical validity / invalidity of each impedance element is constituted by the switching transistor, but the switching means is constituted by the fuse and the specific fuse is cut off from the impedance control circuit. A signal may be applied.

In this embodiment, the switching transistors are connected in series to all the impedance elements, but the switching means such as switching transistors is connected in series to only some of the impedance elements. You may make it have a variable impedance characteristic.

(Second Embodiment) Next, a second embodiment will be described.

FIG. 4 is a diagram showing a schematic configuration of the entire system according to the second embodiment. In this embodiment, in addition to the variable impedance 48 having the same configuration as the variable impedance 7 shown in FIG. 2A, the impedance control circuit is configured by the register 43, and the output signal of the register 43 is set by the external input signal 44, and the output Transistors 39 and 4
A large number of groups of 0s are provided, the output terminals of the groups of output transistors are connected in series with each other, and the drive capability of each output transistor is controlled by the output signal of the register 43 (second selection circuit). In addition, the output signal of the register 43 is set according to the external input signal 44, and the impedance value of the variable impedance 48 is selected by this output signal, which is common to the control method shown in FIG. There is. That is, in this embodiment, the register 43 functions as the first and second selection circuits.

Here, a feature of this embodiment is that the output transistors connected to the input / output signal line include a plurality of sets of output transistors 39a and 40a, 39b and 40b ,.
The output terminals of the output transistors are arranged in series on the input / output signal line. And
The external input signal 44 of the register 43 controls the signals applied to the gates of the output transistors 39b and 40b, ..., 39x and 40x by the transfer gates 45b and 46b, ..., 45x and 46x. For example, the signals DTOUT50 and XDTOUT5 are output only when the transfer gates 45b and 46b are enabled by the output signal of the register 43.
1 is added to the gates of the output transistors 39b and 40b to change the actual drive capability of the output transistors. Reference numeral 49 is an input buffer that functions as a signal input unit of the semiconductor device.

In this embodiment, the drive capability of the output transistor that changes when the potential applied from the external power supply 41 and the reference potential Vref applied from the reference power supply terminal 53 to the input buffer 49 changes is selected and at the same time. The impedance value of the input / output signal line 4 can be selected via the variable impedance 48. That is, there is an advantage that the input / output level of the external interface can be changed and that the load impedance according to the level can be selected.

A first selection circuit for controlling on / off of each switching transistor of the variable impedance 48 and a second selection circuit for controlling on / off of the output transistor.
The selection circuit may be provided separately.

(Third Embodiment) Next, a third embodiment will be described. FIG. 5 shows a configuration in which the impedance added to the interface arranged in the signal input / output unit of the semiconductor device is self-selected inside the semiconductor device without being controlled by the outside. Variable impedance 54
2 is the same as that of the variable impedance shown in FIG. 2A, and each impedance element is switched between valid and invalid by turning on / off each switching transistor.

A feature of this embodiment is that the input buffer 56
Phase adjustment circuit 59 and register 57 arranged on the output side of
Between and, a phase comparison circuit 58 that receives the output signal of the phase adjustment circuit 59 (that is, the signal of the input / output signal line) and the reference signal 61, compares the phases of both, and outputs a phase difference signal,
A counter 60 that receives the output of the phase comparison circuit 58 and sets the output signal of the register 57 is sequentially interposed.

Also in this embodiment, the variable impedance 5
ON / OFF of each switching transistor of No. 4 is controlled by the output signal of the register 57.
The output signal of the counter circuit 60 is input to. Then, the counter circuit 60 sets the output signal of the register 57 so that the impedance value of the variable impedance 54 takes the lowest value when the power is turned on, and the value of the impedance of the variable impedance 54 according to the detection signal of the phase comparison circuit 58. A signal is output to the register 57 so that The phase adjustment circuit 59 delays so that the phase ideally matches the reference signal 61 correctly.

In this embodiment, the phase comparison circuit 58 causes
When the output signal from the input buffer 56 and the reference signal 61 are compared and the phase difference between the two signals is detected, it indicates that the impedance value of the variable impedance 54 is not appropriate.
When a phase difference occurs between both signals, the phase comparison circuit 5
A pulse signal is output from 8 to the counter 60.
On the other hand, if the impedance value of the variable impedance 54 is appropriate, no signal is output from the phase comparison circuit 58 and the output of the counter 60 becomes constant, and the impedance value in that state is selected. In this state, at least the input buffer 56 can detect the input signal from the input / output signal line, and the impedance that does not cause the delay due to the impedance mismatch is selected.

[0050]

According to the invention of claim 1, the variable impedance connected to the input / output signal line is provided inside the semiconductor device, and the impedance value of the variable impedance is changed by the impedance changing means. Many fixed elements exist in the system while eliminating impedance mismatch due to load of input / output interface outside device, frequency characteristics, operating frequency, wiring length of branch wiring, number of branches, difference in input / output potential of interface, etc. The number can be reduced.

According to the invention of claim 2, the variable impedance in claim 1 is composed of a plurality of impedance elements, and the effective / ineffective state of the impedance elements is switched by the switching action of the switching means. It is possible to facilitate selection of values.

According to the invention of claim 3, since the switching means in claim 2 is constituted by the switching transistor which can be switched on / off by the control of the first selection circuit, the system inside the semiconductor device is constituted. It becomes easy to adjust the impedance value in consideration of the operating frequency and characteristic impedance of the interface to be used later.

According to the invention of claim 4, the first selection circuit in claim 3 is composed of a mode register of a synchronous DRAM, and an impedance of variable impedance according to a mode set signal inputted from an existing signal line. Since the value is selected, it is possible to achieve impedance matching without increasing the number of pins of the current semiconductor device or the number of sequences of the set signal to be input.
It is possible to reduce the area of the semiconductor device and reduce the number of fixed elements existing in large numbers in the system.

According to the invention of claim 5, the variable impedance according to claim 1 is constituted by a single transistor having a switch characteristic, so that the area occupied by the semiconductor device can be greatly reduced by simplifying the configuration. You can

According to the invention of claim 6, since the switching means in claim 2 is composed of a fuse, the operation for impedance matching can be simplified and stabilized.

According to the invention of claim 7, 8 or 9, the phase difference between the signal of the input / output signal line and the reference signal is detected, and the impedance value of the variable impedance is adjusted according to the phase difference. Therefore, impedance matching can be automatically achieved without using an external signal.

According to the invention of claim 10 or 11, a plurality of output transistors are arranged in series on the input / output signal line,
Since the current drive capability of the entire output transistor is variably controlled, it becomes possible to respond to changes in the input / output potential level of the interface. It is possible to eliminate the impedance loaded in series to the output signal line.

According to the twelfth or thirteenth aspect of the invention, in addition to the effect of the tenth or eleventh aspect of the invention, impedance matching can be achieved without increasing the occupied area of the entire system.

[Brief description of drawings]

FIG. 1 is an electric circuit diagram schematically showing a configuration of an entire system according to a first embodiment and an electric circuit diagram showing a modified example of an input / output unit of a semiconductor device.

FIG. 2 is an electric circuit diagram showing a configuration example of a variable impedance in the first embodiment.

FIG. 3 is an electric circuit diagram showing a control system when the impedance control circuit in FIG. 2 is configured by a register.

FIG. 4 is an electric circuit diagram showing the configuration of the entire system when the drive capability of the output transistor according to the second embodiment is varied.

FIG. 5 is an electric circuit diagram showing the configuration of the input / output unit of the semiconductor device when the impedance according to the third embodiment is self-selected inside the semiconductor device.

FIG. 6 is a block diagram showing a configuration of an entire conventional system in which a fixed resistor is provided outside a semiconductor device.

[Explanation of symbols]

1 External Input / Output Signal Line 2 Resistance 3 Power Supply Terminal 4 Branch Wiring (Input / Output Signal Line) 5 Fixed Resistor 6 Semiconductor Device 7 Variable Impedance 8 Impedance Control Circuit (Impedance Changing Means) 9 Output Transistor 10 Output Transistor 11 Input Buffer 12 Variable Impedance 13 Impedance control circuit (impedance changing means) 14-16 Impedance element 17-19 Switching transistor (switching means) 20-22 Impedance element 24-26 Switching transistor (switching means) 29-31 Impedance element 32-34 Switching transistor (switching means) ) 35, 57 register (first selection circuit) 36 external input signal (first control signal) 43 register (first selection circuit, second selection circuit) 58 phase comparison circuit 6 0 counter (setting signal output means)

Claims (13)

[Claims] 1. A semiconductor device connected to an external device via an input / output signal line having a predetermined impedance, the variable impedance being connected in series or in parallel to the input / output signal line and having a variable impedance value. A semiconductor device comprising: an impedance changing unit that changes an impedance value of the variable impedance. 2. The semiconductor device according to claim 1, wherein the variable impedance is connected in series to an impedance element connected in parallel with each other and at least one of the impedance elements, and A semiconductor device comprising: switching means for individually switching between electrically valid / invalid of one impedance element. 3. The semiconductor device according to claim 2, wherein the switching means is a switching transistor which is turned on / off according to a signal to the gate, and the impedance changing means receives a first control signal. The semiconductor device is a first selection circuit that selects the impedance value of the variable impedance by controlling ON / OFF of each of the switching transistors. 4. The semiconductor device according to claim 3, wherein the semiconductor device is a synchronous DRAM, the first control signal is a mode set signal in the synchronous DRAM, and the mode set signal is The first selection circuit is configured to be inputted into the semiconductor device through either one of the address input signal line and the existing input signal line, and the first selection circuit is a mode register of a memory section of the synchronous DRAM. A semiconductor device, which is a circuit. 5. The semiconductor device according to claim 1, wherein the variable impedance is composed of a single transistor having a switch characteristic. 6. The semiconductor device according to claim 2, wherein the switching means is a fuse, and the impedance changing means is configured to give a signal for cutting off the fuse. apparatus. 7. The semiconductor device according to claim 3, wherein the impedance changing means inputs a signal detection circuit for detecting a signal on the input / output signal line, and a signal on the input / output signal line and a reference signal. And a phase comparison circuit that compares the phases of both signals to generate a phase difference signal, and the first selection circuit is connected to the phase comparison circuit,
A semiconductor device, wherein a switching state of each switching means is controlled according to the phase difference signal. 8. The semiconductor device according to claim 7, wherein a minimum value of impedance values that the variable impedance can take is set as an initial value, and the initial value of the impedance value is sequentially set according to a phase difference signal from the phase comparison circuit. Further provided is a setting signal output means for outputting a setting signal for increasing the impedance value in a minimum changeable unit, and the phase difference between the signal of the input / output signal line and the reference signal is substantially detected by the phase comparison circuit. A semiconductor device, characterized in that it is configured to increase the impedance until self-alignment is achieved until it disappears. 9. The semiconductor device according to claim 7, wherein the signal detection circuit is an input buffer including a differential amplifier provided between the input / output signal line and the phase comparison circuit. A semiconductor device characterized by: 10. A semiconductor device connected to an external device through an input / output signal line having a predetermined impedance, and a plurality of output transistors having output terminals connected in series on the input / output signal line, the semiconductor device comprising: A second selection circuit that receives a second control signal from the outside of the device and controls the operation / non-operation of each of the output transistors, and the current driving capability of the entire output transistor by the second selection circuit. Is variably controlled. 11. The semiconductor device according to claim 10, further comprising a transfer gate interposed between a gate of at least one output transistor among the plurality of output transistors and an input signal line, A semiconductor device characterized in that the connection of the output signal of the selection circuit to the transfer gate controls the connection of the output transistor to the input signal by the second selection circuit. 12. The semiconductor device according to claim 1, 2, 3 or 4, wherein a plurality of output transistors having output terminals connected in series with each other on the input / output signal line, and a second external transistor from the outside of the semiconductor device. And a second selection circuit for controlling the operation / non-operation of each of the output transistors in response to the control signal of 1., so as to variably control the current drive capability of the entire output transistor by the second selection circuit. A semiconductor device comprising: 13. The semiconductor device according to claim 12, further comprising a transfer gate interposed between a gate of at least one output transistor among the plurality of output transistors and an input signal line, A semiconductor device characterized in that the connection of the output signal of the selection circuit to the transfer gate controls the connection of the output transistor to the input signal by the second selection circuit.