JP2905337B2 - Digital control circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to integrated circuits and, more particularly, to controlling the effective size variation of devices to improve the operation of the integrated circuit.

[0002]

BACKGROUND OF THE INVENTION Variations in the performance of integrated circuits are due to the fact that their manufacturing processes are not performed with the desired accuracy. In fact, there is variability even between ICs formed from different locations on the same semiconductor wafer. Variations in these characteristics include delay characteristics, speed characteristics (frequency response), and power consumption. The IC designer must take this variation in characteristics into account when designing the IC. Therefore, it is necessary for the designer of the IC to assume the worst of the characteristics of the IC.

If the variation in the characteristics of individual ICs can be reduced, the yield will be improved. While bipolar ECL technology allows for self-control of heat dissipation within the integrated circuit, such is not possible with MOS integrated circuits due to the inherently different modes of operation. The only solution to this MOS integrated circuit is to select an integrated circuit that meets specifications after the circuit is manufactured. Problems related to frequency characteristics and power consumption within an integrated circuit are related to the specific impedance appearing at the input and output terminals of the integrated circuit.

As a signal exits an IC terminal, travels a significant distance along a signal path, and enters another IC terminal, signal reflections result from impedance mismatches along the signal path. This signal reflection is a serious problem both in digital and analog. Assuming that the signal path is a transmission line having a particular impedance, to eliminate this undesirable signal reflection, terminate at the transmitting end and / or the receiving end having an impedance having a value equal to the characteristic impedance of the transmission line.

[0005]

Therefore, in order for a high-frequency signal to be efficiently transmitted through a signal path of a considerable distance,
Integrated circuits need to have specific, well-controlled impedance values at the input and / or output. A general requirement for such termination impedance is that the impedance values be equal for both positive and negative signals. This condition is relatively relaxed when a signal of a single polarity is transmitted and received. An example of this is when the integrated circuit is digital and sends signals. The same is true for integrated circuit power. When power is distributed, the output impedance must equal the characteristic impedance of the transmission line. For optimal power transmission, even in the absence of a transmission line, the output impedance of the signal source must equal the load impedance.

[0006] Knight et al., "A Self-Terminating Low
-Voltage Swing CMOS Output Driver ", IEEE Journal of
Solid-State Circuits, Vol. 23, No. 2, pp. 457-46
4, April 1988, discloses a CMOS circuit whose output terminal generates a digital signal having a specific control output impedance. The output buffer of this device consists of a series connection of P-channel transistors having a drain connected to the drain of an N-channel transistor, the sources of which are connected to the respective power supplies. The junction where the drains of the two transistors are connected is also connected to the output terminal.
The gate of each transistor is driven by a separate predrive circuit, which alternately enables and controls each transistor. Each predrive circuit sets the gate-source voltage of each transistor to a particular level so that this transistor presents a predetermined impedance at its terminals.

This pre-drive circuit is a digital inverter connected between a constant voltage source and a variable voltage source. Each of the pre-drive circuits is also responsive to a digital input signal. The digital signal of one pre-drive circuit is a logical inversion of the digital signal of the other pre-drive circuit.

The above device has several disadvantages. Each predrive circuit requires a controllable analog voltage,
Because the level of this voltage must be maintained under changing operating conditions, the circuit that produces this voltage is difficult to design, has many elements, and is very power consuming. Noise is also a problem.

[0009]

In order to solve the above-mentioned problem, a digital control circuit according to the present invention is characterized in that the size of an integrated circuit transistor is digitally controlled. Such digital control is achieved, for example, by connecting MOS transistors in parallel. In certain applications, the digitally controlled transistor functions as a control impedance that is connected to an output terminal of the integrated circuit. Here, a plurality of transistors are enabled by a control signal, and the set of enabled transistors is responsive to an input signal input to a conventional transistor. In another application, the digitally controlled transistor functions as a control impedance at the input terminal of the integrated circuit, enabling only the transistor, so that only the control signal that determines the effective impedance is used. In another application, digital control of transistor size is employed to control effective transistor speed and power consumption. Such control is performed to reduce manufacturing variations of the integrated circuit.
Alternatively, such control is performed as part of feedback control of the operating characteristics of the entire circuit. In such feedback applications, a digital signal that controls the size of the transistor is derived from evaluating the operation of the circuit. In applications that control manufacturing variations, the digital signal that controls the size of the transistor is derived from measuring integrated circuit parameters associated with a reference element.

[0010]

1, an output terminal 10 transmits a digital signal to a transmission line 200. FIG. The functional circuit 100 is related to the output terminal 10 and has another terminal (input or output). In the figure, the functional circuit 100 is independent, and the relationship between the functional circuit 100 and other terminals is not treated.
The output drive stage of the functional circuit 100 associated with the output terminal 10 is represented by impedances 11 and 13. One end of impedance 11 is at ground potential and the other end is switch 12
To one end. The other end of the switch 12 is connected to the output terminal 10. Similarly, the impedance 13 is connected to a constant negative potential (−V) and one end of the switch 14. The other end of the switch 14 is connected to the output terminal 10.

The switch 14 is controlled by a digital input signal S _in , and the switch 12 is controlled by its logically inverted signal -S _in . When switch 14 is closed and switch 12 is open, current from transmission line 200 flows to a constant negative potential, which flows through impedance 13. When the switch 14 is open and the switch 12 is closed, a current from the ground potential flows into the transmission line 200, and this current flows through the impedance 11. Ideally, impedances 11 and 13 have equal values and correspond to the characteristic impedance of the transmission line, for example, 50 ohms.

To make the values of the impedances 11 and 13 equal or to a predetermined value, the following is performed. First, to form an impedance in a MOS integrated circuit, a turned-on MOS transistor is used. The voltage at which the transistor turns on is
A method for controlling the generated impedance value is provided, while the size of the transistor provides another control method for the formed impedance value. Although the principles of the present invention apply to other implementations of impedance, the present disclosure discloses the most general approach. Next, with current design techniques, integrated circuit MOS transistors exhibiting similar characteristics under the same environment can be manufactured. Therefore, it is not difficult to form the impedances 11 and 13 at substantially the same value or at a predetermined ratio. However, it is difficult to always produce impedances 11 and 13 having specific values. Thus, in the present invention, the values of impedances 11 and 13 are digitally controlled during operation of the circuit.

FIG. 2 is a block diagram of FIG. In the figure, a digital impedance 20 responds to S _in and a negative voltage source. Similarly, the digital impedance 30 is -S
_in (via inverter 15) and ground potential (0V). Output 23 of digital impedance 20 and 30
And 33 are input to the output terminal 10. To provide the digital control method described above, a digital impedance 20 is used.
Responds to the digital control signal bus 21, and the digital impedance 30 responds to the digital control signal bus 31.

FIG. 3 shows a detailed embodiment of the digital impedance 20. The digital impedance 30 has substantially the same configuration. This is basically a digital sized transistor. A MOS transistor 24 is arranged in parallel between the fixed negative potential terminal 22 and the output 23 of the block. In "impedance control" applications, this configuration represents a parallel connection of resistive paths. Transistor 24
The number is a design matter. Each transistor 24 is a NAN
The gate is controlled by the D gate 25. NAN
D gate 25 has two input gates. One input gate of the NAND gate 25 is an input terminal 2 of a digital size block which is a digital impedance block.
6 is connected. The remaining input terminals of the NAND gate 25 are connected to the digital control signal bus 21.

The concept of digital impedance 20 in FIG. 3 is that transistor 24 is completely turned on by a control signal, thereby placing it in a low impedance state. By placing a sufficient number of transistors 24 in a low impedance state, the effective low impedance value between terminals 22 and 23 is reduced to a desired level. This is simply the addition of conductance.

Although FIG. 3 is shown as a parallel connection of resistors, the principles of the invention may be a series connection of resistors, or a series and parallel connection of resistors. In this embodiment, transistor 24 is n-channel rather than p-channel, and NAND gate 25 is not a NAND gate,
An AND gate may be used. In another application, NAND gate 25 may be an OR, NOR, EXOR gate.

In the configuration of FIG. 3, the transistors 24 have the same size. In such a configuration, each transistor 24 enabled by the digital control signal bus 21 increases the conductance between outputs 22 and 23 by a fixed increment. This configuration can provide a linear step-like adjustment of the conductance between outputs 22 and 23. Another approach to the size of transistor 24 is to use transistors 2
That is, to make the impedance of 4 a power of 2. That is, if the first smallest transistor has a conductance X, the second transistor is the same length and is twice as wide, its conductance is 2X, the nth transistor is 2 ⁿ times wide, and the conductance is Is 2 ⁿ X.

This power-of-two approach requires fewer parallel paths than an approach employing transistors of the same size (logs for this binary approach).
K transistors versus K transistors of the same impedance value approach). However, there are timing issues when a given transistor is enabled and all previously enabled transistors must be disabled (eg, 01
In the case of switching from 111111 to 10000000).

Another approach to sizing transistors 24 is to group transistors 24 into a plurality of subsets. If two subsets are used, one subset of the transistors coarsely adjusts the overall impedance and the other subset eventually adjusts the overall impedance. Of course, more than two subsets can be used to provide an "intermediate" roughness adjustment function. In a coarse / fine tuning embodiment, for example, the overall width of the transistors in the fine tuning subset is equal to the width of a single transistor in the coarse tuning subset, with each subset including 16 transistors.

FIG. 4 shows a circuit for generating an impedance control signal. In particular, the digital impedance 20 of FIG.
Is a circuit for generating an impedance control signal 21 for the input signal. The circuit of FIG. 4 is basically a Wheatstone bridge. The impedance 41 is connected between the ground potential terminal and the balance terminal 51, the impedance 42 is connected between the negative potential terminal (-V) and the balance terminal 51, and the reference impedance 43 is the ground potential terminal and the balance terminal 5
2 and the digital impedance 44 is connected between the negative potential terminal (−V) and the balance terminal 52. The values of the impedances 41 and 42 are appropriate. However, there is a predetermined ratio between them. The digital impedance 44 is an impedance controlled to balance the Wheatstone bridge, and the reference impedance 43 has a reference impedance value. Since only the ratio of impedances 41 and 42 is important for balancing the Wheatstone bridge, these impedances can be formed on the integrated circuit.
Digital impedance 44 is a control impedance,
It is formed on an integrated circuit and tests the manufacturing quality of the integrated circuit. The reference impedance 43 is the only impedance that must be accurately formed. Of course, the impedances 41 and 42 need not be formed on an integrated circuit, but if they are formed on an integrated circuit, they must be carefully manufactured to have a known ratio and characteristics to each other. is there. A configuration that satisfies this specification is a resistor formed in a heavily doped polysilicon layer on the integrated circuit substrate.

In an actual configuration, when the ratio of the digital impedance 44 to the reference impedance 43 is not equal to the ratio of the impedance 42 to the impedance 41, a voltage difference occurs between the balance terminals 51 and 52. This voltage difference is measured by the comparator 53. The purpose of balancing the Wheatstone bridge is to reduce this voltage to zero. This object can be realized by a clock method by adding a clock signal and the output of the comparator 53 to the converter 54. This clock signal is generated from the oscillator 55.

Converter 54 generates a set of digital signals which are input to an impedance control bus of digital impedance 44. If the parallel configuration of the resistive paths of digital impedance 44 includes transistors of the same size, converter 54 is implemented with a bidirectional shift register. In this bidirectional shift register, a left shift input provides a logic level 1 and a right shift input provides a logic level 0. The output of comparator 53 determines whether the shift register should shift right or left. When the output of the comparator 53 indicates that the voltage of the balance terminal 52 is equal to or less than the voltage of the balance terminal 51, it is necessary to input zero to the shift register.

If the parallel configuration of the resistive path of digital impedance 44 comprises a transistor constructed according to the above-described binary system, converter 54 is implemented by an up / down counter, which advances with a clock signal. , Counter up / down control responds to comparator 53. When the output of the comparator 53 indicates that the voltage at the balance terminal 52 is lower than the voltage at the balance terminal 51, the count of this counter is decreased, and as a result, the up / down control counts down.
It will be a down set.

If the parallel configuration of the resistive paths of digital impedance 44 includes a subset of transistors in a coarse / fine control configuration, converter 54 becomes slightly more complex. In this case, the converter 54 performs the above binary up /
It is realized by a down counter and a plurality of sub-converters responsive to the up / down counter. This sub-converter converts a binary number into an equivalent number of ones. If there are two subsets and the subset of the small transistors is equal to the width of a single transistor of the subset of the large transistors and the total width of all 16 transistors is equal, then the first sub-converter will be the 4th of the up / down counter. And the second sub-converter is connected to the upper bits of the up / down counter.

As mentioned above, the Wheatstone bridge of FIG. 4 acts on the digital impedance 44, which only evaluates the characteristics of the integrated circuit. In particular, digital impedance 44 evaluates changes in integrated circuit characteristics from nominal values. This evaluation value is reflected on the control signal generated by the converter 54. When the digital impedance 20 is configured to be compatible with the configuration of the digital impedance 44, the control signal input to the digital impedance 44 can be directly input to the digital impedance 20. For example,
If all the parallel resistive paths in digital impedance 44 have the same impedance value, the parallel resistive paths in digital impedance 20 will also have the same impedance value, so that the control signal generated by converter 54 will be directly digital. It is input to the control signal bus 21. The resistance value of the resistive path of the digital impedance 20 does not need to be the same as the resistance value of the resistive path of the digital impedance 44. However, if they are not the same, the effective impedance of digital impedance 20 differs from the effective impedance of digital impedance 44, but the ratio of their values needs to be kept constant. In fact, digital impedance 44
And the digital impedance 20 may be different (for example, one is a binary value method and the other is an equal impedance value method). However, in such a case, the control signal of the digital impedance 20 must be appropriately converted to correspond to different systems. Such conversion is accomplished by a separate converter (not shown) inserted between converter 54 and digital control signal bus 21. The above sub-converter is such a converter.

When the differential voltage applied to the comparator 53 is minimized, the operation of the circuit of FIG.
The output of 3 regularly changes between logic level 1 and logic level 0. Although this oscillation is not a real problem, it is important to prevent this oscillation signal from reaching the control signal for digital impedance 20. The advantage of this blocking is that the signal line transmitting digital information to the digital impedance 20 does not need to be raised if the level would drop during the immediately following clock period. This saves power and prevents unwanted noise injection introduced by switching. In FIG. 4, this blocking is performed by the detector 56 and the register 57. Detector 56 is connected to comparator 53 and is configured to detect the appearance of alternating 1 and 0 (ie, some 1 and 0 pairs) sequences at the logical output of comparator 53. Upon detecting this sequence, the detector 56 generates a disable signal and inputs it to the register 57. Register 57 is connected to the output of converter 54, and each change in the output of converter 54 is reflected on the output of register 57 until the disable signal freezes the output of register 57. The output of the register 57 is determined by the comparator 53 as 1 and 0.
It will be frozen as long as it keeps outputting the sequence.

In FIG. 4, the output of the register 57 is shown in FIG.
Is a digital signal input to the digital control signal bus 21 of FIG. In practice, the register 57 rarely changes its state, so the Wheatstone bridge of FIG.
Is very low. If it is very expensive to generate the signal lines (eg, if the signal lines occupy a large portion of the substrate), the information from the bridge in FIG. 4 to the NAND gate in FIG. 3 is transferred serially. This is achieved by sending the right shift / left shift signal of converter 54 directly to the circuit of FIG. 3 (including a converter similar to converter 54).

The control signal input to the digital impedance 20 is often different from the control signal input to the digital impedance 30. This is because a transistor with a digital impedance of 20 has a back gate bias effect that a transistor with a digital impedance of 30 does not have.

FIG. 5 shows a circuit for generating a control signal 31 for the digital impedance 30. This circuit is shown in FIG.
4 is substantially the same as that of FIG.
3 in that a digital impedance 45 is used in FIG. The digital impedance 45 is the same as the digital impedance 44 of FIG.
(Via the register 57). In FIG. 5, the digital impedance 46 is controlled and adjusted.

As described above, the accuracy of the impedance driven by the digital control signal generated by the circuits of FIGS. 4 and 5 includes: a) the accuracy of the ratio between the impedances 41 and 42, and b) the reference impedance 43. Is related to the accuracy of the absolute impedance value. Since, in absolute terms, the only element that must be accurate is the reference impedance 43, all of the other elements included in FIGS. 1-5 can be formed with the functional circuit 100 in an integrated circuit board. Regarding the reference impedance 43, the reference impedance 43 is realized in a form different from the IC chip element until a technique for forming an accurate impedance value on the substrate is developed. Of course, under certain conditions, the exact resistor is formed on silicon by laser trimming, laser / electrical cutting of the link.

Only one reference impedance 43 is required for a large circuit having the same or a characteristic according to the purpose. If the same impedances are required and these impedances undergo the same changes that the digital impedances 20 receive, the control signal input to the digital impedances 20 is connected between the output terminal and the negative fixed potential. The control signal that is input to all impedances that are input to the digital impedance 30 is input to all impedances that are connected between the output terminal and the ground potential.
If there is a certain relationship between the impedance value of the digital impedance 20 and the other impedance values, a conversion circuit is inserted between the digital impedance 20 and the control terminals having different impedances. This is illustrated in FIG. 6, where the control signal generator 110
Converts the digital signal into digital control impedance 103 and digital control impedance 105 of the functional circuit 100.
And the translator 102 converts these signals and forwards them to another control impedance of the functional circuit 100 (eg, digital control impedance 104). The reference source 120 is independent of the functional circuit 100. The translator 102 is adjustable under program control, and in FIG.
09 and 111 are shown.

In FIG. 3, digital impedance 2
0 forms an impedance controlled by the input signal (terminal 26). The control signal at input terminal 26, when given the appropriate input signal, enables the impedance,
Otherwise, it is disabled. Thereby, the switch operation of FIG. 1 is performed, and a function of controlling a digital signal of the digital impedance 20 is provided. Thus, the digital impedance 20 is not a simple impedance but a control impedance signal transmission element. If the terminal is used to receive information, such switching action is not necessary for the impedance of the terminal. What is necessary is that there is a fixed input impedance of a predetermined value. This means that the NAND gate 25 of FIG.
This is achieved by replacing with an inverter responsive to one control signal. Alternatively, in certain applications where the digital impedance provides the function of an input termination impedance, this impedance may be disabled by a signal at input terminal 26.

In some cases, the signal input to the input terminal is unidirectional, that is, current always flows through the terminal, for example, in one direction from the terminal into the circuit. This current may vary between large and small values, but is unidirectional. Such a condition exists when the signal source is an emitter-connected logic device (ECL). Under such conditions, as shown in FIG.
There is no need to have two digital impedances. 1
One is enough.

In applications where power is distributed in one direction at the terminals, it is not necessary to have the same impedance in the opposite direction. For example, an integrated circuit that drives a laser diode propagates power to the diode only at logic level one. In this case, only one of the digital impedances of FIG. 2 is needed.

Although the above description has mainly dealt with the problem of controlling the value of impedance at the terminals of a circuit, it is very important to obtain an accurate impedance value in an integrated circuit. The invention has application in controlling variations in the manufacture of other elements in an integrated circuit and in accurately controlling the operating characteristics of such circuits. For example, control of characteristics when a MOS transistor is used as a transistor.

Once an integrated circuit has been designed, the design is analyzed prior to manufacture of the circuit, parts of the circuit are identified, and specific elements, ie, transistor operation, are analyzed. In general, the parameters of interest to designers are circuit speed,
Signal delay through the circuit, power consumption of the circuit. Once a critical element is identified in the circuit, the designer replaces the design with a digitally modifiable equivalent of all critical transistors (FIG. 3).
Thus, when a transistor different from an expected one is produced in manufacturing the transistor, adjustment is made in the manufacturing process with a digital equivalent. Decreasing the effective size of a transistor slows down, increases impedance, and reduces its power consumption.

The ability of the functional circuit 100 to affect critical transistors is shown in FIG. 1, where the functional circuit 100 is the same as the digital impedance 20 or the digital impedance 30 and depends on the position of the functional circuit 100. This capability is merely exemplary, since the exact placement of output terminal 101 within functional circuit 100 depends on the circuit itself and does not form part of the present invention.

The above description has been directed to controlling the effective size of a transistor to control terminal impedance or to compensate for manufacturing variations in elements within a functional circuit of an integrated circuit. It was done. This is achieved by a Wheatstone bridge having a reference impedance 43 and an IC sampling digital impedance 44. This bridge configuration produces a signal that controls the effective size of the transistor.
However, control of the digital size and the effective size of the transistor is not limited to means of variation of the integrated circuit from a reference. The effective size of the transistor is also controlled as a means for activating the function of the functional circuit itself. This is to utilize the digital size control of the transistor in conventional feedback or feedforward mode.

FIG. 8 shows a reference source 12 composed of an integrated circuit.
0 indicates a configuration in which the terminal 122 is connected to the laser diode 121. The light output of the laser diode 121 is spliced to the fiber 123 and the light detector 124 is
Is input to The electronic output of the light detector 124 is input to a peak detecting means 125, and the peak detecting means 125
Compares the received signal peak with a predetermined threshold. A circuit similar to the converter 54 of FIG. 4 generates a digital signal representing how close the received peak signal is to a desired peak signal, ie, a value specified by a predetermined threshold. This digital signal is transferred to integrated circuit 120 via path 126, where it is suitably buffered and input to digital control drive circuit 127. The digital control drive circuit 127 connects the laser diode 121 to the terminal 12
2 and affects the amount of power injected into the laser diode 121.

[0040]

As described above, according to the control circuit of the present invention, it is possible to effectively control the termination impedance of the integrated circuit by digitally controlling the size of the integrated circuit transistor.

[Brief description of the drawings]

FIG. 1 is a block diagram of an output drive circuit.

FIG. 2 is a partially enlarged block diagram of FIG. 1, showing signals connected to an output driving element.

FIG. 3 is a block diagram of the digital impedance 20 of FIG. 2;

FIG. 4 is a circuit diagram for controlling a digital impedance 20.

FIG. 5 is a circuit diagram for controlling the digital impedance 30 of FIG. 2;

FIG. 6 illustrates a state where different sets of circuit elements are controlled by digital control signals.

FIG. 7 is a diagram illustrating a state in which different control signals of different circuit elements are controlled by processor control.

FIG. 8 is a diagram illustrating a state where a digital size transistor is controlled via feedback.

[Explanation of symbols]

 Reference Signs List 10 output terminal 11 impedance 12 switch 13 impedance 14 switch 15 inverter 20 digital impedance 21 digital control signal bus 23 output 24 MOS transistor 25 NAND gate 26 input terminal 30 digital impedance 31 digital control signal bus 33 output 41 impedance 42 impedance 43 reference impedance 44 Digital impedance 45 Digital impedance 46 Digital impedance 51 Balance terminal 52 Balance terminal 53 Comparator 54 Converter 55 Oscillator 56 Detector 57 Register 100 Function circuit 102 Translator 103 Digital control impedance 104 Digital control impedance 105 Digital control impedance 06 Translator 107 translator 108 translator 109 translator 110 control signal generator 120 reference source (integrated circuit) 121 laser diode 122 terminal 123 fiber 124 optical detector 125 peak detecting means 126 pass 127 digital control driving circuit 200 transmission line

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Tadge John Gabala USA 18078 Pennsylvania near Schnexville, Penhill Drive 11 (72) Inventor Scott Carroll Nower USA 07092 New Jersey Mountainside, Summit Train 1081 (56) References JP-A-62-38616 (JP, A) JP-A-59-51303 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) H03K 19/0175 H04L 25/02

Claims (7)

(57) [Claims] A digital control module having a pair of terminals and a digital signal port for changing an electrical characteristic between the pair of terminals; a digital control module formed in the integrated circuit; and a first port of the integrated circuit. A reference source connected between the first and second ports of the integrated circuit; a digital control reference module connected between a second port and a third terminal of the integrated circuit; A first element to be connected; a second element connected between the third terminal and the balance terminal of the circuit; and a digital control reference module connected between the balance terminal and the second port. And a comparator module for generating a digital control signal to be controlled and a digital signal to be input to the digital signal port, wherein the digital control reference module Wherein the reference source is formed inside the integrated circuit and the reference source is formed outside the integrated circuit. 2. The digital control circuit according to claim 1 , wherein the reference source is an impedance element. A comparator connected between the balance terminal and the second port; a clock pulse generator; and the digital controller responsive to the comparator and the clock pulse generator. The digital control circuit according to claim 1 , further comprising: a converter that generates a digital control signal for controlling the reference module. 4. A sequence detector for detecting a predetermined signal sequence generated by the comparator in response to the comparator, and a digital signal input to the digital signal port in response to the converter and the sequence detector. 4. A register for generating a signal.
3. The digital control circuit according to claim 1. 5. A power loss characteristic changing means for changing a power loss characteristic of a power loss element in response to a digital control signal in units of a change amount of 1/4 or less of a nominal power loss of the power loss element. A power loss element formed in the integrated circuit, a digital control reference module connected between a first port and a first terminal of the integrated circuit, and a second terminal of the integrated circuit and a balance terminal. A first element connected, a second element connected between the first terminal and the balance terminal of the integrated circuit, and a second element connected between the first port and the second port of the integrated circuit; a reference source is connected between said balance terminal and said first port, the input to the power loss characteristic changing means to generate a digital control signal for controlling the digital control reference module Is composed of a comparator module for generating digital control signals, the digital control reference module is formed in the integrated circuit, a digital control circuit for the reference source is characterized by being formed outside the integrated circuit. 6. The digital control circuit according to claim 5, wherein said reference source is an impedance element. 7. A terminal impedance module formed in an integrated circuit and responsive to a digital impedance control signal to set an impedance to an impedance value determined by the digital impedance control signal , and a first terminal having a fixed potential. A first bridge impedance having a lead connected thereto and a lead connected to the first balance terminal; a lead connected to a second terminal having a fixed potential; and a lead connected to the first balance terminal. A switchable impedance module having a second bridge impedance, a lead connected to the second terminal, and a lead connected to the second balance terminal; connected between the first terminal and the second balance terminal; Reference impedance, the first balance terminal and the second balance end A comparator that measures a potential difference between the two, and generates a switchable impedance module control signal indicating the potential difference input to the switchable impedance module to control the switchable impedance module so as to minimize the potential difference; Means for generating the digital impedance control signal in response to the switchable impedance module control signal, wherein the switchable impedance module is formed within the integrated circuit and the reference impedance is formed outside the integrated circuit. A digital control circuit, characterized in that: