JP2826504B2 - Semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit (hereinafter referred to as "LSI") having a three-state input / output buffer connected to an input / output terminal, and more particularly to a signal output from the three-state input / output buffer. When the polarity of a signal supplied from the outside is different, a malfunction of an internal circuit caused by a collision of both signals at an input / output shared terminal (hereinafter, referred to as a bus fight) due to a timing shift is prevented. The present invention relates to a semiconductor integrated circuit.

[0002]

2. Description of the Related Art Along with the progress of the miniaturization technology of semiconductor devices, the functions built in LSIs have become complicated, and the exchange of signals with the outside has increased, and the types of input / output signals have also increased. Therefore, a large number of input buffers and output buffers for interfacing these signals between the internal circuit and the external circuit of the LSI, or a large number of three-state input / output buffers that share input and output terminals to suppress an increase in the number of terminals are incorporated. It was started.

Referring to FIG. 11 which shows a block diagram of an output circuit section in a conventional semiconductor integrated circuit of this kind, and FIG. 12 which shows a timing chart for explaining the operation thereof, this semiconductor integrated circuit 1 has an internal circuit. An output signal line output from 2 to the outside is connected to the input terminal of the output buffer 10 of the three-state input / output buffer 5, and its output terminal is connected to the input / output terminal 11 and the input terminal of the input buffer 9, respectively. The output terminal is connected to the internal circuit 2. Further, an input / output switching terminal 8 serving as a switching signal for the input / output buffer 5 is connected to the input / output switching signal line 12 via the internal circuit 2, and the input / output switching signal line 12 is connected to the input / output control terminal of the output buffer. It is configured.

When testing this LSI, the LSI
Tester 6 is connected to input / output terminal 11.

When the input / output buffer 5 is set to the output mode, a high-level output mode setting signal is sent from the input / output switching terminal 8 to the input / output switching signal line 12 of the input / output buffer 5 via the internal circuit 2. Output (point F).

Similarly, when switching to the input mode, a low-level output mode setting signal is output from the input / output switching terminal 8 via the internal circuit 2 to the input / output switching signal line 12 of the input / output buffer 5 (point F). Timing t2).

However, from an output mode in which the LSI tester 6 supplies a signal to the LSI under test at a predetermined level and at a timing t1, a signal output from the LSI under test at a timing t2 in response to the signal supplied from the LSI tester 6 When the input mode is switched to the input mode for comparing and measuring with a predetermined reference value (timing t3), the timing is controlled by the test pattern.

For this reason, the input / output buffer 5 switches from the input mode to the output mode or vice versa and switches from the output mode to the input mode.
The switching timing t1 of the SI tester 6 was earlier.

For example, when the output buffer 5 is set to the input mode, a signal is output from the LSI tester 6 at the timing t1, and when the input / output switching terminal 8 of the LSI 1 is set to the low level, the level at the point F changes to the low level at the timing t2. However, although the LSI tester 6 has already been switched to the signal output mode at the timing t1, the LSI
The level at the point F of the output circuit unit 5 changes to the low level with a delay until timing t2. Timing t1 during that time
From t to t2, the output buffer 10 is in the output state and outputs high-level data. However, since the low level is supplied from the LSI tester 6, bus fight occurs, and the level at the point B becomes an intermediate level. . The input buffer 9 for inputting the intermediate level has p
Channel MOS transistor and n-channel MO
The S transistors are turned on, a through current flows, and the ground potential GND of the input buffer 9 fluctuates.

Another example of the conventional output circuit section in which the above bus fight is improved is described in Japanese Patent Application Laid-Open No. 1-1175414. Referring to FIG. 13 which shows a circuit diagram of an output circuit unit described in the publication, this output buffer circuit includes:
3-state buffers 27 and 28 for outputting data signals A and B on the bus lines, respectively, and voltage-dividing resistance element 4 for maintaining the bus lines at 2 V when floating.
1 and 42, TTL input buffer 30 and CMOS
A floating detection circuit 29 comprising a buffer 31 and a coincidence circuit 32, a delay line 35 having a delay amount longer than the signal delay time of the output buffer 27, an output of the delay line 35 and a bus line. A matching circuit 36 for matching the data of
A gate 33 for generating a bus fight inhibit signal from the non-coincidence signal and the output coincidence output of the coincidence circuit 32 of the floating detection circuit 29, and an enable / disable enable signal is generated from the generated bus fight inhibit signal and the output control signal A. A gate 34 for controlling the output buffer 27, a gate 40 for similarly controlling the output buffer 28, a delay line 437 matching circuit 38 and a gate 3
9 and a gate 40.

The operation of this circuit is such that when either of the three-state output buffers 27 or 28 is in a high impedance state, the bus line is divided by two by resistance division.
Although the output voltage is V, the mismatch value is sent out by the matching circuit because the output values of the TTL buffer and the CMOS buffer are different due to different logic threshold voltages. On the other hand, when the bus line is at a high level or a low level, a coincidence signal is sent from the coincidence circuit.

Thus, the floating state of the bus line and another state are detected separately.

Still another example of a conventional output circuit section having improved bus fight is described in Japanese Patent Application Laid-Open No. 4-262440. Referring to FIG. 14, which shows a circuit diagram of an output circuit unit described in the publication, the output buffer circuit 43 includes:
This is a tri-state output buffer circuit having a normal CMOS transistor configuration. The input signal DO of this buffer is also input to the comparator 45. The comparator 45 outputs the output signal D of the output buffer 43 via the inverter 46 to the NAND4.
7 is input to the NOR 50 via the inverter 49, and the signal DO is commonly input to the other input terminals of the NAND 47 and the NOR 50, respectively. The output of the NAND 47 is input to the NOR 51 via the inverter 48, and the output of the NOR 50 is directly input to the NOR 51. The output of the NOR 51 outputs the ERR signal via the inverter 52.

The output buffer circuit 43 is controlled by an enable signal HZ from the inside. When the enable signal HZ is at a low level, the output buffer circuit 43 has the same polarity as the data signal DO from the circuit preceding the output buffer circuit. The signal D is output to the input / output terminal 53.

The comparator 45 is a circuit for comparing the levels of the two signals, that is, the data signal DO and the output signal D of the output buffer circuit.
It outputs a high-level ERR signal.

Two inverters 4 constituting the comparator 45
6, 49, one inverter is set to have a higher logic threshold level, and one inverter is set to have a lower logic threshold level, and does not respond to an intermediate level. Has become.

[0017]

A first problem with the conventional output circuit described above is that a delay occurs in the switching time of the input / output buffer from the output mode to the input mode. The signal of the next pattern was input from the tester to the input / output buffer, and bus fight occurred on the input / output line. Due to the occurrence of the bus fight, the potential on the input / output line becomes an intermediate potential state, and this signal is input to the input buffer of the input / output buffer, in which a through current flows from the power supply potential to the ground potential, and the ground potential of the buffer is reduced. There has been a test trouble that fluctuates and becomes unmeasurable during LSI measurement due to noise due to the fluctuation.

The reason is that the switching signal between the input mode and the output mode of the input / output buffer is transmitted through the internal circuit of the LSI.
This is because, at the same time as the pattern is switched from the tester to the input buffer via the input / output line directly, a bus fight of a signal corresponding to the LSI internal circuit time occurs.

The second problem is that when the output signal of the output buffer is in a floating state, the bus line to which the output signal has been output has a potential of 2 V due to resistance division. However, a TTL input buffer and a CMOS input buffer are used. Since each output value is different by making the logical threshold voltage different, the input / output buffer is temporarily controlled to the input mode by detecting each output by the matching circuit, so that the bus line is in the floating state. And the other state was adopted,
It has been impossible to accurately and instantaneously detect a potential change of the input / output line.

On the other hand, another method has a comparator for comparing the levels of two signals, that is, a data signal and an output signal of an output buffer circuit. When the two signals have different levels, a high-level ERR signal is output. Is output, one of the two inverters constituting the comparator is set to have a higher logic threshold level, and the other is set to have a lower logic threshold level. Thus, it does not respond to the intermediate level, but also in this case, it is impossible to accurately and instantaneously detect a change in the potential of the input / output line.

The reason is that since a change in the input / output potential is detected by an inverter or a buffer, a voltage of about 1.0 V or more is required as a differential voltage between a high level and a low level, and bus fight is avoided. The circuit scale becomes large. Further, it is impossible to set the logical threshold voltage with high accuracy due to manufacturing variations.

That is, referring to FIG. 15, which shows the response characteristics of the buffer circuit, the horizontal axis indicates the input voltage, and the vertical axis indicates the output voltage, and the response characteristics of the buffer change under manufacturing conditions. Curves A and B each have a variation of 0.4 V with respect to Curve B where the center value of the threshold value at which the output is inverted is 1.9 V.

An object of the present invention has been made in view of the above-mentioned drawbacks, and prevents the occurrence of a test trouble that cannot be measured at the time of an LSI test. An object of the present invention is to provide a semiconductor integrated circuit that avoids fight.

[0024]

The features of the semiconductor integrated circuit of the present invention include an input terminal, an output terminal, an input / output shared terminal, and an input / output connected to the shared terminal and controlled to switch to an input mode or an output mode. A semiconductor integrated circuit comprising: a buffer; and an input / output switching terminal configured to switch the input / output buffer to the input mode or the output mode in response to an input / output switching signal supplied from the outside. When a test signal is input to the test terminal, an intermediate potential detecting means for detecting the potential of the input / output shared terminal, and receiving the output signal of the intermediate potential detecting means, transmitting the input / output switching signal to the input / output buffer. And an input / output switching control means for outputting.

Further, the intermediate potential detecting means includes a first reference voltage generating means and a first differential comparing means having the reference voltage as one input and the other input connected to the input / output terminal. A second differential voltage generating means, a second differential voltage comparing means having one input as its reference voltage, and the other input connected to the input / output terminal, and an output of the first differential frequency comparing means. And an intermediate potential generation means for generating an intermediate potential detection signal by an exclusive OR of the signal and the output signal of the second differential comparison means.

Further, the intermediate potential generating means includes an exclusive OR circuit for inputting the output signals of the first and second differential comparing means, respectively, and outputs the output signal of the exclusive OR circuit to a predetermined signal. A delay circuit that delays by a time, and an OR circuit that takes a logic of a delay output signal of the delay circuit and an output signal of the exclusive OR circuit. This is a potential detection signal.

Further, when the potential of the input / output common terminal transitions from a high logical level to a low level, the intermediate potential generating means changes the intermediate potential during the transition period to the first and second potentials. Even if it is detected as a pulse signal by the differential comparison means and the exclusive OR circuit,
If the pulse width of this pulse signal is narrower than the delay time of the delay circuit, it is not generated as the intermediate potential detection signal, and the intermediate potential detection signal maintains the previous output state.

The intermediate potential generating means generates the intermediate potential detection signal if the pulse width of the pulse signal is wider than the delay time of the delay circuit, and outputs the intermediate potential detection signal from the input / output switching terminal according to the intermediate potential detection signal. The input / output buffer is switched to the input mode at a timing earlier than the supplied signal.

Further, the first reference voltage generating means includes:
A first impedance element having one end connected to the power supply potential and a second impedance element having one end connected to the ground potential are connected in series with each other, and the potential at the series connection point is set higher than the intermediate potential; The second reference voltage generating means includes a third impedance element having one end connected to the power supply potential and a fourth impedance element having one end connected to the ground potential, which are connected in series with each other. It is set lower than the intermediate potential.

Further, the first, second, third and fourth impedance elements are each a resistance element, and the resistance value of the second impedance element is higher than that of the first impedance element. The third impedance element is set to be larger, and the third and fourth impedance elements are also resistance elements, and the resistance value of the third impedance element is set larger than that of the fourth impedance element.

Further, the first impedance element is a first p-channel MOS transistor, and the second impedance element is
Is a first resistance element, the third impedance element is a second resistance element, the fourth impedance element is a first n-channel MOS transistor, and the first p-channel The ON resistance value of the type MOS transistor is smaller than the resistance value of the first resistance element, and the resistance value of the second resistance element is the first n.
It is set to be larger than the on-resistance value of the channel type MOS transistor.

Further, a second p-channel MOS transistor is inserted in series between the first impedance element and the power supply potential, and a second n-channel MOS transistor is inserted between the second impedance element and ground potential. Are inserted in series, a third p-channel MOS transistor is inserted in series between the third impedance element and the power supply potential, and a third n-channel MOS transistor is inserted between the fourth impedance element and ground potential. MO
An S transistor is inserted in series connection, and the test signal is supplied to the gate electrodes of the second and third p-channel MOS transistors by the second and third n-type MOS transistors.
An inverted signal of the test signal is input to the gate electrode of the channel type MOS transistor.

[0033]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In an integrated circuit according to the present invention, when an input / output buffer is switched from an output mode to an input mode and a bus fight occurs, an input / output terminal has an intermediate potential and a signal is input to an intermediate potential detecting section. Outputs a detection signal.
A signal output by the intermediate potential detection unit and passed through the control unit can be transmitted to the input / output line at a higher speed than a signal input from the input / output buffer switching terminal via the LSI internal circuit.

First, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. Referring to FIG. 1, a semiconductor integrated circuit 1 of the present invention has a data output G output from an internal circuit 2 input to an output buffer 10 and an input / output that outputs the output to an input buffer 9 and an input / output shared terminal 11. Buffer 5,
An intermediate potential detecting section 4 for inputting a signal input / output to the input / output common terminal 11 and detecting a state of the intermediate potential, a signal E detected by the intermediate potential detecting section 4 and an input from the input / output switching terminal 8 for internal Input / output switching signal C output via circuit 2
And a control unit 3 that outputs an input / output switching signal F to the output buffer 10 in response to a test signal input from the test terminal 7. During test, L is directly connected to input / output terminal 11.
The SI tester 6 is connected.

The output circuit section 1 detects the state of the intermediate potential outputted on the input / output common terminal 11 of the input / output buffer 5 by the intermediate potential detecting section 4, and the control section 3 detects the state of the intermediate potential from the input / output switching terminal 8. The signal and the signal from the intermediate potential detection unit 4 are compared, and the faster signal is selected and output to the input / output switching line 12.

The output buffer 10 is activated when the input / output switching signal F output on the input / output switching line 12 is at a high level, and the data G input from the internal circuit 2 is output.
Is output to the input / output terminal 11.

Referring to FIG. 2 which shows a block diagram of the intermediate potential detecting section 4, the intermediate potential detecting section 4 has an input / output common terminal 11 which is connected to a first differential comparison circuit section 15 and a second differential comparison section. The reference voltage input terminal of the first differential comparison circuit unit 15 connected to the comparison voltage input terminal of the circuit unit 16 is connected to the first reference voltage generation unit 13 and the second differential comparison circuit unit 16
Is connected to the second reference voltage generator 14. The output terminals of the first and second operation comparison circuit sections 15 and 16 are connected to the input terminal of EX-NOR 19, respectively, and the output terminal of EX-NOR 19 is a delay circuit comprising one input terminal of OR 20 and delay element 22a. 21 are connected to the other input terminal of the OR 20 via
The output of R20 is configured to be the output signal of the control unit.

Referring to FIG. 3 showing a circuit diagram of the differential comparison section and the reference voltage generation section, reference voltage generation section 13 includes resistance elements 131 and 132 between a power supply potential and a ground potential.
Are connected in series, and this series connection point is used as an output terminal of the reference voltage. The voltage determined by the voltage dividing ratio of the resistance elements 131 and 132 is set so that a higher voltage such as 3.8 V is obtained. Is set.

Similarly, reference voltage generating section 14 is configured such that resistance elements 141 and 142 are connected in series between a power supply potential and a ground potential, and this series connection point is used as an output terminal of a second reference voltage. The respective resistance values are set so that a voltage determined by the voltage division ratio of 141 and 142 can obtain a lower voltage such as 0.6 V, for example. The range of these reference voltages is the range of the intermediate potential.

In these reference voltage generators 13 and 14, resistance elements 131 and 132 may be formed by P-channel MOS transistors and n-channel MOS transistors. Referring to FIGS. 4A and 4B showing modified examples, reference voltage generating section 13 includes a p-channel MOS transistor 13 between a power supply potential and a ground potential.
3 and the resistance element 132 are connected in series, a gate electrode is also connected to the drain electrode of the p-channel MOS transistor 133 at this connection point, and the drain electrode serves as a reference voltage. The reference voltage generator 14 has the same configuration, and the components 133 and 141 and 132 and 1
43 correspond to each other.

Referring to FIG. 5 in which these reference voltage generators 13 and 14 are further modified, a p-channel MOS transistor and a resistor 1 are connected between a power supply potential and a ground potential.
A first reference voltage generator in which the first reference voltage generator 31, the resistance element 132, and the n-channel MOS transistor 134 are connected in series;
A second reference voltage generator in which a p-channel MOS transistor 143, a resistor 141, a resistor 142, and an n-channel MOS transistor 144 are connected in series between a power supply potential and a ground potential; a resistor 131 and a resistor 1
The first reference voltage is taken out from the connection point with the resistance element 32, and the second reference voltage is taken out from the connection point between the resistance element 141 and the resistance element 142. p-channel type MO
Test signals input from the external terminal 7 are directly input to the gate electrodes of the S transistors 133 and 143, and input to the gate electrodes of the n-channel MOS transistors 134 and 144 via the inverter 23, respectively. .

Referring again to FIG. 3, the differential comparison circuit 1
5, a p-channel MOS transistor 151 and an n-channel MOS transistor 152 are connected in series between the power supply potential and the other electrode of the n-channel MOS transistor 153 having one electrode connected to the ground potential; The p-channel MOS transistor 1 is placed between the other electrode of the channel-type MOS transistor 153 and the power supply potential.
54 and the n-channel MOS transistor 155 are connected in series, and the gate electrode of the p-channel MOS transistor 151, the gate electrode and the drain electrode of the p-channel MOS transistor 154, and the gate electrode of the n-channel MOS transistor 153 are connected in common. And
The gate electrode of n-channel MOS transistor 155 is connected to the first reference potential, the gate electrode of n-channel MOS transistor 152 is connected to input / output terminal 11, and n-channel MOS transistor 15
2 is a p-channel MOS transistor 1
56 and an input of an inverter composed of an n-channel type MOS transistor 157, and its output is
It is configured to output to the EX-NOR 19 from the other input terminal.

The differential comparison circuit section 16 includes a p-channel MOS transistor 16 having one electrode connected to the power supply potential.
P-channel MOS between the other electrode 1 and the ground potential
Transistor 162 and n-channel MOS transistor 163 are connected in series, and p-channel MOS transistor 164 and n-channel MOS transistor 165 are connected in series between the other electrode of p-channel MOS transistor 161 and ground potential; The gate electrode of the n-channel MOS transistor 163, the gate electrode and the drain electrode of the n-channel MOS transistor 165, and the gate electrode of the p-channel MOS transistor 161 are commonly connected. 2, the gate electrode of p-channel MOS transistor 162 is connected to input / output terminal 11, and the drain electrode of p-channel MOS transistor 162 is connected to p-channel MOS transistor 162. Is connected to an input of an inverter consisting of Njisuta 166 and the n-channel MOS transistor 167, EX its output from one input terminal of the controller 3
-Is configured to be output to NOR19.

That is, in the intermediate potential detecting section 4 having the above-described configuration, when the signal waveform at the input / output terminal 11 has a gentle slope waveform, the intermediate potential output section 4 operates and the delay circuit 22 makes the intermediate potential unstable. The detection signal is removed, and the detection signal is delayed in order to prevent switching of the input / output buffer 5 at an early stage.

Referring to FIG. 3, differential comparison circuit sections 15 and 16 and reference voltage generation sections 13 and 14 will be described. The first differential comparison circuit section 15 and the second differential comparison circuit section 16 of the intermediate potential detection section 4 are constituted by differential amplifiers, and the first and second reference voltage generation sections 13 and 14
Is a circuit for generating an arbitrary reference voltage according to the resistance value ratio. The resistance element 131 is set at a lower resistance value than the resistance element 132, so that the intermediate element has a high potential in the range of the intermediate potential, that is, the upper limit value. The element 142 is set to have a lower resistance value than the resistance element 141, and thus has a lower potential in the range of the intermediate potential, that is, a lower limit value.

In the modified sequence shown in FIG. 4, the on-resistance value of p-channel MOS transistor 133 of first reference voltage generating section 13 is smaller than resistance element 132 and is smaller than that of second reference voltage generating circuit 14. The ON resistance value of the n-channel MOS transistor 26 is configured to be smaller than the resistance value of the resistance element 141. With this setting, matching between the reference voltage and the output transistor of the input / output buffer can be achieved, and a more accurate reference voltage can be generated.

The modification of the reference voltage generator shown in FIG. 5 is a circuit in which the reference voltage generator is activated only at the time of a test, so that power consumption can be reduced.

That is, in the test state, a low-level test signal is supplied from the test terminal 7, so that the p-channel MOS transistors 133 and 143 conduct, and the test signal is inverted by the inverter 23 to be at a high level. The n-channel MOS transistors 134 and 144 are also turned on to generate reference voltages.

On the other hand, during normal operation, the test terminal 7
Supplies a high-level test signal, the p-channel MOS transistors 133 and 143 are turned off, and the test signal is inverted by the inverter 23 to a low level, so that the n-channel MOS transistors 134 and 144 are also turned off. In this state, the current from the power supply potential to the ground potential is cut off.

Referring to FIG. 6 showing a circuit diagram of the control unit 3, the control unit 3 connects each output terminal of the NANDs 241 and 242 to one of the other input terminals, and
The other input terminal of the AND 241 is connected to an input / output switching signal line from the internal circuit 2, and the other input terminal of the NAND 242 is connected to the output line of the intermediate potential detecting unit 4.

The output terminal of the NAND 241 is connected to one input terminal of the OR 25, and the test terminal 7 is connected to the other input terminal. An output terminal of the OR 25 is connected to one input terminal of the AND 26, and an input / output switching signal line from the internal circuit 2 is connected to the other input terminal. The output terminal of the AND 26 becomes the output terminal of the control unit, and is configured to be connected to the control terminal of the output buffer 10 of the input / output buffer 5.

The operation of the semiconductor integrated circuit having the above configuration will be described. First, in order to determine the resistance values of the reference voltage generators 13 and 14, the reference voltage setting load line shown in FIG. 7A is connected to the p-channel MOS transistor on the power supply potential side shown in FIG. And FIG. 7 (c)
The load lines when an n-channel MOS transistor is connected to the ground potential side shown in FIG.

Referring to FIG. 7A, the horizontal axis indicates the power supply voltage of 5 V, and the vertical axis indicates the current value of 100 mA. In the case of a 50Ω load straight line, ImA = (5V / 50) = 100mA, and in the case of a 75Ω load straight line p of a p-channel MOS transistor, ImA = (5V / 70) = 66mA, and a 75Ω load straight line. In the case of p, ImA = (5V
/ 75) = − 66 mA, and for a 75Ω load straight line p of an n-channel MOS transistor, ImA = (5V
/ 75) = 66 mA.

Assuming that the on-resistance of the n-channel MOS transistor has a minimum value of 15Ω, a central value of 20Ω, and a maximum value of 26Ω with respect to these load lines, the minimum value is 0.85V and the maximum value is Is obtained as 1.7V. Similarly, assuming that the ON resistance of the p-channel MOS transistor has a minimum value of 30Ω, a center value of 40Ω, and a maximum value of 52Ω, the operating point is obtained as a minimum value of 2.4V and a maximum value of 3V.

These operating voltages are from 0.85V to 1.7V.
And the range from 2.4 V to 3.0 V indicate the bus fight range between the high-level input voltage minimum value VIH of the input buffer and the low-level output voltage maximum value VOL of the output buffer, respectively. The range is the maximum value of the low-level input voltage VIL of the input buffer.
And a bus fight range between the output buffer and the high-level output voltage minimum value VOH of the output buffer.

For example, since the currents flowing through the transistor pairs of the differential comparison circuit 15 are equal,
A reference voltage at which the voltage at one of the two input terminals for inputting the output signal of the output buffer is equal to the voltage at the other input terminal for inputting the reference voltage is applied when the ON resistance of the p-channel MOS transistor is a minimum value of 30Ω. Is set to 3.8 V, which is higher than the operating voltage 3V, and 0.6 V, which is lower than the operating voltage 0.85 V when the on-resistance of the n-channel MOS transistor has the minimum value of 15Ω.

Of these reference voltages, reference voltage generator 1
3 is a voltage dividing resistance element 131 and 1
Calculating the resistance value of 32 gives about 31 KΩ and 100 KΩ. Similarly, the reference voltage generator 14 outputs the reference voltage 0.6.
When the resistance values of the voltage-dividing resistance elements 141 and 142 are determined to be V, about 100 KΩ and 14 KΩ are obtained.

As described above, the maximum value of the on-resistance of the MOS transistor is set to 52Ω for the p-channel MOS transistor and 26 for the n-channel MOS transistor.
Assuming Ω, the through current of the input / output buffer is about 60 mA per input / output buffer. The rise of the ground potential due to the influence is about 60 mV.

Therefore, the reference voltage of the first differential comparison circuit section 15 is set to 3.8 V, and the reference voltage value of the second differential comparison circuit section 16 is set to the intermediate voltage within the range of 0.6 V.

8 and 9, which show timing charts for explaining the operation together with FIGS. 1 to 7, FIG. 8 shows the LSI tester input / output mode signal at point A in FIG. I), the output mode is indicated by (O), the signal at the input / output terminal 11 at point B in FIG. 1, the input / output switching signal from the internal circuit at point C in FIG.
1 shows an intermediate potential detection unit signal at point, an output correction signal of the intermediate potential detection unit at point E in FIG. 1, and an output signal of the control unit at point F in FIG.

When the input / output mode of the LSI tester changes from the input mode (I) of the input / output buffer 5 to the output mode (O), the input / output switching signal F from the internal circuit 8 goes high due to an internal delay. Is delayed, the output buffer 10 keeps the signal output shut off, and the input / output terminal 11 is in a floating state (Float).

When the delay time has elapsed, the input / output switching signal F changes to the high level, so that the signal from the input / output terminal 11 at the point B immediately outputs the high level output of the internal circuit 2 to the input / output terminal 11. At this time, the differential comparison circuit unit 15
Output of the differential comparison circuit section 16 detects the intermediate level and outputs a high level, so that the exclusive OR signal of the EX-NOR 19 at the point D is low level. The signal at the point E becomes low level only during a period delayed by the OR of the signal and the signal OR20 delayed by the delay circuit 22 for a predetermined time. However, since the input / output switching signal at the point C is still at the low level, the flip-flop 31 of the control unit 3 does not accept the low level at the point E, and the output signal line 12 of the control unit 3 remains at the low level (the potential at the point F). ).

When the input / output switching signal at point C goes high after the elapse of the floating time, the output buffer 10 enters the output mode and outputs a high level. In response to this high level, the output buffer 10 of the differential comparison circuit 15 Since the output detects the high level and outputs the high level, and the differential comparison circuit section 16 also outputs the high level, the exclusive OR signal of the EX-NOR 19 at the point D outputs the high level. OR of the signal and the signal delayed for a predetermined time by the delay circuit 22
The signal at point E changes from low level to high level by the logical sum of 20.

The reset of the flip-flop 31 of the control unit 3 is released by this high level, and the input / output switching signal at the point C is also at the high level.
Outputs a high level, the output buffer 10 enters an output mode, and outputs a high level to the input / output shared terminal 11.

At time t2, the LSI remains in the output mode and a low-level signal is supplied from the LSI to the input / output terminal 11. However, since the driving capability is much smaller than the driving capability of the LSI tester, the output is low. The signal transitions to a low level to some extent. Since this transition period is at the intermediate level, the output of the differential comparison circuit section 15 detects the intermediate level again and outputs a low level, and the output of the differential comparison circuit section 16 detects the intermediate level and outputs a high level. Therefore, the exclusive OR signal of the EX-NOR 19 at the point D outputs a low-level pulse signal. However, if the period of the pulse signal which becomes low level at the intermediate level is shorter than the delay time of the delay circuit 22, this pulse signal does not appear in the OR output (OR20) and the high level which is a normal output signal is displayed. Will last.

At timing t3, the LSI changes to the input mode, and a high-level signal is supplied from the LSI tester 6 to the input / output common terminal 11, but the input / output switching signal input to the control terminal of the output buffer 10 is output. Since the signal on the line 12 is still outputting a low level due to a delay in the internal circuit 2, a period occurs in which the high level from the LSI tester 6 and the bus fight occur and become an intermediate level.

Since the intermediate level is detected by the differential comparator circuit section 15 and is output at a low level, and the output of the differential comparator circuit section 16 outputs the intermediate level as a high level, the exclusive NOR of the EX-NOR 19 at the point D is exclusive. The logical sum signal outputs a low level, and the signal at the point E becomes low level only during a period delayed by the logical sum of this signal and a signal delayed by a predetermined time in the delay circuit 22 by the OR 20.

Since the input / output switching signal at the point C is still at the high level, the flip-flop 31 of the control section 3 receives the low level at the point E and is set to output a low level. In response to the low level, the output of the AND 34 is inverted and the low level is output as the output of the control unit 3 from the output buffer 10.
To a floating state. Therefore, the level of the input / output shared terminal 11 becomes the high level supplied from the LSI tester 6.

At timing t 4, the LSI tester 6 supplies a low-level signal to the input / output terminal 11 while the LSI remains in the input mode. The driving capacity is L
Since the driving capability of the output buffer of the SI is much higher, the input signal transitions to the low level quite steeply. Even during this transition period, the output level of the differential comparison circuit section 15 detects the intermediate level again and outputs a low level because the output of the differential comparison circuit section 15 is at the intermediate level for a short period, and the output of the differential comparison circuit section 16 detects the intermediate level. Since a high level is output, EX at point D
The exclusive-OR signal of the NOR 19 outputs a low-level pulse signal. However, since the period of the pulse signal which becomes low level at the intermediate level is shorter than the delay time of the delay circuit 22, the pulse signal does not appear at the OR output of the OR 20 and the high level which is a normal output signal is maintained. Will be. Therefore, the output signal line 12 of the control unit 3 remains at the low level, and the input buffer 9 can input a normal low-level signal from the LSI tester.

Next, in FIG. 8, when the input / output mode of the LSI at the point A in FIG. 1 is switched from the output mode to the input mode, the signal of the input / output common terminal 11 to which the signal is supplied from the LSI tester 6 is shown. 1, the input / output switching signal at point F in FIG. 1, the impedance state of the input / output terminal at point B in FIG. 1, the voltage at the input / output terminal at point B in FIG. 1, and the through current waveform of the input buffer 9 in FIG. And state changes of the ground potential of the input buffer 9.

When the signal at the input / output switching signal point (point F) in FIG. 8 is switched from a dotted line (conventional waveform) in the present invention to a solid line (waveform of the present invention), the input speed is increased. The impedance time at the output common terminal 11 (point B), the through current time of the input buffer 9, and the noise time of the ground potential of the input buffer 9 are also shorter than before.

To summarize the above operation, the input / output common terminal 11 is set to the intermediate potential state when a bus fight occurs due to the output value of the input / output buffer 5 and the input value of the LSI tester 6, and the intermediate potential detection unit 4, the first differential comparison circuit section 15 outputs a low level, the second differential comparison circuit section 16 outputs a high level, and the EX-NOR circuit 19 outputs a low level. A time shorter than the delay value of the delay circuit 22 itself;
If the signal is an intermediate potential detection signal, a low level is not output as the output value of the OR 20. Therefore, if the output value of the input / output buffer 5 and the input value of the LSI tester 6 are intermediate potential output values other than the bus fight, a low level is not output as the output value of the OR 20.

The low level output signal of the intermediate potential output circuit 4 is input to the NAND 242 of the control unit 3 and the output value is input to the NAND 241 at the high level. One input of the NAND 242 is a signal from the input / output terminal 8 via the internal circuit 2 and outputs a high level during the delay time of the internal circuit itself. The output of the NAND 241 is at a low level, and the test terminal 7 is fixed at a low level during LSI measurement by direct input from an external terminal, so that the output value of the OR 25 is at a low level. The input of AND26 is the LSI internal circuit 2
However, since the output of the OR 25 is at the low level, the output of the AND 26 is at the low level and is output to the input / output switching signal line 12.

The intermediate potential at the time when the input / output buffer 5 switches from the output mode to the input mode is detected by the intermediate potential detecting section 4, so that the intermediate potential is higher than the signal from the input / output switching terminal 8 input via the internal circuit 2. High-speed input to the input / output switching signal line 12 of the input / output buffer 5 is enabled.

When the input / output terminal 11 of the input / output buffer 5 is in the input / output determined state, the EX-NOR
19 outputs a high level, and the control unit 3 receives the high level from the intermediate potential detection unit 4 and outputs the signal from the input / output switching terminal 8 to the input / output switching signal line 12 Will be done.

If the signal from the input / output switching terminal 8 arrives at the input / output switching signal line 12 earlier than the signal from the intermediate potential detector 4, the signal from the input / output switching terminal 8 is input. . As a result, the signal that has reached the input / output switching signal line 12 earlier is input to the output buffer 10 as an input mode switching signal.

According to the above-mentioned embodiment, referring to FIG. 9 showing the input / output characteristics in manufacturing, samples A and B show an input voltage of 5 V on the horizontal axis and an output voltage of 5 V on the vertical axis. , C, the output voltage is 2V, for example.
It can be seen that the characteristic variation width between them is within 50 mV.

[0079]

According to the semiconductor integrated circuit of the present invention described above, at least one test terminal and an input / output switching terminal for switching an input / output buffer to an input mode or an output mode in response to an input / output switching signal supplied from the outside. An intermediate potential detecting means for detecting the potential of the common input / output terminal when a test signal is input to the test terminal; and receiving an output signal of the intermediate potential detecting means and outputting an input / output switching signal to the input / output buffer. The first effect is that the time required for a through current of about 60 mA per input / output buffer to flow through the input / output buffer due to the intermediate potential state on the input / output line is reduced, and that the input / output About 60m per
The rise time of the ground potential of V can be shortened, and a test trouble that cannot be measured due to noise at the time of measuring the LSI is eliminated.

The reason is that the intermediate potential detection signal generated by the bus fight can be input to the input / output switching line of the input / output buffer faster than the signal output from the internal circuit.

The second effect is that although a threshold voltage of about 1.0 V or more is required for an inverter or a buffer,
High-precision detection can be performed at a voltage of 0 mV or more, and the circuit scale for avoiding bus fight has also been reduced.

The reason is that a differential amplifier is used for the intermediate potential detecting section, and a voltage value based on the resistance division ratio is used as the reference voltage, so that the threshold voltage level is kept within a few percent of the manufacturing variation of the resistance ratio. Is now possible.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of a semiconductor integrated circuit of the present invention.

FIG. 2 is a circuit diagram of an intermediate potential detecting unit in FIG.

FIG. 3 is a circuit diagram of a differential comparison unit and a reference voltage generation unit in FIG. 2;

FIG. 4 is a circuit diagram of a modification of the reference voltage generator in FIG. 2;

FIG. 5 is a circuit diagram of another modification of the reference voltage generator in FIG. 2;

FIG. 6 is a circuit diagram of a control unit in FIG. 2;

FIG. 7 is a diagram showing a load straight line for setting a reference voltage.

FIG. 8 is a timing chart for explaining the operation of the present invention.

FIG. 9 is another timing chart for explaining the operation of the present invention.

FIG. 10 is a characteristic diagram showing variations in a manufacturing process of the semiconductor integrated circuit of the present invention.

FIG. 11 is a block diagram illustrating an example of a conventional semiconductor integrated circuit.

FIG. 12 is a timing chart for explaining the operation of a conventional semiconductor integrated circuit.

FIG. 13 is a block diagram showing still another example of a conventional semiconductor integrated circuit.

FIG. 14 is a block diagram showing another example of a conventional semiconductor integrated circuit.

FIG. 15 is a characteristic diagram showing variations in a manufacturing process of a conventional input / output buffer of a semiconductor integrated circuit.

[Explanation of symbols]

Reference Signs List 1 semiconductor integrated circuit (LSI) 2 internal circuit 3 control unit 4 intermediate potential detection unit 5 input / output buffer 6 LSI tester 7 test terminal 8 input / output switching terminal 9, 30, 31, 44 input buffer 10, 27, 28, 43 output Buffer 11 I / O shared terminal 12 I / O switching signal line 13 First reference voltage generator 14 Second reference voltage generator 15 First differential comparison circuit 16 Second differential comparison circuit 17 First Differential comparator 18 Second differential comparator 19 EX-NOR (exclusive OR) 20, 25 OR (logical OR) 21 Delay circuit 22 Delay element 23, 46, 48, 49, 52 Inverter 26 AND 29 Floating Detection circuit 32, 36, 38 Matching circuit 35, 37 Delay line 33, 34, 39, 40 Gate 41, 42 Resistance element 45 Comparator 47, 24 , 242 NAND 50,51 NOR 53 input and output terminals 131,132,141,142 resistance element 133,143,151,154,155,161,1
62, 164, 166 p-channel MOS transistors 134, 143, 144, 152, 155, 153, 1
56,163,165,167 n-channel MOS
Transistor

Claims (9)

(57) [Claims] At least one test terminal in a semiconductor integrated circuit comprising an input terminal, an output terminal, an input / output shared terminal, and an input / output buffer connected to the shared terminal and controlled to switch between an input mode and an output mode. And an input / output switching terminal for switching the input / output buffer to the input mode or the output mode in response to an externally supplied input / output switching signal. When a test signal is input to the test terminal, An intermediate potential detecting means for detecting the potential of the writing output shared terminal, and input / output switching control means for receiving the output signal of the intermediate potential detecting means and outputting the input / output switching signal to the input / output buffer. Semiconductor integrated circuit. 2. An intermediate potential detecting means, comprising: a first reference voltage generating means and a first differential comparing means having the reference voltage as one input and the other input connected to the input / output terminal. A second differential voltage generating means, a second differential voltage comparing means having one input as its reference voltage, and the other input connected to the input / output terminal, and an output of the first differential frequency comparing means. 2. The semiconductor integrated circuit according to claim 1, further comprising: intermediate potential generation means for generating an intermediate potential detection signal by an exclusive OR of a signal and an output signal of said second differential comparison means. 3. An exclusive-OR circuit for inputting output signals of the first and second differential comparing means, respectively, and an intermediate potential generating means for converting an output signal of the exclusive-OR circuit into a predetermined signal. A delay circuit that delays by a time, and an OR circuit that takes a logic of a delay output signal of the delay circuit and an output signal of the exclusive OR circuit. 3. The semiconductor integrated circuit according to claim 2, wherein the signal is a potential detection signal. 4. The intermediate potential generating means, when the potential of the input / output terminal transitions from a high logic level to a low logic level, sets the intermediate potential during the transition period to the first and second difference. Even if the pulse signal is detected by the dynamic comparison means and the exclusive OR circuit, if the pulse width of the pulse signal is smaller than the delay time of the delay circuit, the pulse signal is not generated as the intermediate potential detection signal and the intermediate potential is not generated. 4. The semiconductor integrated circuit according to claim 3, wherein the detection signal maintains the previous output state. 5. The intermediate potential generating means generates the intermediate potential detection signal if the pulse width of the pulse signal is wider than the delay time of the delay circuit, and outputs the intermediate potential detection signal from the input / output switching terminal according to the intermediate potential detection signal. 5. The semiconductor integrated circuit according to claim 4, wherein said input / output buffer is switched to said input mode at a timing earlier than a supplied signal. 6. The first reference voltage generating means, wherein a first impedance element having one end connected to a power supply potential and a second impedance element having one end connected to a ground potential are connected in series with each other. The potential of the connection point is set higher than the intermediate potential, and the second reference voltage generating means includes:
A third impedance element having one end connected to the power supply potential and a fourth impedance element having one end connected to the ground potential are connected in series with each other, and the potential at this series connection point is set lower than the intermediate potential. The semiconductor integrated circuit according to claim 2. 7. The first, second, third, and fourth impedance elements are each a resistance element, and the resistance value of the second impedance element is larger than that of the first impedance element. 7. The semiconductor integrated circuit according to claim 6, wherein the third and fourth impedance elements are set as resistance elements, and the resistance value of the third impedance element is set to be larger than that of the fourth impedance element. . 8. The first impedance element is a first p-channel MOS transistor, the second impedance element is a first resistance element, and the third impedance element is a second resistance element. Wherein the fourth impedance element is a first n-channel MOS transistor, and the on-resistance value of the first p-channel MOS transistor is smaller than the resistance value of the first resistance element; 7. The semiconductor integrated circuit according to claim 6, wherein a resistance value of said resistance element is set to be larger than an on-resistance value of said first n-channel MOS transistor. 9. A second p-channel MOS transistor is inserted in series between the first impedance element and a power supply potential, and a second n-channel MOS transistor is inserted between the second impedance element and a ground potential. Are inserted in series, a third p-channel MOS transistor is inserted in series between the third impedance element and the power supply potential, and a third n-channel MOS transistor is inserted between the fourth impedance element and ground potential. A MOS transistor is inserted in series connection, the test signal is applied to the gate electrodes of the second and third p-channel MOS transistors, and the test signal is applied to the gate electrodes of the second and third n-channel MOS transistors. 9. The semiconductor integrated circuit according to claim 8, wherein an inverted signal of said test signal is input.