JP2010020801A - Microcomputer - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a microcomputer for accessing a double-data-rate (DDR) synchronous DRAM at high speed. <P>SOLUTION: The microcomputer including a central processing unit, a memory control means, and a clock control part outputs a clock supplied from the clock control part to the outside of the microcomputer as an external clock, and outputs a clock obtained by inverting the external clock to the outside of the microcomputer. The memory control means generates, in response to the clock, a data strobe signal shifted between a first potential state and a second potential state. A memory controlled by the memory control means is a DDR synchronous memory which inputs and outputs data synchronously with the rising edge and trailing edge of the data strobe signal. The memory control means outputs, when writing data to the synchronous memory, the data synchronously with the rising edge and trailing edge of the data strobe signal. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a microcomputer connected to a semiconductor memory, and more particularly to a microcomputer that is connected to a double data rate (DDR) type synchronous dynamic random access memory (SDRAM) to read and write data. It is related to technology effective when applied to.

  The present invention also relates to a technique that is effective even when applied to a microcomputer system comprising the microcomputer and the double data rate type synchronous dynamic random memory.

  A technique for connecting a microcomputer to a synchronous random access memory (SDRAM) adopting a double data rate (DDR) system, reading data from the memory, or writing data is conventionally used. In this case, a memory controller for controlling the DDR type SDRAM is connected between the microcomputer and the DDR-SDRAM for connecting the microcomputer to the DDR-SDRAM.

Japanese Patent Laid-Open No. 5-120114

  When the memory controller is provided independently of the microcomputer and the DDR-SDRAM in order to connect the microcomputer and the double data rate (DDR) type memory, between the microcomputer and the memory controller, and the memory controller It is necessary to exchange addresses and data with the memory. For this reason, the speed performance is reduced because data and addresses are exchanged via the memory controller. Furthermore, since the signal passes through a useless path, useless power is generated. As a result, the performance of a microcomputer system combining a microcomputer and a DDR-SDRAM has been hindered.

  In addition, when the microcomputer and the DDR-SDRAM are formed on one semiconductor substrate, a memory controller for controlling a DDR type memory is provided outside the microcomputer and the DDR-SDRAM formed on the same substrate. It was necessary to connect, and as described above, it was an obstacle to performance improvement.

  Further, when a DDR type memory controller is connected between the microcomputer and the DDR-SDRAM as described above, the number of parts increases, the mounting area increases, and this is an obstacle to lowering the cost.

  An object of the present invention is to provide a microcomputer that improves the performance of reading and writing data between the microcomputer and the DDR-SDRAM by incorporating the functions of the microcomputer and the DDR type memory controller into the microcomputer. Is to provide.

  Furthermore, an object of the present invention is to provide a system using a DDR type SDRAM at a low cost by incorporating a memory controller in a microcomputer, thereby reducing the number of components and reducing the mounting area.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  An outline of typical ones of the present invention will be briefly described below.

  In the present invention, in order to achieve the above object, the data of the DDR-SDRAM is transferred on the same semiconductor substrate as the microcomputer by an address signal consisting of a plurality of bits output from the central processing unit (CPU) of the microcomputer. Necessary for memory control and the like for memory control means for generating and outputting various strobe signals for controlling the memory in a double data rate method for reading and writing data, and for the central processing unit and the memory control means. And a clock control means for supplying a correct clock.

  Specifically, on the same semiconductor substrate as the microcomputer, a high-speed internal clock signal serving as a reference for generating an address signal for controlling the memory, generating a strobe signal, and inputting / outputting data is supplied to the memory. Means are formed that allow data to be read from and written to memory in a double data rate manner using a low speed external output clock signal.

  As described above, it is possible to provide a microcomputer in which the microcomputer and the DDR-SDRAM are directly connected and it is not necessary to separately connect a memory controller between the microcomputer and the DDR-SDRAM. Further, it is possible to construct a microcomputer system in which the microcomputer and the DDR-SDRAM are directly connected.

  Furthermore, when the microcomputer and the DDR memory are formed on the same semiconductor substrate, it is possible to provide a microcomputer or microcomputer system that does not require a DDR memory controller to be connected to the outside of the semiconductor substrate.

  As described above, the efficiency of data exchange between the microcomputer and the memory is improved, high-speed data transfer is possible, and power consumption can be reduced. Furthermore, it is possible to provide a low-cost system with a small number of parts, a smaller area than conventional ones.

  According to the present invention, a double data rate (DDR) synchronous DRAM (SDRAM) can be connected to a processor without connecting a memory controller separately. Furthermore, by using the internal clock of the processor, it is possible to reduce the circuit for controlling the DDR-SDRAM, and the area efficiency is high, and high-speed access between the processor and the DDR-SDRAM is possible. It becomes.

1 is a block diagram of a microcomputer and a memory according to the present invention. The block diagram of the clock control part concerning this invention. FIG. 4 is a timing chart of clocks necessary for memory control according to the present invention. 1 is a connection diagram of a microcomputer and a memory according to the present invention. 1 is a schematic diagram of a register according to the present invention. 4 is a timing chart when the double data rate synchronous DRAM (DDR-DRAM) according to the present invention is read-accessed. 5 is a timing chart when a double data rate synchronous DRAM (DDR-SDRAM) is write-accessed using the memory control device according to the present invention. FIG. 3 is a block diagram of a bus data buffer and a control signal generator according to the present invention.

  FIG. 1 shows one typical embodiment of the present invention. A microcomputer (MPU: microprocessor unit) formed on one semiconductor substrate and a double data rate synchronous DRAM (DDR-SDRAM) 21 formed on one semiconductor substrate are shown. Although only one DDR-SDRAM is shown in the figure, a configuration in which a plurality of DDR-SDRAMs are connected to one microcomputer may be employed.

  The inside of the microprocessor unit in FIG. 1 will be described. Reference numeral 1 denotes a memory interface module for controlling 21 DDR type memories, 2 a module composed of a central processing unit (CPU) and a cache memory (Cache), and 3 a direct memory access controller (DMAC) module. The CPU / Cache module 2 and the DMAC module 3 specify the predetermined memory cell in the memory for reading the data stored in the memory or storing the data in the memory toward the memory interface module 1. In addition to the address, an access request is also output. The access request that the CPU / Cache module makes to the memory interface module includes a memory access request for reading from and writing to the memory, and a read / write register access request for the register 6 in the memory interface module. and so on. As an access request made by the DMAC module to the memory interface module, there is a memory access request for reading / writing the memory.

  Of the above register access requests from the CPU / Cache module to the register 6 in the memory interface, when the CPU / Cache module makes a write request to the register, the CPU / Cache module requests the register write access request as a request in the memory interface module. Output to the control unit 4. At the same time, data to be written to the register 6 is output to the register 6 via 103. Upon receiving a request for writing to the register from the CPU / Cache module, the request control unit 4 outputs a register access request 101 to the register R / W control unit 5. The register R / W control unit that has received the register access request outputs a register write signal 102 to the register 6. Data sent from the CPU / Cache module to the register 6 is written into the register 6 by the series of operations described above.

  When the CPU / Cache module needs data stored in the DDR-SDRAM, the CPU / Cache module requests a memory access request and an address for designating a predetermined location of the DDR-SDRAM as a request in the memory interface module. Output to the control unit 4. When the request control unit receiving the memory access request recognizes that the CPU / Cache module requests access to the memory, the request control unit outputs a memory access request 104 to the external bus control unit 7 in the memory interface module. The external bus control unit that has received the memory access request controls the address control unit 8, the control signal generation unit 9, and the data control unit 10 to start memory access with the DDR-SDRAM.

  The address control unit 8 described above generates address information to be output to the memory from the memory address in the data stored in the register in advance and the request address 107 output from the request control unit 4. The generated address is transferred to the memory 21 via the address bus 34 connected to the DDR-SDRAM. The control signal generator 9 receives the memory information 105 in the data stored in advance in the register 6 via the external bus controller 7, and generates a memory control signal 35 necessary for memory access according to the received memory information. , Output to memory. The memory control signal includes various commands for instructing the memory to read from the memory / write to the memory. The data control unit 10 controls the bus data buffer 11 according to an instruction from the external bus control unit 7, and performs data exchange between the microprocessor and the memory, which is performed via the data bus 36 connected to the DDR-SDRAM. Controls sending and receiving.

  In this embodiment, a microprocessor with a built-in DMAC module is used, but a microprocessor without a built-in DMAC module may be used.

  FIG. 2 shows a detailed example of the clock control unit 12 formed in the microprocessor of FIG. The clock control unit 12 mainly includes a clock generation unit 13 that generates a reference clock and a clock frequency divider 14 that generates a frequency that is ½ of the clock generated by the clock generation unit 13. The clock generated by the clock generator 13 becomes the reference clock of the microprocessor of this embodiment, that is, the internal clock 30 supplied to the central processing unit or the like. In this embodiment, the reference clock is generated by the clock generator, but there is no problem even if it is a clock supplied from the outside.

  The clock divider 14 is mainly composed of a latch means 15 and a frequency divider inverter 16. The output of the latch 15 is inverted through the frequency divider inverter 16 to be input to the latch, and data is taken in at the rising edge of the clock signal, thereby generating a reference clock, that is, a clock having a frequency half that of the internal clock 13. . A clock having a frequency half that of the internal clock generated by the clock divider is output as an external clock 31 to the outside of the microprocessor, that is, to a DDR-SDRAM or the like. Further, a signal obtained by inverting the clock having a frequency ½ of the internal clock generated by the clock divider by the external clock inverter 17 is output to the outside as the inverted clock 32. Further, a clock having a frequency ½ of the reference clock is also sent to the external bus control unit in the memory interface module 1 and used as the output command synchronization signal 33. There are various modifications of the configuration of the clock divider and the like in addition to the present embodiment, but the description thereof is omitted.

FIG. 3 shows command synchronization timing in the memory interface module 1.
The memory interface module is supplied with an internal clock of the processor and a command synchronization signal 33 having a frequency ½ of the internal clock output from the clock controller 12. The command synchronization signal is a clock having the same frequency and the same phase as the external clock supplied to the DDR-SDRAM outside the processor. The memory interface module controls the memory to receive various commands at the rising edge of the external clock 31. The memory can receive the command output to the memory during the period when the external clock is LOW (T2) at the time of the next rising edge of the external clock, but the memory receives the command during the period when the external clock is HIGH. The command given to it cannot be received. Therefore, it is necessary to output the control signal only when the command can be output, that is, when the external clock is LOW, and not to output the control signal during the command output disabled period.

  In this embodiment, the command output cycle is one cycle of the internal clock (30), but the command output cycle may be one cycle of the external clock (31).

  FIG. 4 shows an example of connection between a microprocessor and a double data rate (DDR) synchronous DRAM. Memory control signals necessary for accessing the DDR-SDRAM 21 include a clock (CLOCK), an inverted clock (/ CLOCK), a clock enable signal (CKE), a chip select signal (/ CS), a row address strobe signal (/ RAS), a column There are an address strobe (/ CAS), a write enable signal (/ WE), a data mask enable signal (DQM), and a data strobe signal (DQS). In addition to these memory control signals, there are an address (Addr.) For designating an address of the memory and data (DATA) exchanged between the microprocessor and the memory. By outputting various control signals, the microprocessor gives various commands, addresses, and data for defining memory operations to the double data rate synchronous DRAM, enabling read from the memory and write access to the memory. To do. In the drawing, signals with a horizontal line at the top of the alphabet and signals with a diagonal line before the alphabet in the above indicate that the signal is activated when the signal becomes LOW level. Yes.

  FIG. 5 shows a schematic diagram of the register 6 in the microprocessor. Although not particularly limited, in this embodiment, the register 6 is a 32-bit register. Memory access timing information is set in TRC0 to 2, TPC0 to 2, RCD0 to 1, and TRWL2 to 0. Also, the bit numbers of the row address and the column address are set to 0 from AMX2. The contents of these registers 6 can be set according to the type and operating frequency of the DDR-SDRAM used.

  FIG. 6 shows a timing chart at the time of read access from the DDR-SDRAM by the microprocessor, and FIG. 7 shows a timing chart at the time of write access from the microprocessor to the DDR-SDRAM.

  In FIG. 6, an ACTV command (not shown) is issued to DDR-SDARM in a Tr cycle that is one cycle of the internal clock of the processor. At the same time, the row address (Row) is notified to the memory via the address (Addr.) Line. At the rise of the Trw cycle following Tr, that is, at the rise of the external clock, the memory takes in the row address (Row) applied through the address line. Thereafter, the memory 21 waits for a prescribed cycle. After the specified cycle has elapsed, a READ command is issued in the Tc1 cycle to notify the column address (c1), and the memory 21 is applied via the address line at the start of the Tc2 cycle, that is, at the rise of the external clock. The column address (c1) is fetched. Thereafter, after waiting for a period corresponding to the latency defined in advance in the memory, Tc2 and Tc3, the read DATA is sampled. In this embodiment, since the burst length of the memory is 4, after 4 cycles after issuing the READ command in the Tc1 cycle, the READA command, which is a read command with auto precharge, is issued as a subsequent command, and the precharge is executed. ing.

  Also in FIG. 7 showing the timing at the time of writing to the memory, the ACTV command is issued in the Tr cycle, and the row address is supplied to the memory via the address line (Addr.). At the rising edge of Trw, which is the next cycle following Tr, of the external clock supplied to the memory, the memory takes in the supplied row address. Next, a WRIT command is issued in the Tw1 cycle, and a column address is supplied to the memory via the address line. Further, in the cycle of Tw1, write DATA is driven. In this embodiment, since the memory burst length is 4, after 4 cycles of issuing the WRIT command in the Tw1 cycle, a WRITE command, which is a write command with auto precharge, is issued as a subsequent command, and the precharge is executed. ing.

  If the subsequent access is to the same address as the row address issued by Tr, the read / write command without precharge is terminated at the end of the access, not the read / write command with precharge, and the read of the Tc1 cycle is performed. Alternatively, access can be continued only by issuing a write command, and access can be performed at high speed for Tr and Trw cycles.

  FIG. 8 shows details of the bus data buffer 11 and the control signal generator 9 shown in FIG. Only the data strobe controller 50 is shown for the control signal generator. In the DDR-SDRAM, the change of the data signal output from the memory at the time of data reading and the change of the data strobe signal are the same timing. The memory interface is configured to capture data with a data strobe signal delayed by 90 degrees from the external clock. Further, the memory operation clock and the data change timing are not defined, and data cannot be sampled with the memory operation clock.

  On the other hand, when writing data, the output of the data strobe signal is specified so that the memory can capture data at the rising edge and falling edge of the data strobe signal, and the data setup / hold time is specified for the data strobe signal. Yes.

At the time of writing data, the memory controller needs to output data in synchronization with the rising and falling edges of the external clock, and simultaneously output a data strobe signal that is delayed by 90 degrees from the external clock.
Since both the external clock serving as a reference for memory operation and an internal clock having a frequency twice that of the external clock are generated inside the processor, the phase difference between the external clock and the internal clock can be controlled. Further, by using an internal clock having a frequency twice that of the external clock, it is possible to easily perform a phase shift of 90 degrees with respect to the external clock.

  Since the phase difference between the external clock and the internal clock can be controlled, it is possible to capture data at the rising edge of the internal clock without using a data strobe signal when capturing data when reading data. The internal clock has twice the frequency of the external clock, and data that changes in synchronization with the rise and fall of the external clock can be captured at the rise of the internal clock. When the data strobe signal output from the memory is used, a phase shift circuit for delaying the phase by 90 degrees is required. However, this embodiment is not particularly necessary. As a result, there is an advantage that even if the frequency is changed, it is not necessary to change the phase shift circuit. Further, when a memory controller is provided outside the processor, there is no correlation between the data taken by delaying the phase of the data strobe signal by 90 degrees and the reference clock for the processor operation, and the data signal becomes an asynchronous signal. Synchronization circuit becomes necessary. In other words, it is disadvantageous in terms of speed.

  When writing data, the internal clock is used and output so that the data strobe signal changes at the falling edge of the internal clock, whereby the 90-degree phase shift of the external clock can be easily performed. A phase shift circuit is not required as in the case of reading. Since the data signal is driven from the memory side when data is read, drive control is performed by a tri-state buffer so that the signal does not collide.

  Further, by using an internal clock having a frequency twice that of the external clock, it is possible to cope with a change in the frequency of the external clock for improving speed performance.

  As described above, by incorporating the DDR-SDRAM memory controller and the clock control unit in the processor, it is possible to supply the internal clock as the reference for the processor operation and the external clock as the reference for the memory operation, and generate the memory control signal. And data signal input / output control can be realized with a simple circuit. Further, unnecessary synchronization circuits can be reduced.

  In addition, embodiment mentioned above is one embodiment of this invention to the last, and this invention is not limited to the said embodiment. For example, the phases of the internal clock, the synchronization signal, and the external clock shown in FIG. 3 are not limited to those in the drawing, and the synchronization signal and / or the external clock may be a signal inverted from the drawing. In the description related to FIG. 8, when reading data from the memory, it is possible to capture data at the falling edge of the clock instead of capturing data at the rising edge of the internal clock. Similarly, the same can be said for the timing of data writing.

1 Memory interface module 2 CPU / Cache module 3 DMAC
4 Request Control Unit 5 Register R / W Control Unit 6 Register 7 External Bus Control Unit 8 Address Control Unit 9 Control Signal 10 Data Control Unit 11 Data Buffer 12 Clock Control Unit 13 Clock Generation Unit 14 Clock Divider 15 Latch 16 Divide Inverter 17 external clock inverter 20 microprocessor 21 double data rate synchronous DRAM (DDR-SDRAM)
30 Internal clock 31 External clock 32 Inverted clock 33 Output command synchronization signal 34 Address 35 Memory control signal 36 Data 101 Register access request 102 Register write signal 103 Data 104 Memory access request 105 Memory timing information 106 Memory address information 107 Request address

Claims (1)

A central processing unit;
Memory control means connected to the central processing unit;
A clock controller for supplying a clock to the central processing unit and the memory control means, and a microcomputer formed on one semiconductor chip,
The microcomputer outputs the clock supplied from the clock control unit as an external clock to the outside of the microcomputer, and outputs an external inverted clock obtained by inverting the external clock to the outside of the microcomputer.
The memory control means can generate a data strobe signal corresponding to the clock and transitioning between a first potential state and a second potential state;
The memory controlled by the memory control means is a double data rate synchronous memory capable of inputting / outputting data in synchronization with a rising edge and a falling edge of the data strobe signal,
The memory control means outputs data to the outside in synchronization with the rising edge and falling edge of the data strobe signal when writing data to the synchronous memory,
The central processing unit generates a memory address for accessing the synchronous memory;
The microcomputer characterized in that the memory control means can output the memory address in synchronization with the external clock.

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