KR100201283B1 - Communication system micro-wired control and matching - Google Patents

Abstract

1. The technical field to which the invention described in the claims belongs:

A technology related to interfacing and microwired control between a processor and a transmission chip of a communication system.

2. The technical problem to be solved by the invention:

Provided are a circuit and a method capable of performing micro-wired control by one chip without having to individually provide a plurality of control circuits, and reducing the load of a microprocessor pointed out as a conventional problem.

3. Summary of the solution of the invention:

A data interface unit for performing communication between the adapter, which is a transmission chip, and the microprocessor in the system; A selection unit connected to a data bus of the microprocessor to generate a selection signal; And a timing generator and a controller connected to the interface unit and the selection unit to generate timing signals necessary for operation of the clock and each unit by using a frame synchronization signal and a system clock provided from the system. The apparatus may further include a holding signal generator that is connected to the timing generator and the controller to provide the holding signal and receives and latches and gates the timing signals.

4. Important uses of the invention:

It is useful for micro wired control of a private switching system having a large number of subscribers.

Description

Method and circuitry for performing microwired control and matching of communication system

1 is an overall block diagram of a microwired control circuit according to the present invention.

2 is a detailed circuit diagram of timing generation and a controller in FIG.

3 is a timing diagram for each part of FIG. 1 and FIG.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a communication system such as a private branch exchange (PBX) or digital key phone system. In particular, the present invention relates to a digital adapter for subscriber circuits that is connected between a phone and a main device to perform signaling. A circuit and method for controlling and interfacing with a host device.

In general, a communication system such as a private exchange or a digital keyphone system usually includes a digital adapter for a subscriber circuit connected between the telephone and the main device to perform signaling. One such adapter is known in the art from the TP3401 series of National Semiconductor Corporation in the United States.

Since the communication system has many adapters in proportion to its capacity, a circuit for micro-wired control is used between the microprocessor and the adapters of the communication system. This circuit performs data interfacing between the adapters and the microprocessor and appropriately controls the adapter in response to instructions of the microprocessor.

In the related art, a plurality of control chips are used for such micro-wired control, and accordingly, there is a problem of increased cost and complicated circuits. In addition, in the related art, since a holding signal for holding the microprocessor is generated in software while a signal is generated in the adapters, the burden of the microprocessor increases accordingly, which impairs actual call processing. There was a problem.

Accordingly, it is an object of the present invention to provide a circuit and method that can solve the conventional problems as described above.

Another object of the present invention is to provide a micro-wired circuit and a method thereof capable of efficiently controlling a digital adapter for a subscriber circuit connected between a telephone and a main device and performing signaling in a communication system, and efficiently interfacing with the main device. have.

It is still another object of the present invention to provide a holding signal generating circuit and method which can reduce the burden on a microprocessor in a communication system.

According to a circuit of the present invention for achieving the above objects, there is provided a circuit comprising: a data interface for performing communication between an adapter and a microprocessor in a system by interfacing inputs and outputs of control channel data in response to an applied clock; A selector coupled to a data bus of the microprocessor to generate a select signal for operating one of the adapters by loading and gating the control channel data according to a chip select signal; And a timing generator and a controller connected to the interface unit and the selection unit to generate timing signals necessary for operation of the clock and each unit by using a frame synchronization signal and a system clock provided from the system. The apparatus may further include a holding signal generator that is connected to the timing generator and the controller to provide the holding signal and receives and latches and gates the timing signals. According to the circuit of the present invention described above, it is possible to perform micro-wired control even by one chip without having to individually provide a plurality of control circuits, and to reduce the load of the microprocessor pointed out as a conventional problem.

Hereinafter, a micro wired control circuit and a method of use according to a preferred embodiment of the present invention will be described with the accompanying drawings. In the following description, the detailed items for such constructions are described in detail in order to provide a more thorough understanding of the present invention. However, it will be apparent to those skilled in the art that the present invention may be practiced without these specific details. Moreover, features and functions of well-known structures are not described in detail in order not to obscure the present invention.

Referring to FIG. 1 to better understand the overall structure of the circuit according to the present invention, the circuit includes a data interface 100, a selector 200, a timing generator and a controller 300, and a holding signal generator 310. Include. The interface unit 100 is a part that provides serial communication between the microprocessor's data bus and the adapters through the control channel data input CI and the output CO. The selector 200 is responsible for providing a chip select signal for designating and operating the plurality of adapters. The timing generation and control unit 300 is a part that provides timing signals and control signals for timing control of the entire circuit. By the above configuration, micro-wired control is performed between the microprocessor and the transmission chip (adapter), and the data clock DCLK and the clock CLK of the control clock CCLK required for the control of the transmission chip are provided, and the enable of the transmission chip is enabled. Signals / CS0- / CS7 are generated by the chip select signal and the timing signal of the microprocessor. In addition, by exchanging control and status registers through the CI and CO for micro-wired control between the transfer chip and the microprocessor, the microprocessor can control the transfer chip and recognize the state of the transfer chip. In FIG. 1, the interface unit 100 includes a buffer 103, 113, an inverter 101, 107, a parallel / serial converter 103, a multiplexer 109, and a serial / parallel converter 111, and are generally responsible for data interfacing. That is, the interface unit 100 is a part for generating serial data to be actually sent to the transmission chip and loading the serial data received through the transmission chip onto the data bus. Data to be sent to the transfer chip is stored by the buffer 103 and the parallel / serial converter 103 converts the parallel data of the buffer 103 into serial data. Serial data received from the transmission chip is applied to the multiplexer 109, and the serial / parallel converter 111 converts the data into parallel data and provides the same to the buffer 113. Here, the converters 105 and 111 operate by opposite edge clocks, and the load enable is delayed slightly after the low waveform of the channel enable signal as shown in 3C of FIG.

The selector 200 includes an inverter 202, a buffer 204, and a gate part 206. In this case, the selector 200 is configured to designate the eight transfer chips, that is, the adapter. The operation of the selector 200, when the processor provides the chip select signal CHIPSEL through the inverter 202, the buffer 204 receives channel data of the data bus and sets it high. Thereafter, when the channel enable signal CHENB signal is applied to the timing generation and control unit 300, the transmission chip is operated as a low signal with a slight timing margin. That is, data is loaded into the buffer 204 and enabled as the channel enable signal. This is because the enable end of the gate unit 206 has a configuration connected to the control unit 300.

A detailed configuration of the timing generation and the control unit 300 is shown in FIG. 2. The signals of the output terminals A and B-G in FIG. 1 coincide with the signals of the output terminals A and B-G in FIG. The controller 300 is provided with a frame registration signal FS, a clock of 4 MHz, and a channel enable signal CHENB from a microprocessor. Here, for convenience of explanation and understanding, FIG. 3 shows the input and output signals of FIG. 1 as 3A-3H. Referring to FIG. 2, the control clock CCLK provided at the output stage G is performed by dividing a clock of C4M, that is, 4 megahertz, to generate a clock of 1 megahertz. This is accomplished by the connection of the two tee flip-flops 302,303 and the di-flop flop 304 in the second figure. The data clock DCLK provided at the output stage F is created by the counter 305 counting the frame sync signal and is generated as 16 kilohertz. In addition, a 2 MHz hertz and a channel enable signal, and a signal of 1 mega hertz, may be applied to a combination of inverters 310,308, di flip-flops 311-314,306,320, di flip-flops 316-318, NAND gates 309,315,321, end gates 319,322, and retarder 307. To generate the AE signal.

Meanwhile, the holding signal generator 310 generating the holding signal DTACK includes an inverter 311, a de-flip flop 312, 315, a NAND gate 313, and an end gate 314 as shown in FIG. The 3B signal of FIG. 3 is obtained. Therefore, the hardware generation of the signal can reduce the load of the microprocessor.

Therefore, according to the present invention as described above, there is an advantage that can control a plurality of adapters with one microwired circuit, and is a digital adapter for subscriber circuits connected between the telephone and the main device in the communication system to perform signaling In addition, there is an advantage of efficiently controlling and interfacing with the main device, and also reducing the burden on the microprocessor in the communication system by the device generation of the holding signal.

Although the above-described invention has been described and limited by way of example with reference to the drawings, the same will be apparent to those skilled in the art that various changes and modifications can be made without departing from the spirit of the invention.

Claims (5)

A circuit located between a microprocessor of a communication system and an adapter for signaling; A data interface for performing communication between the adapter and the microprocessor in the system by interfacing inputs and outputs of control channel data in response to an applied clock; A selector coupled to a data bus of the microprocessor to generate a select signal for operating one of the adapters by loading and gating the control channel data according to a chip select signal: the interface and the selector And a timing generator and a controller for generating timing signals necessary for operation of the clock and each unit by using a frame synchronization signal and a system clock provided from the system. The circuit of claim 1, wherein the circuit further comprises a holding signal generator coupled to the timing generator and the control unit to provide a holding signal to the microprocessor, the holding signal generator configured to receive, latch, and gate the timing signals. . A micro wired control circuit of a private exchange system; Interfacing means for interfacing inputs and outputs of control channel data between a data bus of a microprocessor in the system and an adapter for a subscriber circuit in response to an applied clock; Selection means coupled to the data bus to generate a selection signal for operating one of the adapters by loading and controlling the data of the control channel in accordance with a chip select signal; Timing generation and control means for providing the interfacing means and the selection means with timing signals necessary for the operation of the clock and the respective parts; And holding signal generating means for receiving, latching, and gating the timing signals to provide a holding signal to the microprocessor. A microwired control method between a data bus and a transmission chip of a communication switching system; A selection signal generation step for selecting the transmission chip by gating the loaded data in response to a chip enable signal after loading channel data of the data bus in response to a chip selection signal applied from a processor of the system; An interfacing step of converting the channel data on the data bus in series in response to an applied clock and providing the converted data to the transmission chip, and converting serial data received from the transmission chip in parallel and providing the data to the data bus; Receiving a frame synchronization signal and a system clock applied from a system to generate various timing signals and the clock required for the steps. A microwired control method between a data bus of a private exchange and a transmission chip; A selection signal generating step for selecting the transmission chip by gating the loaded data in response to a chip enable signal after loading channel data of the data bus in response to a chip selection signal applied from a processor of the exchange; An interfacing step of converting the channel data on the data bus in series and providing them to the transmission chip in response to an applied clock, and converting the serial data received from the transmission chip in parallel to provide them to the data bus; Receiving a frame synchronization signal and a system clock applied from the exchange to generate various timing signals and the clock necessary for the steps; Generating a holding signal for holding the microprocessor for a predetermined time by latching and gating using the timing signal.