KR960016350A - Method and circuitry for performing microwired control and matching of communication system - Google Patents

Abstract

1. the technical field to which the invention described in the claims belongs; A technology related to interfacing and microwired control between a processor and a transmission chip of a communication system.

2. The technical problem to be solved by the invention; Provided are a circuit and a method capable of performing micro-wired control by one chip without having to individually provide a plurality of control circuits, and reducing the load of a microprocessor pointed out as a conventional problem.

3. Summary of the Solution of the Invention; A data interface unit for performing communication between the adapter which is a transmission chip and the microprocessor in the system; A selection unit connected to a data bus of the microprocessor to generate a selection signal; And a timing generator and a controller connected to the interface unit and the selection unit to generate timing signals necessary for operation of the clock and each unit by using a frame synchronization signal and a system clock provided from the system. The apparatus may further include a holding signal generator that is connected to the timing generator and the controller to provide the holding signal and receives and latches and gates the timing signals.

4. Significant use of the invention; It is useful for micro wired control of a private switching system having a large number of subscribers.

Description

Method and circuitry for performing microwired control and matching of communication system

As this is a public information case, the full text was not included.

1 is an overall block diagram of a micro-wired control circuit according to the present invention,

2 is a detailed circuit diagram of timing generation and a controller in FIG.

3 is a timing diagram for each part of FIG. 1 and FIG.

Claims (5)

A circuit located between a microprocessor of a communication system and an adapter for signaling; A data interface for communicating the microprocessor time within the system with the adapter by interfacing inputs and outputs of control channel data in response to an applied clock; A selector coupled to a data bus of the microprocessor to generate a select signal for operating one of the adapters by loading and gating the control channel data according to a chip select signal; And a timing generation unit and a control unit connected to the interface unit and the selection unit to generate timing signals necessary for operation of the clock and each unit by using a frame synchronization signal and a system clock provided from the system. . The circuit of claim 1, wherein the circuit further comprises a holding signal generator coupled to the timing generator and the control unit to provide a holding signal to the microprocessor, the holding signal generator configured to receive, latch, and gate the timing signals. . A micro wired control circuit of a private exchange system; Interfacing means for interfacing input and output of control channel data between the data bus of the microprocessor in the system and the adapter for the subscriber circuit in response to an applied clock; Selection means coupled to the data bus to generate a selection signal for operating one of the adapters by loading and NAND-catching the control channel data in accordance with a chip select signal; Timing generation and control means for providing the interfacing means and the selection means with timing signals necessary for the operation of the clock and the respective parts; And holding signal generating means for receiving, latching, and gating the timing signals to provide a holding signal to the microprocessor. A microwired control method between a data bus and a transmission chip of a communication switching system; A selection signal generation step for selecting the transmission chip by gating the loaded data in response to a chip enable signal after loading channel data of the data bus in response to a chip selection signal applied from a processor of the system; An interfacing step of converting the channel data on the data bus in series and providing them to the transmission chip in response to an applied clock, and converting the serial data received from the transmission chip in parallel and providing them to the data bus; And receiving a frame synchronization signal and a system clock applied from the system to generate various timing signals and the clock required for the steps. A microwired control method between a data bus of a private exchange and a transmission chip; A selection signal generating step for selecting the transmission chip by gating the loaded data in response to a chip enable signal after loading channel data of the data bus in response to a chip selection signal applied from a processor of the exchange; An interfacing step of converting the channel data on the data bus in series and providing them to the transmission chip in response to an applied clock, and converting the serial data received from the transmission chip in parallel and providing them to the data bus; Receiving a frame synchronization signal and a system clock applied from the exchange to generate various timing signals and the clock necessary for the steps; Generating a holding signal for holding the microprocessor for a predetermined time by latching and gating using the timing signal. ※ Note: The disclosure is based on the initial application.