KR0161811B1 - Clock regulating circuit and system using it - Google Patents

Abstract

The present invention discloses a clock control circuit and a system using the same. The circuit outputs the normal enable signal in the normal mode in response to the test mode signal and the shift mode signal, outputs the signal in the first state in the clock control mode, and outputs the test enable signal in the partial clocking mode. A multiplexer, a flip-flop for storing and outputting a test enable control signal as a test enable signal in response to a logical multiplication of the shift mode signal and a clock signal, and the selection in response to the clock signal in the second state. A clock signal generator for transmitting an output signal of the means, latching the transmitted signal in response to the clock signal in the first state, and outputting the latched signal as a system clock signal in response to the clock signal. have. Therefore, in the normal mode, power consumption may be reduced by controlling the normal enable signal to disable operations of blocks in which operation is unnecessary. In the test mode, the test is alternately performed from the clock control mode to the partial clocking mode or from the partial clocking mode to the clock control mode. In this case, the test speed may be improved since the clock signal does not need to be disabled.

Description

Clock control circuit and system using same

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock control circuit, and more particularly, to a clock control circuit capable of reducing power consumption and improving testability of an entire chip by controlling a clock signal applied to flip-flops or modules. It is about.

There are two methods of controlling a conventional clock. One method is to stably generate a clock signal input to a flip-flop by using a latch, and the other is to use a transmission gate at a module level. A method of improving testability in space-time by enabling or disabling a clock signal.

1 shows a clock control circuit using a conventional latch and includes inverters 10, 16, 18, 22, and 26, transmission gates 12, 14, 20, and 24, and an AND gate 28. It is.

When the clock signal CK is applied, the value of the output signal CK 'is determined by the value stored in the latch. That is, if the latched value is 0, the value of the output clock signal CK 'is maintained at 0. If the latched value is 1, the clock signal CK is generated as the output clock signal CK'.

When the clock signal CK is fixed to zero, the value of the output clock signal CK 'is fixed to zero regardless of the state of data stored in the latch composed of the inverters 22 and 26 and the transfer gate 24. Then, the value of one of the two input signals NE and TE is ready to be latched. Therefore, at this time, all the flip-flops or modules controlled by the clock signal CK remain in the previous state.

Referring to the operation of the circuit shown in Figure 1 divided into the normal mode and the test mode as follows.

In the normal mode, a low level test mode signal is applied. The transfer gate 12 is turned on in response to the low level test mode signal and transmits a normal enable signal NE. If the normal enable signal NE is at low level, this signal NE is transmitted through the transmission gate 12. The output signal of the transfer gate 12 is latched to the latch through the transfer gate 20 in response to the low level clock signal CK. The latch composed of the inverters 22 and 26 and the transmission gate 24 inverts the low level signal and outputs a high level signal. The AND gate 28 generates the high level clock signal CK 'in response to the high level clock signal. That is, when the normal enable signal NE is at the low level, the latched signal having the high level may be generated as the clock signal CK 'in response to the clock signal CK. On the contrary, when the normal enable signal NE is at the high level, the clock signal CK 'is fixed at the low level.

Accordingly, by controlling the normal enable signal NE in the normal mode, power consumption may be reduced by controlling the enable or disable of the clock signal CK 'applied to the flip-flops or modules.

In the test mode, a high level test mode signal is applied. Therefore, if the low level test enable signal TE is applied, the high level latched signal is output as the clock signal CK 'in response to the clock signal CK. In contrast, when the high level test enable signal TE is applied, the clock signal CK 'is fixed at the low level.

In the test mode, the test is performed by changing the enable or disable of flip-flops or modules. For example, if a test is performed on three blocks, first, disable the first block, enable the second and third blocks, and then perform the test operation. If you enable it and disable the third block to perform the operation, when switching to the second operation after performing the first operation, each block maintains the result value after performing the first operation. Should be Therefore, it is necessary to operate the clock signal CK's to zero and the clock signals CK 'to all zeros. That is, since the operation of these blocks is performed sequentially, the result value of the previous operation must be maintained as it is. In order to perform the second operation, the test enable signal TE is applied to perform a test operation.

Accordingly, the clock control circuit shown in FIG. 1 can arbitrarily control the enable or disable of the clock signal CK by controlling the normal enable signal NE and the test enable signal TE in the normal and test modes. Therefore, in the normal mode and the test mode, unnecessary power consumption may be reduced by controlling the enable or disable of the clock signal applied to the flip-flops or modules.

The circuit shown in FIG. 1 is filed under Korean Patent Application No. 95-1573 (1995, 1, 27).

However, the circuit shown in FIG. 1 performs a test while changing an enable or disable state of each flip-flop or each module in a test mode, before each flip-flop or each module performs a change operation. There is a problem in that the clock signal CK must be disabled in order to maintain the same.

2 shows a conventional clock control circuit using a transfer gate, which is comprised of a flip-flop 30 and a transfer gate 32.

This method has two clock signals, one is the system clock signal and the other is the test clock signal. If the output signal Q of the flip-flop is 0, the transfer gate 32 is turned on to output the system clock signal. On the contrary, if the output signal Q of the flip-flop is 1, the transfer gate 32 is Off to not output the system clock signal. Thus, all flip-flops or modules connected to this circuit are controlled to be enabled or disabled in response to this system clock signal. The signal stored in the flip-flop is determined by the input data.

That is, if the input data is 0, the flip-flop 30 outputs zero data in response to the test clock signal to turn on the transmission gate 32 so that the system clock signal is transmitted. If the input data is 1, the flip-flop 30 outputs data of 1 in response to the test clock signal to turn off the transmission gate 32 so that the system clock signal is not transmitted.

However, in the conventional clock control method using a transmission gate, and also in the circuit shown in FIG. 1, the previous state value is maintained when the test is performed while changing the enable or disable of each flip-flop or module. Must be maintained. Therefore, in order to proceed to the next state and perform a test, the test clock signal and the system clock signal should be disabled so that each flip-flop or module maintains the value of the previous state. That is, the circuit shown in FIG. 2 also has a problem in that the test clock signal or the system clock signal must be alternately turned on and off to control the states of flip-flops or modules.

As a result, the circuits shown in FIGS. 1 and 2 have a problem in that the generation of the clock signal must be disabled when performing the test mode, and therefore, there is a problem that the test speed is delayed.

SUMMARY OF THE INVENTION An object of the present invention is to control a clock control circuit which can reduce power consumption and does not need to disable a clock signal, thereby improving test speed.

Another object of the present invention is to provide a clock control system using a clock control circuit for achieving the above object.

The clock control circuit of the present invention for achieving the above object outputs a normal enable signal in a normal mode in response to a test mode signal and a shift mode signal, and outputs a signal of a first state in a clock control mode, and Selection means for outputting a test enable signal in a clocking mode, a flip-flop for storing a test enable control signal in response to a logical multiplication of the shift mode signal and a clock signal and outputting the test enable signal; Transmits an output signal of the selection means in response to the clock signal in the second state, latches the transmitted signal in response to the clock signal in the first state, and outputs the latched signal in response to the clock signal. And clock signal generating means for outputting the clock signal.

A clock control system of the present invention for achieving the above another object is a system having a plurality of blocks in response to each clock signal, each of the plurality of blocks in the normal mode in response to a test mode signal and a shift mode signal Selecting means for outputting a normal enable signal at a time, outputting a signal in a first state in a clock control mode, and outputting a test enable signal at a partial clocking mode, and performing a logical multiplication of the shift mode signal and a clock signal. A flip-flop for storing a clock control data input signal in response to the signal and outputting the signal as the test enable signal, and transmitting an output signal of the selection means in response to the clock signal of the second state, Latching the transmitted signal in response to a clock signal, and latching the latched signal in response to the clock signal It includes a clock control circuit having a clock signal generating means for outputting the system clock signal, in the normal mode to control the clock signal applied to the respective blocks in response to the normal enable signal, in the test mode Inputting and shifting the clock control data input signal by performing the clock control mode as a test enable signal for controlling the respective blocks, and by performing the partial clocking mode to the respective blocks. And controlling a clock signal applied to each of the blocks in response to the stored clock control data input signal.

1 shows a clock control circuit using a latch.

2 shows a clock control circuit using a transfer gate.

3 shows a clock control circuit of the present invention.

4 is a block diagram showing the clock control circuit shown in FIG.

5 is a block diagram of a system using the clock control circuit shown in FIG.

Hereinafter, a clock control circuit and a system using the same will be described with reference to the accompanying drawings.

3 illustrates a clock control circuit of the present invention, which includes an AND gate 40, a flip-flop 42, a multiplexer 44, inverters 46, 48, 52, 56, and transmission gates 50, 54. , And AND gate 58.

The operation of the clock control circuit can be largely divided into a normal operation and a test operation, and the test operation consists of a clock control mode and a partial clocking mode.

The clock signal CK 'is connected to the system clock. The signal NE of the two control signals NE and TE is a normal enable signal, and the signal TE represents a test enable signal, respectively, and is a signal applied in the normal mode and the test mode, respectively.

First, the operation in the normal mode will be described.

As shown in the table, in the normal mode, 1 and X (don't care) are applied as the control signals NE and TE, respectively. At this time, the multiplexer 44 outputs the normal enable signal NE in the normal mode. This signal is transmitted through the transmission gate 50 in response to the low level clock signal CK. This signal is latched and inverted on a latch comprised of inverters 52 and 56 and a transfer gate 54. That is, the latch outputs a high level signal when the normal enable signal NE is low level, and outputs a low level signal when the normal enable signal NE is high level. The AND gate 58 generates the low level clock signal CK 'when the latched signal is at the low level, and clocks the latched signal in response to the clock signal CK when the latched signal is at the high level. It is generated by the signal CK '.

Thus, if you want to operate the flip-flops or modules in the normal mode, apply a low level normal enable signal NE, and if you do not want to operate it, apply a high level normal enable signal NE. .

As described above, by controlling the normal enable signal NE using the multiplexer 44 in the normal mode, it is possible to control the enable or disable of the clock signals entering the flip-flops or modules to reduce unnecessary power consumption. have.

Next, the operation in the test mode will be described. The test mode is divided into a clock control mode and a partial clocking mode as described above.

First, the clock control mode operation will be described.

As shown in Table 1, in the gartting clock control mode, 0 and 1 are applied as the test mode signal and the shift mode signal applied to the multiplexer 44, respectively. At this time, the flip-flop 42 latches the test enable signal TE in response to the AND signal 40 of the high level clock signal CK and the shift mode signal, and outputs the signal TE '. Occurs. The multiplexer 44 selects a value of 1 and outputs the selected value. This signal is transmitted through the transmission gate 50 in response to the low level clock signal CK. In addition, this signal is inverted and latched by a latch composed of inverters 52 and 56 and a transmission gate 54, and a zero signal is passed through the AND gate 58 in response to the high level clock signal CK. Is output. Therefore, in the clock control mode, the value of 1 is latched through the multiplexer 44, and the clock signal CK 'is kept at zero. However, the flip-flop 42 continuously outputs the test clock signal TE as the test clock signal TE '. That is, the clock signal CK 'is maintained at 0 in the clock control mode, and the test clock signal TE is output as the test clock signal TE'. Therefore, the clock control mode maintains the state of the flip-flop or the module responding to the clock signal CK 'by keeping the clock signal CK' at 0, and enables test operation if it is desired to operate in the test mode. To control the enable or disable of a flip-flop or module responding to the clock signal CK 'by applying 0 as the signal TE and not applying the signal as the test enable signal TE. will be.

Finally, the partial clocking mode operation is described as follows.

As shown in the above table, 0 and 0 are respectively applied to the test mode signal and the shift mode signal applied to the multiplexer 44. At this time, the multiplexer 44 outputs the output signal TE 'of the flip-flop 42. This signal is output through the transfer gate 50 in response to the low level clock signal CK. This signal is also latched by a latch composed of inverters 52 and 56 and a transfer gate 54 in response to a high level clock signal CK. The AND gate 58 inverts and outputs the signals latched in the latch in response to the high level clock signal. That is, the partial clocking mode may partially operate any flip-flops or modules by the value input in the clock control mode, or may maintain the previous value. That is, to go to the partial clocking mode, the clock control mode must be passed. If the signal TE 'is 0, the clock signal CK is generated as the clock signal CK'. If the signal TE 'is 1, the clock signal is generated. Set (CK ') to 0.

That is, in the test mode, when the clock control mode is performed and the flip-flop and the module are desired to operate in response to the clock signal CK ', a signal of 0 is applied as the test enable signal. A signal of 1 is applied as the signal. The partial clocking mode is performed to output a signal inverted from the zero signal input in the clock control mode as the clock signal CK 'in response to the clock signal CK, or output a signal of 1 input in the clock control mode. In response to the inverted signal, a zero signal is output as the clock signal CK '.

Therefore, the clock control circuit of the present invention shown in FIG. 3 does not need to disable the clock signal when performing the test mode. That is, the test enable signal is stored by applying the test enable signal for controlling the state of flip-flops or modules for the next test without performing the clock control mode by disabling the clock signal and performing the partial clocking mode. In response to the signal, the clock signal CK 'is set to zero and the clock signal CK is output as the clock signal CK'.

4 is a block diagram illustrating the clock control circuit of the present invention shown in FIG. 3, and includes a test mode and a shift mode signal input terminal for determining a mode, a normal mode enable signal NE, and a test mode enable signal. Normal mode and test mode enable signal input terminal for inputting (TE), clock signal input terminal for inputting clock signal CK, and clock signal output for outputting clock signal CK ' It consists of an output terminal for outputting the enable signal TE '.

5 is a block diagram of a clock control system for controlling a clock signal applied to N blocks in one system 100 using the clock control circuit of the present invention. 70- (M-1), 70-M, 70- (M + 1), ... 70- (N-1), 70-N), and clock signals input to each of N blocks Clock control circuits 80-1, ... 80- (M-1), 80-M, 80- (M + 1), .... 80- (N-1), 80 -N). In FIG. 5, each block represents a flip-flop or module described above.

First, the normal mode operation will be described.

In the normal mode, 1 and X are applied as test mode and shift mode signals, respectively, and the clock control circuits 80-1, 80- (M-1), 80-M, 80- (M + 1 By controlling the normal enable signal NE applied to 80- (N-1) and 80-N, respectively, N blocks 70-1, .... 70- (M -1), 70-M, 70- (M + 1), .... The clock signal CK 'input to 70- (N-1), 70-N can be enabled or disabled. . Although the method for applying the normal enable signal NE has not been described in detail, the normal enable signal NE can be applied in various ways. For example, if all blocks must be enabled in normal mode, then one low-level signal from the outside is applied to the N clock control circuits, and in 80-1 to 80-M in normal mode. If blocks up to are enabled and blocks from 80- (M + 1) to 80-N should be disabled, the low level signal applied from the outside is normal to the blocks of blocks 80-1 to 80-M. The signal is applied to the enable terminal NE, and an inverted signal is applied to the blocks from 80- (M + 1) to 80-N. Accordingly, power consumption can be reduced by enabling only blocks that require operation among N blocks, and disabling operations of blocks that do not require operation.

The operation in the test mode is as follows.

First, 0 and 1 are respectively applied as the test mode signal and the shift mode signal in the clock control mode, and the clock control data input signal CDI is provided through the test clock signal TE input terminal of the clock control circuit 80-1. ; clock control data input). This signal is shifted to the next clock control circuit 80-2. Such a shift operation is performed through the clock control circuits to be output as a clock control data output signal CDO through the test clock signal output terminal TE ′ of the clock control circuit 80 -N. That is, in the clock control mode, the clock control circuits 80-1, 80- (M-1), 80-M, 80- (M + 1), .... 80- (N-1 ), 80-N) will perform the shifting operation. Thus, a value of 0 is entered in blocks that want to operate in a test mode, and a value of 1 is entered in blocks that do not want to operate.

In the partial clocking mode, 0 and 0 are applied as the test mode signal and the shift mode signal, respectively. In this mode, when the clock signal CK is normally input, the clock control circuits 80-1, 80- (M-1), 80-M, 80- (M + 1), ... 80- (N-1) and 80-N latch the test clock signal TE 'selected by the respective multiplexer 44 to latch the plurality of blocks 70-1, ..., 70- (M -1), 70-M, 70- (M + 1), .... 70- (N-1), 70-N) are applied to each clock signal input terminal. That is, in the partial clocking mode, each block may or may not be operated by the test enable signal TE ′ stored in the clock control mode. That is, if the test enable signal input in the clock control mode is 0, the clock signal CK is applied as the clock signal CK 'and blocks are operated. If 1, the signal is applied to the clock signal CK'. The blocks will not work. As described above, in order to perform the partial clocking mode, the clock control mode must be passed.

Therefore, the system using the clock control circuit of the present invention can perform the clock control mode to control the enable or disable of the respective blocks without having to disable the clock signal when the test mode is performed, and to increase the test speed. Can be improved.

Therefore, the clock control circuit and the system using the same of the present invention can reduce power consumption by controlling the normal enable signal in the normal mode to disable the operation of blocks that do not require operation.

In the test mode, the test is alternately performed from the clock control mode to the partial clocking mode or from the partial clocking mode to the clock control mode. In this case, the test speed may be improved since the clock signal does not need to be disabled.

Claims (8)

In response to the test mode signal and the shift mode signal, a normal enable signal is output in the normal mode, a first state signal is output in the clock control mode, and a test enable signal is output in the partial clocking mode. Means 44; Flip-flops (40, 42) for storing a test enable control signal and outputting the test enable control signal in response to a logical multiplication of the shift mode signal and a clock signal; And transmitting an output signal of the selecting means in response to the clock signal in the second state, latching the transmitted signal in response to the clock signal in the first state, and receiving the latched signal in response to the clock signal. And a clock signal generating means (50, 52, 54, 58) for outputting the system clock signal. 2. The apparatus of claim 1, wherein the clock signal generating means comprises: first transmitting means (50) for transmitting an output signal of the selecting means in response to the clock signal in the second state; Latches (52, 54, 56) for inverting and latching an output signal of the first transmission means in response to the clock signal in the first state; And an AND gate (58) for outputting the clock signal as a system clock signal in response to the signal latched in the latch. The clock control circuit of claim 1, wherein the clock control mode and the partial clocking mode are sequentially performed in a test mode. 2. The apparatus of claim 1, wherein the latch comprises: a first inverter (52) for inverting an output signal of the first transfer means and applying it to the clock signal generation means; A second inverter 56 for inverting the output signal of the first inverter; And second transmission means (54) for outputting the output signal of the second inverter to the first inverter in response to the clock signal of the first state. In a system having a plurality of blocks corresponding to each clock signal, each of the plurality of blocks outputs a normal enable signal in a normal mode in response to a test mode signal and a shift mode signal, and in a clock control mode. Selecting means (44) for outputting a signal in a first state and outputting a test enable signal in a partial clocking mode; Flip-flops (40, 42) for storing a clock control data input signal in response to a logical multiplication of the shift mode signal and the clock signal, and outputting the clock control data input signal as the test enable signal; And transmitting an output signal of the selecting means in response to the clock signal in the second state, latching the transmitted signal in response to the clock signal in the first state, and receiving the latched signal in response to the clock signal. And a clock control circuit having clock signal generating means (50, 52, 54, 56, 58) for outputting as a system clock signal, which is applied to each of the blocks in response to the normal enable signal in the normal mode. The clock signal is controlled, and in the test mode, the clock control data input signal is input and shifted by the clock control mode, and the test clock signal is applied as a test enable signal for controlling the respective blocks. A clock is applied to each of the blocks in response to a clock control data input signal stored in each of the blocks by performing a mode. A system for controlling a ruck signal. 6. The apparatus of claim 5, wherein the clock signal generating means comprises: first transmitting means (50) for transmitting an output signal of the selecting means in response to the clock signal in the second state; Latches (52, 54, 56) for inverting and latching an output signal of the first transmission means in response to the clock signal in the first state; And an AND gate 58 for outputting the clock signal as a system clock signal in response to the signal latched in the latch. 6. The system of claim 5, wherein the clock control mode and the partial clocking mode are performed sequentially in a test mode. 6. The apparatus of claim 5, wherein the latch comprises: a first inverter (52) for inverting the output signal of the first transfer means and applying it to the clock signal generation means; A second inverter 56 for inverting the output signal of the first inverter; And second transmission means (54) for outputting the output signal of the second inverter to the first inverter in response to the clock signal of the first state.