SU1394459A1 - Multimodule switching system for asynchronous digital signals - Google Patents

Abstract

The invention relates to the field of telecommunications. The purpose of the invention is to simplify the device by means of group processing of service signals. The device contains M modules 1, each of which consists of 1 input transducers of code 2, 1 blocks 3 time latching, block 4 memory of addresses of shaper 5 time code, block 6 of switching, 1 output transducers of code 7. Bi-pulse signals transmitted by incoming lines The communications are switched into outgoing conversions to binary code. However, control and interworking overhead signals, as well as test control signals transmitted via communication lines between adjacent station control devices, are necessary. convert to binary code before transmitting to the control device, laziness of its station, since through communication, information is transmitted in a bi-pulse code. To implement the conversion function, the blocks newly introduced into the device are intended: two. adder Y, M, block 9 of time codes, block 10 of constants, block 12 of memory, block 13 of signal conversion and a register. 2 Il. i (L

Description

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The invention relates to telecommunications and can be used in digital switching systems.

The purpose of the invention is to simplify the device by means of group processing of service signals.

FIG. t is an electrical block diagram of a multi-module switching system for asynchronous digital signals; in fig. 2 is a structural electrical circuit of a signal conversion unit.

Multi-modular switching system

To the bot of all the blocks of its module 1. In order for the drivers 5 of all M modules 1 of the device to operate synchronously, the same sequence of pulses f from the station generator is fed to them. All time code generators 5 are zeroed with the same pulses.

Using the address A and the synchronization signals of the time code generator 5, the information from blocks 3 and 4 is cyclically read out and output to the switching blocks 6 of all modules 1

The theme for asynchronous digital signal is 5 devices. Each block memory cell contains M modules 1, each of which consists of 1 input transducer 2 codes, 1 block 3 latch time, block 4 address memory.

Shaper 5 time code, block 6 20 transmission in parallel code code

switching, 1 output converters 7 code, the first adder 8,. a block 9 of time codes, a block of 10 constants, a second adder 11, a block 12 of memory, a block 13 of signal conversion and a register 14.

The conversion unit 13 (the signal contains the elements OR 13-1, NOT 13-2 and AND 13-3 and the trigger 13-4.

A multi-module switching system for asynchronous digital signals operates as follows.

Input code converters receive switched bi-pulse signals from incoming lines. At the same time, in accordance with the operation of the converters, if the polarity of the signal in the i-th line changes, the output signal p 1 is produced, otherwise / 0. With the help of signal p, a new code of the signal ( information And) incoming line. The new signal code is recorded in the memory cell of the time-latching unit 3 with the address A from the driver 5 of the time code. The same time memory cell records the time code from the shaper 5 of the time code, which captures the moment of arrival of the signal in the device. Each input line of the input code converter 2 has its own memory location in the corresponding time latching unit 3. The time code generator 5 is an electronic counter that generates a time code, the address A of the incoming and outgoing lines being serviced, and the signals synchronized

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the signal, its code, time from the block and the address of the outgoing communication line to which this information belongs, block 4.

In block 6, the walking address of the mod 2 is monitored, and then by comparing it with the address of its module 1, the incoming information is determined by the given model. If the information belongs to the given module, then the signal about 1 is generated in the block.

The code of the signal and the time code from block 6, accompanied by the address of the outgoing line to which this information belongs, goes to the inputs of blocks 7.

Thus, bi-pulse signals transmitted over the incoming lines of communication are switched into the initial conversions into a binary code. However, one of the following control and interaction signals, as well as test control signals transmitted via communication lines between controllers of adjacent stations, must first be created in binary code, transmitted to the station control device, as transmitted in bi-pulse code. In order to perform the function of converting information from the bi-pulse code into binary code, newly introduced blocks are intended. These blocks work as follows.

The time code GT; which is called the current time code (TKB) is fed to the input A 1 of the first sum 8 and block 9 of the code BpeMCfif in the block

Codes 3 and 4 are read at a certain time interval of the group path of the GT, - (, 2, .. .1) device. In this interval,

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signal, its code, time from block 3 and the address of the outgoing line of communication to which this information belongs, from block 4.

In block 6, the outgoing line address mod 2 is monitored, and then by comparing it with the address of its module 1, it is determined that the incoming information belongs to this module. If the information belongs to this module, then the signal about 1 is generated in the block.

The code of the signal and the time code from block 6, accompanied by the address of the outgoing line to which this information belongs, is fed to the inputs of blocks 7.

Thus, bi-pulse signals transmitted over incoming lines of communication are switched to the original ones without conversion to binary code. However, control and interaction follow-up signals, as well as test control signals transmitted via communication lines between adjacent station control devices, need to be converted to binary code before being transmitted to the control device of their station, as the information is transmitted in bi-pulse mode. code. The blocks introduced into the device are intended to perform the function of converting information from a bi-pulse code into a binary one. These blocks work as follows.

The time code GT; which is called the current time code (TKB) is input to input 1 of the first adder 8 and block 9 of the BpeMCfif code of the cf blocks

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31394459

3 fixing time. Block 9 of time codes has ml of memory cells, i.e. For each incoming link serviced by device module 1, there is a memory cell, the number of which corresponds to the line number. Block

The 9 time codes at address A of the input line provide two read and write operations. At first, this block at address A, coming from the generator 5 of the time code, reads the previous time code (PKV) arriving at the first adder 8, and then records the TKB from the time-fixing blocks 3 into the same memory cell. Thus, in one GT operation interval, the time codes are read and written in block 9.

The first adder 8 receives the TKB In the forward code and the PKV in the reverse code. The first adder 8 performs the operation of adding TKB + PKV P.

10 constants. Block 10 is constructed similarly to block 9, i.e. It has ml memory cells attached to incoming lines. The constants from the station control device (CLC) are recorded in the memory cell of block 10.

The write and read operations in block 10 of constants are performed similarly to block 9 of time codes at address A of shaper 5 of the time code.

The second adder 11 completes the addition operation, i.e. to the result of P, obtained in the first adder 8, is added the inverse code of the constant K from the block 10 of the constants. The magnitude of the 3N is a sign of the addition of the values of P + K. In this case, the mantissa after addition (P + K) is not used. Using the obtained character, the signal is determined by the signal d, which is fed to the inputs of the memory unit 12 and the signal conversion unit 13, and provides the conversion of signals from a bi-pulse code to a binary one. The signal o (MN, t, e. - the signal c / is received in the second adder 11 after inverting (passing through the NOT circuit) the received MN sign,

The signal (A- is fed to the input of memory block 12. This block is a single-bit semiconductor memory having a number of memory cells ml, t, e.

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lines each device module 1. The numbers of the memory cells of block 12 coincide with the numbers of lines. The recording and scoring operations in block 12 are performed for each time interval of the GT operation, similarly to the blocks of time codes 9 and constants 10. During the read operation, the address from the form A is formed. The time code body 5 is outputted from the memory unit 2 to the input of the signal conversion unit 13 of the previous value of the signal o (and during the recording operation the new signal d from the second totalizer 1 is recorded in the same memory cell).

The flf signal from the memory unit 12 is recorded on the trigger 13-4 (Fig. 2) of the signal conversion unit 13. The signal o (from the second adder П goes to the circuit AND 13-3 and through the circuit NOT 13-2 to the circuit OR 13-1. The signal about / from the output of the trigger 13-4 also goes to circuit AND 13-3. If signals about / 1 and 1, and also, if (x O, then, from the outputs, circuits AND 13-3 and NOT 13-2, respectively, to the inputs OR 13-1, signals equal to one are received, which ensure the generation of the signal oi 1 coming from information And (by signal o /) to register 14.-Signals o (1 and o (I means that two additional signals of 416 ISS each were transmitted along the i-th line, i.e. binary 1, which should be per The signal means that a signal 2 is transmitted along the i-th input line 2, equal to 832 μs, t, e, received a new O.

Information and in binary code with the help of the signal w 1 is recorded on register 14 together with address A (from the driver 5) of the incoming line. Register 4 is controlled by the signal W 1. The binary cut code and the address of the input line from register 14 are transmitted to the station control device,

Ula Invention Form

A multi-module switching system for asynchronous digital signals, consisting of M modules, each short-circuit which contains 1 serially connected input code converters and 1 time latch blocks.

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serially connected time code generator and address storage unit, time code generator output connected to the second input of each time latch block, switching unit and 1 output code converters, switching unit output connected to information input of each of 1 output code converter, control The input input of each of which is connected to the control input of the switching unit, the information inputs of the switching unit of each and the modules are connected with the corresponding bits to the outputs of the fixing units

time and an address memory block, characterized in that, in order to simplify the system by means of group processing of service signals, 20 serially connected first and second adders, a block of constants, the output of which is connected to the second input of the second adder, are entered. memory block

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and a signal conversion unit, the first inputs of which are connected to the output of the second adder, a register, the output of which is the output of service signals, and the first input connected to the output of the signal conversion unit, the second input of which is connected to the output of the memory unit, the second input of which is connected to the first the input of the block of constants, the output of the time code generator, the control input of the switching unit, the time code block whose output is connected to the first input of the first adder, the second input of which is connected to the first input of the block time codes and outputs of the time latching units; the second input of the constant block is connected to the second input of the address memory block; the output of the time code generator is connected to the control input of each of the input converters and the second input of the time code block.

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Claims (1)

Claim A multi-module switching system for asynchronous digital signals, consisting of M modules, each of which contains 1 series-connected input code converters and 1 time-fixing blocks, series-connected time code shaper and address memory block, the output of the time code shaper is connected to the second input of each of the blocks time fixation, switching unit AND 1 output code converters, the output of the switching unit is connected to the information input of each of 1 output code converters, the control input of each of which is connected to the control input of the switching unit, the information inputs of the switching unit of each module are connected by the corresponding bits to the outputs of the time-fixing units and the address memory unit, characterized in that, in order to simplify the system by group processing of service signals, series-connected the first and second adders, a block of constants, the output of which is connected to the second input of the second adder, a memory block and a signal conversion unit, the first inputs of which are are single with the output of the second adder, the register, the output of which is the output of the service signals, and the first input is connected to the output of the signal conversion unit, the second input of which is connected to the output of the memory unit, the second input of which is connected to the first input of the constant block, the output of the time code generator. the control input of the switching unit, a time code block whose output is connected to the first input of the first adder, the second input of which is connected to the first input of the time code block and the outputs of the time fixing blocks, the second input d constants unit is connected to the second input of memory block addresses, the time code generator output is connected to the control input of each of the input transducer and the second input unit time code.