SU1285616A1 - Multimodule switching system - Google Patents

Description

112

The invention relates to communication technology and can be used in digital switching systems.

The purpose of the invention is to increase the noise immunity during transients.

The drawing shows an electrical structural diagram of a multi-module switching system.

A multimodular switching system contains L modules 1 ,, ..., 1, each of which contains / 1 input converters 2i, ..., 2 codes, t. Blocks 3., ..., 3 timestamps, t blocks 4, ... 4j. Line output, block 5 of the address memory, first time code generator 6, second time code generator 7, t × M input registers 1x (8 |, ...., 8), t switches 9j, ..., 9, t х p asynchronous spatial switches fx (10, ..., 10,), t output registers 11, ..., 11 (, counter 12, t blocks 13, ... , 1ZE information distribution

The multimodular switching system works as follows.

Input converters 2, ..., 2 (codes receive switched signals, determine the polarity change of signals and encode the leading edge of signals with code 1, and the rear edge - O. Input converters 2j, ..., 2 (code served by m communication lines. The code of the switched signals (1 and O) from the input converters 2, ... 2j of the code is issued further, accompanied by the addresses of the incoming communication lines, on which the front or rear lines of the switched signals are received, in blocks 3. , ... 3 (fixing the time, which also receives the time code from the first driver 6 code time The 3,, ... 3 {time-fixing blocks write the signal code and the time code into their memory cells. Each input line of the module 1, ..., 1j has its memory cell in the 3J blocks, ..., 3f timestamping The time code recorded in the g cells of blocks 3, ..., 3 (the time fixation records the moments of arrival of the signal code into these blocks. Time code generator 6 is an electronic counter, which Fabatura time code and signals that synchronize the work of all the blocks of its module 1, ..., 1i, in order for the first and second form

62

The worlds 6 and 7 of the time code of all L modules of the switching system worked synchronously, they are fed the same sequence of pulses fo from the generator station.

Using the generator clock sync pulses, information from blocks 3j, ..., 3j. fixing the time and block 5 of the memory of addresses is cyclically read out and output to the corresponding input registers 8, ..., 8 of all modules L of the switching system. Each cell of the memory of the 3 3 time latch blocks and the 5 address memory block is read in a certain time interval of the group path of its switching system module 1, ..., 1. In this interval, the signal code and the time code are also transmitted from block 3.,., .J of fixing the time and the address of the outgoing line of the link Zi, which owns this information, from

block 5 - addresses to the input registers 8, ..., 8 of the switching center.

In order to increase the noise immunity of the switching circuits of the system, information is received at the input registers 8., .. at a definite moment of time determined by the strobe pulse t, which is in the middle of the time interval for transmitting information. The information recorded in the input registers 8i, ..., 8 by means of the switches 9, ..., and blocks 13j, .. ,, 13 of the distribution of information is transmitted to the asynchronous spatial switches 10 ,, ..., 10 the correctness of the information and the address in switches 9, ..., 9 {pre-tested. If the information or the address is transmitted with an error, then the control circuit in the switches 9j, ..., 9j blocks the reception of information that is transmitted twice, and therefore it is possible to deny its reception once to the asynchronous spatial switches IO, ..., fbh. From the switches 9 j, ..., 9 {the information is transmitted to the asynchronous spatial switches 10j, ..., 10 and to the blocks 13, ..., 13 (. Information distributions, and only the higher bits of the transmitted address and test signal 8 produced by switches 9, ..., 9 {. These bits define the number (address) of the module

317. 1,, i., 1i, and the block number A, ..., 4 {outgoing lines. Blocks 13, ..., 13 (information distributions have comparison and decryption elements, the comparison elements determining the belonging of the received information to this module 1.IL and permitting

decoding the address that is output to the corresponding asynchronous spatial switch 10.,. ,., 10 that allows the reception of information received from the switch 9, ..., 9j. Each of n asynchronous spatial switches. 10, ..., 10, serving one of the outgoing lines 4, ..., 4f, receives information from the corresponding switches 9j, ..., 9j and writes it to its memory cells. In this case, each outgoing line of communication has its own memory location in. each of the n asynchronous spatial switches ". .10j, ..., 10. The numbers of memory cells and outgoing lines are the same. With the help of asynchronous spatial switches 10j (South) it is provided

independent in time and parallel operation of switches 9i, ..., 9f. The asynchronous spatial switches 10i, ..., 10n from the switches 9;, ..., 9 {receive the information and the address of the communication line of the corresponding block 4, ..., 4g of outgoing lines. Information is read from asynchronous spatial switches 10, ..., 1 simultaneously and cyclically using the address coming from counter 12. The read information comes along with the address to output register 11j, ..., 11f. The code of the switched signal, the time code and the address of the outgoing communication line to which this information belongs are sent from the output registers 11i, ..., 11e to the inputs of the blocks Vj, ..., 4f of the outgoing lines, where the code of the switched one is compared. the signal with the status code of the outgoing line, using the incoming address from the output register 11j, ..., 11j. If these codes are the same, then the recording of the incoming information is blocked, and information is read instead of the recording. If the codes differ from each other, the write operation is not blocked. Recording information in the cells of the block A, ... 4j of the outgoing lines is performed

five

fi

0 5 0

five

0

0

five

0

five

164

the simultaneous output of this information, as well as the address of the cell, which is read cyclically using the address received from the second generator 7 of the time code. The numbers of the memory cells of blocks 4, ..., 4 (outgoing lines and outgoing lines are the same. The output of the signal code with the corresponding outgoing communication lines is made after comparing the time code accompanying the information with the time code from the second driver 7 time code.

The proposed multi-module switching system makes it possible to increase the noise immunity of the switching circuits of the system.

Claims (1)

Invention Formula A multimodular switching system containing L modules, each of which contains f input transducers, code breakers, t time fixation blocks, 1 output line blocks, an address memory block, first and second time code drivers, and the output of each input transform. , the code bodies are connected to the first input of the corresponding time latching unit, the second inputs f of the time latching units are connected to the first input of the address storage unit and the output of the first time code generator, the outputs t of the time latching unit are combined, and the t inputs of the outgoing line blocks are connected to the output of the second time code generator, which means that, in order to increase the noise immunity during transients, t x M input registers, T switches, t information distribution blocks are entered into each module xn asynchronous spatial switches, t output registers, the output of each of which is connected to the second input ; of the corresponding unit, the lines and the counter, the output of which is connected to the first tun inputs of asynchronous spatial switches, the first output of each of the n asynchronous spatial switches is connected to the corresponding input of the corresponding output register, the second input and the second output of each of the n asynchronous spatial switches are connected respectively with. The second output and the second input is each 12856166 From the p asynchronous spatial input of the corresponding block of switch switches, the outputs M of the input data divisions corresponding to the registers are connected to the corresponding cadts outputs of t blocks by the distribution inputs of the corresponding information communication connected to the quadtator, the first output of each of the k-5 th inputs of the same name asynchronous connectors is connected to the third inputs of spatial switches, of the same name I asynchronous space-outputs of the memory block of addresses and blocks switches, the second time out- put is connected to the corresponding one of the I switches connected to the main inputs of the input registers.