SU1700762A1 - Asynchronous digital signals time switching device - Google Patents

Abstract

The invention relates to digital communication and can be used in electronic switching systems. The goal is to improve the accuracy of receiving and switching signals by eliminating the possibility of their loss. The device contains an overhead signal accumulation unit 1, a primary memory block 2, a switching unit and an overhead signal memory unit 3, two registers 4 and 8, a secondary memory block 5, a comparison unit 6, a multiplexer 7, a signal distribution unit 9. Block 1 has memory cells. Each incoming link has its own PAM position and its memory cell in block 1. Block 1 selects overhead information from the general information flow in the AIM. The service signals that need to be output to the outgoing lines of communication are recorded in the cells of block 3. The signals from block 3 are read and output to block 2 are performed cyclically and bit by bit. 1 il. about 8 (L

Description

s & y

This invention relates to digital communications and can be used in electronic switching systems.

The purpose of the invention is to improve the accuracy of receiving and switching signals at the expense of eliminating their loss.

The drawing shows a structural electrical circuit of the device for time switching of asynchronous digital signals.

The temporal switching device for asynchronous digital signals comprises an overhead signal accumulation unit 1, a primary memory block 2, a switching unit and a signal signal storage unit 3, the first register 4, and a block 5 of the second one. memory unit, comparison unit 6, multiplexer 7, second register 8, signal distribution unit 9.

The device is a temporary switching asynchronous digital signals works as follows.

On the information and information highway (AIM), the parallel code receives information accompanied by the addresses (numbers) of outgoing communication lines to which this information belongs. The information is the edge codes of the switched signals i and the time code defining the times of signal output to the outgoing communication lines.

In this case, code 1 encodes the leading edge of a single (1) signal, and code O encodes the falling edge.

Unit 2 receives words and, using the address of the communication lines, writes information into the corresponding cells of the i memory. In this case, each outgoing communication has its own cell in block 2. The numbers of communication lines and memory cells are the same.

The service signals arriving at the inputs of the switching system from other stations of the communication network are transmitted to block 1, which has memory slots. Each incoming communication line of the switching system has its own PIM time position and its memory cell in storage unit 1. signal The numbers of the time positions of the PAM, the memory cells of block 1 and the incoming links coincide. In the memory cells of block 1, a bit accumulation of service signals is made. Unit 1 for the time equal to one time position of the AIM performs the operation of reading and writing the same service

signal from the i-th memory cell. The block selects overhead information from the general information flow in the PIM. and issues service signals along with the addresses of the incoming communication lines through which the signals are received.

Service signals that need to be issued to outgoing lines of communication are recorded in the memory cell of block 3. Service signals are accompanied by addresses of outgoing lines that correspond to the addresses of memory cells of block 3. Together with service signals in the memory cells of block 3 The signal Di 1 is also recorded. The signals from block 3 are read out and they are output to block 2 cyclically and bitwise. In one cycle of operation of block 3, one bit is issued for each of the serviced outgoing communication lines. In block 2, for the i-th outgoing line, one service signal bit is output from block 3 and a signal about 1, which prohibits the writing of the service signal bit to the i-th memory cell of the information block 2 from the PIM and provides the same memory cell from block 3 and zero - c time code. The issuance of service signals to outgoing communication lines is performed cyclically. To stop the issuance of service signals to outgoing lines, the signal Sb 0 is entered in the corresponding memory cells of block 3.

Information from the memory cells of block 2 is read cyclically and outputted via the first register 4 to the input of block 5 o. The information bit from the i-th memory cell of block 2 is also output to block 6, to which the information bit from the i-th outgoing lines through multiplexer 7, i.e. that bit of information that was previously issued on the i-th line and recorded in block 9. If these bits were the same, for example, 1 or O, block 6 generates a signal / Ь 1, which prohibits writing new information to the i-th memory cell unit 5, since the previous bit of information (opposite polarity) in this case has not yet been issued from block 5 to the outgoing line until the previous bit is issued from the i-th memory cell of block 5 to the i-th outgoing line, the signal prohibits the recording of new information in

this cell of memory. Thus, loss of information bits is avoided. After issuing this bit signal fO. In this case, a new signal is recorded from the i-th cell of block 2 to the i-th cell of block 5 of the secondary memory.

Block 9 cyclically reads information from the cells of block 5 and compares the time code KB, which accompanies the information from block 5 with the time code KB produced by block 9. If these time codes are the same, then block 9 determines the number of the outgoing communication line into which it is necessary to give the received bit of information. If the KB and KB codes are not equal, then using the signal Y 0, the next bit of information received from block 5 through the second register 8 (Fig. 1) is prohibited.

Claims (1)

Formula of inventions A temporary switching device for asynchronous digital signals, containing an overhead signal accumulation unit, the input of which is connected to the first input of the primary storage unit, the second and third inputs of which are connected respectively to the first and second outputs of the switching unit and the overhead signal storage, and also distribution of signals, characterized in that, in order to improve the accuracy of receiving and switching signals by eliminating the possibility of their loss, serially connected first register, secondary memory block and the second register, as well as serially-connected multiplexer and comparison unit, the output of which is connected to the second input of the secondary memory unit, the third input of which is connected to the second output of the first register and the second input of the comparison unit, and the output of the primary memory unit, and the output of the second register is connected to the input of the signal distribution unit, the first output of which is connected to the second input of the signal accumulation unit, the fourth input of the secondary memory unit, the first input of the multiplex eksora, input switching unit and memory overhead and fourth input primary memory unit, and an output signal distributing unit connected to a second input of the multiplexer.