SU1304024A1 - Device for controlling connection with bus - Google Patents

Abstract

The invention relates to computing and is intended for use in computing systems with a backbone information exchange structure. The purpose of the invention is to increase speed. The device contains a trigger 1, element AND 2, element OR 6, counter 3, memory block 4, register 5, multiplexer 7. The device provides matrix organization of connecting subscribers to the trunk, which reduces the transition time from mode to mode and connecting subscribers to highway. 1 il. 1 tab. S CO about 4: About you NU

Description

The invention relates to computing and is intended for use in computing systems with a backbone information exchange structure.

The aim of the invention is to improve the speed of the device.

The drawing shows the structure. Signals. A request from subscribers is received at inputs 10 and at a fixed state of counter 3, a certain cell from block 4 is selected, in which 1 is programmed only in

roties

; on the scheme of the proposed device.

The device for controlling the connection tO of one of the bits to :, corresponding to the trunk, contains a trigger of a combination of signals at input 10 devices - 1, element AND 2, counter 3, memory block 4, register 5, element OR 6, multiplexer 7, clock input 8, signal input 9, group of request inputs -5 of block 3, depending on combinations 10, group of response inputs 11, groups of signals. The query is given in the table.

One of the options for filling the cells

000000001 000000010 00000001 1 0000

Fixed state counter 3. Priority request 2

Dynamic distribution of priorities, Equitable distribution

Dynamic allocation of priorities. Higher priority request 3

ny information codes 12, a group of signal outputs 13.

The device works as follows.

Signals A request from subscribers is received at inputs 10 and, at a fixed state of counter 3, a certain cell is selected from block 4, in which 1 is programmed only in

roties

one of the combination of block 3 in signals

ohm from bit to: corresponding to the binarization of the signals at input 10 of unit 3, depending on the combinations of stocks. The query is given in the table.

One of the options for filling the cells

0000001 0000010 0000001

0000001

0000001

0000001 0000010

0000010

0000010 0000001 0000010 0000100 0001000

0000000

0000001 0000100 000001 about 0000100

1001111-1 10111111 11011111

00011111 00111111

01011111

thirty

35

Thus, at the outputs of block 4, the logical unit appears at one of the bits and at this clock frequency arriving at input 8 will be overwritten in register 5. These signals come from the device outputs 12 to the subscribers, allowing the output at this clock frequency on the line to the corresponding subscriber.

The receiver of information determines its access to the address provided by the source of information. After rewriting instructions from the trunk to the internal registers, the subscriber receives a signal Reception is finished, which is fed to the device inputs 11, and then from the output of the OR 6 element is fed to the input of the multiplexer 7, to the address input of which the information source code has already been sent from register 5.

From one of the outputs 13 multiplex-; g, a signal, the transmission is completed, goes to the subscriber, signaling the completion of the connection cycle to the trunk for this source of information, which removes the request signal, and at the same time a new device operation cycle begins.

With a new combination of signals, the query is looking for a new source of information, etc. If the source issued "not all the information, the Request signal is not removed and the trunk remains connected to this source until all exchanges of this source have been completed.

0001000 0000100 0010000

0000100

1 о. 9 о о о о

0000100

0

five

with

; y d

or until the appearance of a higher priority (according to the table) signal Query.

To exclude the possibility of a line being occupied by one source for a long time, in particular, to control this possibility and to change the priorities of information sources, after their service, several options of control codes (see the table) were programmed in block 4, but with a different distribution priorities. The choice of one or another variant is made by the address inputs of block 4 connected to the outputs of counter 3, the state change of which is performed every clock cycle, i.e. after the completion of the next exchange on the highway.

The control of the clock frequency input to the input of the counter 3 and the register 5 is carried out using the trigger 1 for storing the indication of the transfer of the array of information.

If the input of the information source receives a signal from the array transfer, the trigger 1 is set to one and closes the frequency input through the AND 2 element to the synchronous inputs of counter 3 and register 5, while re. Ister 5 will save the signal for the previously selected source for as long as the source does not remove the signal from input 9.

Reset trigger 1 and thus permission to change the state of the register

country 5 and the choice of .variant in block 4 is carried out by signals from inputs 11 through the element OR 6.

Claims (1)

Invention Formula A device for controlling the connection to the trunk, which contains a counter and a register, the first group of outputs of the register is a group of information outputs of the device, characterized in that, in order to improve speed, the AND element, the trigger, the memory block, the OR element and multiplexer, a single trigger input is connected to the signal input of the device, the inverse trigger output is connected to the first input AND, the inputs of the OR element are connected Editor M. Bandura Order 1312/49 Compiler G, Ponomareva Tehred M. Khodanich CorrectorN. King Circulation 673 Subscription VNISh State Committee of the USSR for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, st. Project, 4 with the device response input group, the output of the OR element is connected to the zero input of the trigger and the multiplexer information input, the output group of which is the device signal output group, the multiplexer address input group is connected to the second register output group, the input group of which is connected to the outputs of the n unit ti, the first group of address inputs of which is connected to the outputs of the counter, the second group of address inputs of the memory unit is connected to the group of request inputs of the device, the clock input of the device and is connected to the second input of the AND gate, whose output is connected to the counting input of the counter and the clock input of the register.