SU1305700A1 - Interface for linking the using equipment with digital computer - Google Patents

Abstract

The invention relates to digital computing and can be used in data exchange systems between computers and various subscriber devices. The aim of the invention is to increase the capacity of the device. The device contains registers 1, 6, 16 shift, decoder 2, working register 5, elements OR 3 and 32, elements AND 4,9-15,30 and 31, triggers 18,26-29, shaper 8 pulses, element HE 17, counters 19, 20 cycles, multiplexers 7 groups. The device allows to reduce the time of information exchange between the computer and subscribers by reducing the address part of the code parcel from the digital computer in the case of only receiving or issuing information. 1 il. 2 / (L SO about 13

Description

The invention relates to computing, in particular to devices for interfacing subscribers with a digital computer, and can be used in data exchange systems.

The aim of the invention is to increase the capacity of the device.

The drawing shows the functional diagram of the device.

The device contains the first register 1 shift, the decoder 2, the first element OR 3, the first element AND 4, the working register 5, the second register 6 shift, multiplexer 7 group, shaper 8 pulses, the second 9, sixth 10, seventh 11, eighth 12, nine 13th, third 14 and fourth 15 And elements, third shift register 16, NOT 17 element, first trigger 18, second 19 and first 20 clock counters, information input 21 and output 22 communication with digital computers, groups of information inputs. OOD 23, address output 24, groups of information outputs 25, fourth 26, fifth of 27, second 28 and third 29 triggers, ten 30 and Fifth 31 elements And, the second element OR 32, the first 33 and the second 34 bus entry task

device mode. Registers 1 and 16 are used to receive consecutive codes of the subscriber-receiver address and subscriber-source information, respectively. The number of register bits is determined by the size of the address part of the package necessary to encode the address of the subscriber-receiver (subscriber-source).

Register 6 is used to receive a parallel code for the information of the source subscriber and to issue it with a sequential code; the number of bits of the register is determined by the size of the information subscription of the subscriber-source

point, and registers 1 and 16 - for 45- unit state.

ema serial codes of the address of the subscriber-receiver and the subscriber-source, respectively.

The working register 5 serves to receive the serial code of the information parcel and to issue it in parallel to the receiving subscriber, the number of register bits is determined by the size of the information part of the register received from the digital subscriber to the receiving subscriber. 55 address part of the dressing, pass through

The decoder 2 serves to convert AND 13, sets the trigger of the binary codes of the addresses of the subscriber 18 to the one state, the signal from the information receivers of information in the output position of which produces in the register code 5 of the receiver 5

-S

0

0

0

Counter 19 clocks is used to count the bits of the address part of the code parcel from a digital computer.

The 20 clock counter is used to count the bits of the information part of the code parcel.

Information output 22 is a line through which information from a device is transmitted from a digital computer from a device.

Information input 21 is a line through which a code message enters the device.

The group of inputs 23 represents some 5 lines, the number of groups of which is equal to the size of the information part of the code parcel, the number of lines in the group is equal to the number of source subscribers.

Address output 24 is a set of lines, the number of which is equal to the number of subscribers receiving information.

The device works as follows.

When the control signal is sent only via bus 33, the device is configured to receive information from the digital computers to the receiving subscribers, and when the control signal is given only via the bus 34, the device is configured to receive information from the digital subscribers to the source subscribers. When transmitting control signals over buses 33 and 34, device 5 performs the transmission and reception of information in a digital computer.

The device in, the mode of information from the DVR subscriber-receiver works as follows.

At the initial moment, all the registers, counters, and triggers of the device are set to zero.

From the digital computer through the bus 33 receives a signal that sets the trigger 26 in

Each dressing from a digital computer consists of two parts — address and information, and enters the device in the form of a sequential codogram in a post-50 positive code at input 21 and then to the driver 8.

Co each generator of input information shaper 8 produces a pulse. First impulse produced

ka The pulses corresponding to the address part of the parcel from the output of the imaging unit 8 through the AND 11 element opened by the enabling signal from the OR 32 element are fed to the input of the counter 19 to count the number of received bits of the address part of the parcel. At the same time, the pulses from the output of the imaging unit 8 through the element I 9 are fed to the input of the register 1 for receiving the address of the subscriber-receiver. At the end of the addressing part of the dressing counter 19, counting the corresponding number of cycles (when the counter is full), a signal that passed 5 And 10 elements - to the input of the register 16

through the element 30, sets the trigger 26 to the zero state, and the trigger 28 to the single state.

In accordance with the subscriber-receiver address code received in register 1, a signal appears at one of the outputs of the decoder 2, which, through the OR 3 element, prepares the AND 4 element for passing clock pulses.

Upon the arrival of the information part, the serial code from the output of the imaging unit 8 pulses through the element 12, which is opened by the resolving signal from the element 17, is fed to the input of the counter 20 to count the number of bits of the information part of the feed. At the same time, the pulses from the driver 8 through the element I 14, open 40

From the recording element, the information from the subscriber's NOT 17 and trigger 28 is sent to the element I 14, from whose output it goes to the clock input of the register 5. This will receive the serial code of the information part of the register into register 5 When counting in the counter 20 the number of ticks corresponding to the information part of the dressing (when the counter overflows), the signal that sets the triggers 18 and 28 to the zero state is removed from its output, while the information from the register 5 is barred from riemnik. The point is written in parallel code to register 6.

The pulses of the information part of the code parcel from the digital computer from the output of the imaging unit 8 through the I 15 element opened by the enabling signals from the HE element 17 and the trigger 29 are sent to the clock input of the register 6. Since the register 6 records the information code of the initial subscriber then from the output of register 6 the sequential code of the information powder from the source subscriber arrives at the output 22 of the device. From the output of the formuli information to all subscribers-recipients - 50 users 8 pulses corresponding to

NIKI from register output 5 to outputs 25, but the information will be received by the subscriber whose address decoder 2 will output to output 24..

Further, the next code message may be repeated, the device will work without changing the mode or the device will change its mode of operation.

The device in the mode of reception in the digital computer information from the subscriber-source works as follows.

From the digital computer, bus 34 receives a signal that sets the trigger 27 into one state. The enable signal from the output of this trigger enters the elements And 10, 31, OR 32.

When a code parcel arrives from the digital computer, the pulses of the address part of the dressing from the output of the former B through the element 11 arrive at the input of the counter 19 to count the number of bits of the address part of the register and through

to receive the address of the source subscriber.

At the end of the address part of the downlink, counter 19, having calculated the corresponding number of ticks, passes the signal that, having passed through the element 31, sets trigger 27 to the zero state, and trigger 29 turns to one, and also enters the input of register 6 as a recording signal information from the source subscriber to the register 6.

At the same time, the address of the source subscriber arrives from the output of the register 16 to the inputs of multiplexers 7, which transmit the parallel information code from a given subscriber coming from inputs 23 to the inputs of register 6. When entering from And 31 to the input of register 6

la records information from the subscriber-use

the point is written in parallel code in register 6.

The pulses of the information part of the code parcel from the digital computer from the output of the imaging unit 8 through the I 15 element opened by the enabling signals from the HE element 17 and the trigger 29 are sent to the clock input of the register 6. Since the register 6 records the information code of the source subscriber, then from the output of register 6, the sequential code of the information powder from the source subscriber arrives at the output 22 of the device. From the output of the form-information part of the board, through element I 12, opened by an enable signal from the element NOT 17, is fed to the input of counter 20 to count the number of bits of the information part of the board from the source subscriber. When the counter 20 overflows, a signal appears at its output setting trigger 29 to zero state.

The device in the mode of simultaneous reception of digital computers and issuing information to the subscriber-receiver works as follows.

In this case, the signals 33 are set in buses 33 and 34, setting the triggers 26 and 27 to a single state. The address part of the code parcel contains the address of the subscriber-receiver and the address of the subscriber-source.

When the address part of the code parcel containing the subscriber-receiver address arrives from the digital computer, the pulses from the output of the imaging unit 8 through the AND 9 element arrive at the input of register 1 to receive the address of the subscriber-receiver, and through the II element to the input of the counter 19 to calculate the bits the address part containing the address code of the subscriber-receiver. The first impulse of the address part of the parcel, having passed through the element E 13, sets the trigger 18 into the unit state. The signal from the output of the trigger 18 in the register 5 disconnects from the subscriber-receiver. At the end of the address part containing the receiver's subscriber address, at the output of counter 19 (when it is full), a pulse appears that, having passed through AND 30, sets trigger 26 to the zero state, and trigger 28 - to the unit state. In accordance with the subscriber-receiver address code received in register 1, a signal appears at one of the outputs of the decoder 2, which, through the OR 3 element, prepares the AND 4 element for passing clock pulses.

I

Pulses corresponding to the address part containing the address of the source subscriber, from the output of the driver B, via element 10, arrive at the clock input of register 16 to receive the code of the address of the subscriber-source, and through element 11 11 to the input of counter 19 to count the number of bits allocated under the address of the source subscriber. At the end of the address part of the parcel, a signal appears at the output of the counter 19, which, having passed through the element 31, arrives as a signal recording information from the source subscriber to the input of the register 6 and to the inputs of setting the zero state of the trigger 27 and the single state of the trigger 29.

At the same time, the address of the source subscriber arrives from the output of the register 16 to the inputs of the multiplexers 7, when arriving from the element I 31 to the input

Register 6 of the recording signal information from the source subscriber is recorded in parallel code in register 6.

To receive the information part from the driver 8 through the element

and 14 and the AND 4 element are supplied to the clocks arriving at the input of the register 5. In this case, the serial code of the information code is received in the register 5. At the same time, the clocks through

the element And 15 arrive at the input of register 6, and since the code of the information subscriber of the source subscriber is recorded in it, then simultaneously with the reception of each bit of information in the register 5

from the output of register 6, the bit information of the source subscriber is output to output 22.

When counting in the counter 20 the number of ticks corresponding to the information part, at the end of the reception and output from its output, an overflow signal is received, which sets the triggers 18, 28 and 29 to the zero state, and

the prohibition of issuing information from register 5 to the subscriber-receiver.

At the same time, the transfer of the serial code of the information subscriber of the source subscriber to the digital computer is completed and information is output to all subscriber receivers from the output of register 5 to outputs 25. The information will be received by that subscriber

the address of which the decoder 2 leads to exit 24.

Claims (1)

Invention Formula A device for interfacing subscribers with a digital computer, containing a working register and a first shift register, the information inputs of which are connected to the input pulse generator and are the input device for connecting the information output of a digital computer, the second shift register, a group of information inputs which is connected to the outputs of the group multiplexers whose information inputs form a group of inputs for connecting information inputs of source subscribers, the output of the second shift register is the output of the device for connecting the information input of a digital computer, the group of outputs of the working register is a device output group for connecting information inputs of subscribers-receivers, five AND elements, a decoder, a connecting input with an output of the first shift register, and outputs with an input The first element OR, the output of which is connected to the first input of the first element AND, the output connected to the clock input of the working register, three flip-flops, the element-NOT and the first clock counter, the decoder output being the device output for connecting the subscriber-receiver address inputs, the first the inputs from the second to the fourth elements And are connected to the output of the pulse generator, the outputs from the second to the fifth elements And are connected respectively to the control input of the first shift register, the second input of the first element And and the clock and control inputs of the second shift register, the control input of the working register, the second inputs of the third and fourth elements I are connected respectively to the outputs of the first - third triggers, the reset inputs of which are connected to the output of the first clock counter; the output of the element is NOT connected to the third input of the third element And, characterized in that, in order to increase the capacity of the device, the third shift register, the second clock counter, the fourth and fifth triggers, the second OR element, and from the next to ten first AND gates, wherein the control inputs of multiplexers Compiled by V.Lertlib Editor S.Pekar Tehred L.Kranchuk Order 1453/47 Circulation 673 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production Ch1no-polygraphic enterprise, Uzhgorod, Projecto st., 4 the groups are connected to the output of the third shift register, the information input of the device connected to the input for connecting the information output of the computer, and the control input - with the output of the sixth And element, the first inputs from the sixth to the ninth And elements are connected to the output of the pulse former, the first inputs of dec the second element and the second element OR and the second inputs of the second and ninth elements AND are connected to the forward output of the fourth trigger, the inverse output of which is connected to the first input of the fifth and second inputs And, the third input of which is connected to the output of the fifth register and the second inputs of the fifth element AND and the second element OR, the output connected to the input of the element NOT and the second input of the seventh element And, the output of which is connected to the input of the second clock counter whose output with the second input of the tenth and the third input of the fifth element And, the output of the element is NOT connected to the third input of the fourth element And the second input of the eighth element And, the output connected to the input of the first clock counter, the outputs of the ninth, fifth and The tenth And elements are connected respectively to the inputs of the first, third and second triggers, the outputs of the fifth and tenth And elements are connected respectively to the reset inputs of the fifth and fourth triggers, the installation inputs of which are the corresponding inputs of the device for connecting the operation mode of the digital computer device. Proofreader L. Patay