SU1399749A1 - Device for interfacing subscribers with digital computer - Google Patents

Abstract

The invention relates to computing, in particular to devices for interfacing subscribers with a digital computer, and can be used in data exchange systems. The aim of the invention is to increase speed. The device contains three shift registers, a working register, three shift counters, a fixed memory, a decoder, two multiplexers, five triggers, ten AND elements, two OR elements, a NOT element, a single vibrator. 1 il.

Description

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The invention relates to computing technology, in particular to devices for interfacing subscribers with a digital computer, and can be used in data exchange systems.

The purpose of the invention is to increase the speed of the device.

The drawing shows a block diagram of the device.

The device contains the first shift register 1, the decoder 2, the first element OR 3, the first element AND 4, the working register 5, the third shift register 6, the first group of multiplexers 7, the one-shot 8, the sixth 9, the third 10, the fourth 11, the fifth 12, second 13, seventh 14 and eighth 15 elements AND, second shift register 16 NOT .17, third trigger 18, first counter 19 shifts, second I element OR 20, information input; 21, output 22, groups of informational inputs 23, address output 24, groups of information outputs 25, first 26 second 27, fourth 28 and fifth fifth triggers, ninth 30 and ten The first 31 elements are AND, the first 32 and second 33 TIRES, the device control, the second 34 and the third -35 shift counter, the second group of multiplexers 36 and the fixed memory (PP) 37.

The first} and second 16 registers of the | Shift are used to receive the successive codes of the address of the subscriber-primary 1- and the subscriber-source of information, respectively. The number of bits: the register is determined by the size of the address part of the package necessary to encode the address of the subscriber-receiver (subscriber-source). The third shift register 6 is used to receive the parallel code of the information subscriber of the source subscriber and issue it with a sequential code;

The working register 5 is designed to receive the serial code of the information parcel and to issue it in parallel to the receiving subscriber; the number of register bits is determined by the size of the information part of the subscriber supplied from the digital subscriber to the receiver. The decoder 2 is provided for generating the binary codes of the address of the subscriber-receiver of information into a position code.

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45 The device operates in one of the three modes defined by the signals acting on the first 32 and second 33 control buses from the digital computer. When the control signal is sent only via bus 32, the device operates in the mode of outputting information from the digital computer to the addressed subscriber-receiver. When the control signal is sent only via bus 33, the device operates in the mode of receiving information from the addressed subscriber-source to the digital computer. In the presence of control signals on buses 32 and 33, the device performs the issuance and reception of information in a digital computer.

Consider the operation of the device in the mode of issuing information from the digital computer to the subscriber-receiver. At the initial moment, all the registers, counters, and triggers of the device are set to the zero state.

From the digital computer via bus 32, a signal is received that sets trigger 26 into one state. Allowing the 1st signal from the 25 single output of the trigger 26 is fed to the inputs of elements 9, 13, 20 and 30 and to the corresponding control inputs of the multiplexers 36.

Each parcel of a digital computer consists of 30 two parts — address and information — and enters the device in a sequential code at input 2I and a single vibrator 8.

For each bit of the input information, the one-shot 8 produces a pulse. The first impulse through the element And 13, the trigger 18 is set to one state, its single finding disconnects the register 5 from the group of outputs 25 of the device. The pulses corresponding to the address part of the package, from the output of the one-vibrator 8, through the element 11, opened by the enabling signal from the element I, PI 20, are fed to the input of the shift counter 19 to count the number of received bits of the address part of the package.

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At the same time, the pulses from the output of the single-oscillator 8 through the element 9 are fed to the input of the register 1 for receiving and storing the adresser-subscriber.

At the end of the address part of the package, the counter 19 generates an overflow signal, which, having passed through the element 30, sets the trigger 26 to the zero state, and the trigger 28 - to the single state. At the same time, the overflow signal records in the offset 34 counter read 37 in the additional code of the binary-coded format of the information part of the subscriber-receiver code parcel whose address is taken in register 1 and transmitted to the input 37 through the multiplexer 36. Suppose the maximum number of bits to the information part the code send of the receiving subscribers (source subscribers) is 64, then the SP 37 is 6, and if, for example, the destination subscriber’s address is received in register 1, the information part of the code send of which is 32 rows, the counter 34 is recorded code equal to 100000. In accordance with the received code in register 1, the receiver addresses to the subscriber. the corresponding address output 24 from the output of the decoder 2 appears and a signal from the output of the OR 3 element allows the passage of 14 pulses through the element AND from the output of the one-vibrator 8 generated for each bit of the information part of the code message to the input of the register 5.

At the same time, the pulses from the output of the one-shot 8 through the element I 2, opened by the resolution signal from the HE 17, are fed to the input of the shift counter 34 to count the number of bits of the information part of the code parcel, for example 32, after counting which, the output of the counter 34 generates an overflow signal setting triggers 18 and 28 to the initial (zero) state. In this case, the prohibition of issuing information from the register 5 to the outputs 25 of the device is lifted and the information is allowed to be output to all subscribers-receivers that will be received by that subscriber by the receiver whose address of the decoder 2 outputs to output 24.

Further, the operation of the device is repeated in a similar manner until the mode of operation changes from the digital computer.

Consider the operation of the device in the reception mode in the digital computer of information from the source subscriber. In this case, from the digital computer via bus 33 a signal is received, which sets trigger one in a single state, allowing the signal from a single output of which goes to elements 10 and 31 and the element

OR 20 and the corresponding control inputs of multiplexers 36,

When a code parcel arrives from a digital computer, the pulses of the address part of the parcel from the output of the one-shot 8 through the element 11 are fed to the input of the shift counter 19 to count the number of bits of the address part

parcels and through element 10 to the input of register 16 for receiving the address of the source subscriber.

At the end of the address part of the parcel, the counter 19 generates a replenishment signal, which, having passed through the element 31, sets the trigger 27 to the zero state, and the trigger 29 turns to one, and also enters the input of the register 6 as a signal for recording information from the source subscriber in parallel code. At the same time, the overflow signal from the output of counter 19 records in the shift counter 35 read from SPT 37 the additional 5 code of the binary-coded format of the information part of the code message of the source subscriber whose address is received in register 16 and transmitted to multiplexers 36

0 PP 37.

Suppose that the address of the source subscriber is received in register 16, the information part of the code premise of which is 16 bits, then the counter

g 35 records a code of 110,000.

The pulses of the informational part of a co-, dual package from a digital computer from the output of a single vibrator. 8 through the element AND 15, which is opened by the permissive signals from the element NOT 17 and the trigger 29, arrive at the clock input of the register 6. Since the register of the information packet from the source subscriber, is recorded in register 6.

5 then from the output of register 6, the sequential code of the information package from the source subscriber arrives at 22 devices. In addition, the pulses from the output of the one-shot 8, corresponding to the information part of the package, through the element 12, opened by the enabling signal from the element NOT 17, are fed to the input of the shift counter 35 to count the number of bits

g of the information part of parcel, for example, 16, after counting which, at the output of the counter 35, an overflow signal is generated, which sets the trigger 29 to the zero state.

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Consider the operation of the device in the mode of simultaneous reception in the digital computer information from the source subscriber and the issuance of information from the digital computer to the subscriber-receiver. In this case, the buses 32 and 33 receive signals that set the triggers 26 and 27 to one state. For this mode, the address part of the code package contains the address of the subscriber-receiver and 1 Address of the subscriber-source.

When the address h is received from the digital computer; parts of the code parcel containing the subscriber-receiver a | cres, the pulses from the output of the one-vibrator 8 through the element I 9 are fed to the input of register 1; To receive the address of the subscriber-prik | ik and through the element 11 to the input from the 19-shift counter for calculating the number of rows of the address part containing the addresses of the subscriber-receiver. I The first impulse of the address part of the ос link, having passed through the element I W, | becomes the trigger 18 in the single state. Sitsnal from the exit of one 1-1ICHAL arm of the trigger 18 is produced in the register 5 disconnecting from the outputs of the 25 device. At the end of the address part containing the address of the receiver's fiber, an overflow signal appears at the output of the counter 19, which, having passed through the element 30, sets the trigger 26 to the zero State, and the trigger 28 - to the unit.

However, prior to resetting the trigger 26 to the zero state, the signal overflow has time to write the additional code of the binary-coded fmack of the information part of the subscriber-receiver Parcel-receiver code part read from the PS1 37, since

the output of the register 1. So, to the input 45 of the single-vibrator 8 through the element Ш1 37 it is allowed to pass the signals 15 to the input of the register 6,

from the output of register 1 as with unit-shh sign, as it contains the information code for triggers 26 and 27, as well as for a single value of trigger 26 and numerical transmission of the source subscriber, simultaneously with the reception of each

the actual trigger value 27.

Suppose that the address of the subscriber-receiver is received in register 1, the information part of the code premise of which is 24 bits, then a code equal to 101000 is written to the shift counter 34. According to the subscriber-receiver address code received in register 1 at one of the outputs defibrator 2 appears the signal that

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through the SHSh 3 element prepares the AND 4 element for passing the impulses of the information part of the code

 parcels of the subscriber-receiver to the tact-5 вы u and register input 5.

Pulses corresponding to the address part containing the address of the source subscriber from the output of the one-shot

10 8 through the element 10 and arrive at the clock input of the register 16 to receive the code of the address of the subscriber-source and through the element 11 to the input of the counter 19 shifts to count the number

15 bits allocated for the address of the source subscriber. At the end of the address part of the message, at the output of counter 19, an overflow signal 5 appears for the second time, which passed through

20, the element 31, enters as a signal for recording information from the source subscriber to the input of the register 6 and to the inputs for setting the zero state of the trigger 27 and the single state of the trigger

25 Pa 29. At the same time, the overflow signal from output 19 writes to the shift counter 35 the additional code of the binary-coded format of the information part of the source subscriber's code message read from the W 37.

Suppose that the address of the source subscriber is received in register 16, the information part of the code message of which

35 is equal to 8 bits, then a code equal to 111000 is written to the counter 35. Upon the arrival of the information part of the code send, the pulses from the output of the one-vibrator 8 through the element 14 and

The 40th element And 4 are fed to the input of the register 5, in this case the serial code of the subscriber-receiver information parcel is received in the register 5. At the same time, the pulses from

and since it contains the information code

sending the subscriber-source, then simultaneously with the reception of each

bits. information in the register 5 from the output of the register 6 is performed by issuing a bit of information parcel of the source subscriber to the output 22.

When counting in the counter 34

number of bits corresponding to the information part of the subscriber-receiver (in this case 24), an overflow signal appears at its output, which sets

the triggers 18 and 28 are in the zero state, and the prohibition of issuing information from the register 5 to the outputs 25 of the device is removed.

At the same time, the pulses from the output of the one-shot 8 through the element And 12 arrive at the input of the counter 35 shifts. Since, as an example, the subscriber-source is considered, which is in the information part of a code parcel of 8 bits, the overflow signal from the output of counter 35 appears earlier than from the output

ten

The control panel connects to the subscriber's information output groups, while the output of the first element of the IPD is connected to the first input of the first element I, the output of which is connected to the clock input of the working register, which enables the input connected to the single output of the third trigger, the single input of which is connected to the output of the second element I , the first input of which is connected to the first inputs of the third, fourth, fifth, sixth, seventh, eighth elements AND

counter 34. The overflow signal from and with the one-shot output, the information input of the counter 35 sets the trigger 29 to the zero state, however, the device continues until the overflow signal appears from the output of the offset counter 34, after which the device can start the next cycle of receiving information from the subscriber in the digital computer - the source and output of information from the digital computer to the subscriber to the receiver.

Claims (1)

Invention Formula A device for interfacing subscribers with a digital computer containing three shift registers, a decoder, a working register, two OR elements, ten AND elements, five flip-flops, a one-shot, a HE element, two shift counters, the first group of multiplexers, and the information input of the working register is connected with the information inputs of the first and second shift registers, with the one-shot trigger input and the device input for connecting to the information output of the digital computer, the single inputs of the first and second flip-flops are device inputs for CONNECTIONS respectively to the outputs of output and input digital computer, an information output of the third shift register is the output device for connection to a data input of a digital computer, group outputs, group decoder coupled to inputs per-; OR element and form a device output group for connecting subscriber samples to the corresponding inputs, working register information output groups form device output groups for connecting subscriber information input groups, groups of information inputs of multiplexers of the first group form device input groups 20 25 thirty The input of the decoder is connected to the output of the first shift register, the clock input of which is connected to the output of the sixth And element, the second input of which is connected to the second input of the second And element, to the first input of the ninth And element, to the first input of the second OR element and to the single output the first trigger, the zero input of which is connected to the single input of the fourth trigger and to the output of the ninth element And, the second input of which is connected to the first input of the tenth element And, and to the output that the first shift counter overflows, the counting input one of which is connected to the output of the fourth element AND, the second input of which is connected to the output of the second element OR and to the input  2g of the element NOT, the output of which is connected to the second inputs of the fifth, seventh and eighth elements AND, the outputs of which are connected respectively with the counting input of the second shift counter, with 40 by the second input of the first element And with the clock input of the third shift register, the clock input of the second shift register is connected to the output of the third element And, the second input 45 is connected to the zero output of the first trigger and to the second input of the tenth element And, the third input KOf of which is connected to the second input of the second element OR, to the third input of the third element And ij to the single output of the second trigger, the zero input of which is connected to the output of the tenth element And, with the input of the record of the third shift register and with the unit INPUT OF THE FIFTH TRIGGRA, whose single output is connected to the third input of the eighth AND element, the overflow output of the second shift counter is connected to the zero input of the third 50 The control panel connects to the subscriber's information output groups, while the output of the first element of the IPD is connected to the first input of the first element I, the output of which is connected to the clock input of the working register, which enables the input connected to the single output of the third trigger, the single input of which is connected to the output of the second element I , the first input of which is connected to the first inputs of the third, fourth, fifth, sixth, seventh, eighth elements AND The input of the decoder is connected to the output of the first shift register, the clock input of which is connected to the output of the sixth And element, the second input of which is connected to the second input of the second And element, to the first input of the ninth And element, to the first input of the second OR element and to the single output the first trigger, the zero input of which is connected to the single input of the fourth trigger and to the output of the ninth element And, the second input of which is connected to the first input of the tenth element And, and to the output that the first shift counter overflows, the counting input one of which is connected to the output of the fourth element AND, the second input of which is connected to the output of the second element OR and to the input the element is NOT, the output of which is connected to the second inputs of the fifth, seventh and eighth elements AND, the outputs of which are connected respectively with the counting input of the second shift counter, with the second input of the first element And with the clock input of the third shift register, the clock input of the second shift register is connected to the output of the third element And, the second input second connected to the zero output of the first trigger and to the second input of the tenth element And; the third input KOf of that is connected to the second input of the second element OR, to the third input of the third element And ij with the unit output of the second trigger, the zero input of which is connected to the output of the tenth element And, with the input of the recording of the third shift register and with the single INPUT of the FIFTH TRIGGRA, whose single output is connected to the third input of the eighth element AND, the overflow output of the second shift counter is connected to the zero input of the third I