SU1432534A1 - Device for interfacing subscribers with digital computer - Google Patents

Abstract

The invention relates to computing technology, in particular to devices for interfacing subscribers with a digital computer, and can be used in control computing systems. The aim of the invention is to increase speed. The goal is achieved by introducing into the device that contains the control unit, the shift register, the first subscriber address counter, the first word count counter, the first subscriber address decoder, three AND groups, two working register groups and the OR element, the second subscriber address counter, the second words and the second decoder addresses of subscribers. 1 hp f-ly, 4 ill. (ABOUT

Description

The invention relates to computing, in particular, to the interface of subscribers with a digital computer, and can be used in control computing systems.

The purpose of the invention is to increase the speed of the device.

FIG. 1 and 2 shows a block diagram of the device; in fig. 3 and 4 is a functional block diagram.

The device (Figures 1 and 2) contains a control block 1, a shift register 2, a first counter 3 subscriber addresses, a first word count 4, a second counter 5 subscriber addresses, a second counter 6 word counts, a first decoder 7 subscriber addresses, a second decoder 8 addresses of subscribers, elements 9 of the first group, working registers 10 of the first group, elements 11 of the second group, working registers 12 of the second group, elements 13 of the third group, element OR 14, output 15 of the serial device code, group of information outputs of the device 16, entrance 17 pos edovatelnogo code device, a clock input device 18, inputs 19 and 20 command signals and the initial installation of the device, an information input device 21.

The device (Figures 1 and 2) contains buses 22-71 of the inputs and outputs of the elements of the device that perform the following functions: first 22, second 23, fifth 24, fourth 25, sixth 26, third 27 inputs of control unit 1; the first 28, third 29, fifth 30, fourth 31J second 32 outputs of control unit 1; a serial code input 33, a clock input 34, a control register input 35 of the shift register 2; the first group of discharge outputs 36, the second group of discharge outputs-37, the third group of discharge outputs 38, the fourth group of discharge outputs 39 of the shift register 2; information input 40, counting input 41, recording control input 42 of the first counter 3 subscriber addresses; information input 43, counting input 44, recording control input 45 of the first counter 4 of the number of words; information input 46, counting input 47, recording management input of the second counter 5 subscriber addresses; information input 49 count input 50, control input 51. recording the second counter 6 word counts; information entry 52 and

prohibiting entry 53 of the first decoder 7 addresses of subscribers; information input 54 and prohibiting input 55 of the second decoder addresses of subscribers; outputs 56 of the first decoder 7

subscriber addresses; outputs 57 of the second decoder 8 addresses of subscribers; the second 58 and the first 59 inputs of the elements And 9 of the first group; the second 60 and the first 61 inputs of the elements And 11 of the second group; sequential code inputs 62, control inputs 63 and clock inputs 64 operating registers 10 of the first group; control inputs 65 and clock inputs 66 operating registers 12

the second group; information outputs 67 working registers 10 of the first group; information inputs 68 working registers 12 of the second group; second inputs 69 and first inputs 70 elements

And 13 of the third group; input group 71 elements OR 14.

The control unit 1 (FIGS. 3 and 4) holds the triggers 72 and 73, the first, fourth, third, sixth, seventh, second, ninth, eighth and fifth elements AND 74-82, delay elements 83-85, the counter is 86 clocks and the element is OR 87. At 88-122, the inputs and outputs of block 1 are designated.

The control unit 1 is designed to control their signals, which exchange information with a digital computer, and shift register 2 to receive the sequential code of the control word from the digital computer and convert it to n, and

parallel

The command word from the digital computer contains the address of the subscriber of the information receiver (An), the number of words output from the digital computer into the subscriber-receiver (C), the address of the subscriber of the source-information (Bp), the number of words entered into the digital computer from the subscriber of the source (D).

The address of the subscriber's receiver of information (An) is the address of the first subscriber to which information is output from the digital computer.

In accordance with the number of words (s) output from the digital computer, the information is successively output to the subscribers, starting with the subscriber with the address An and ending with the subscriber with the address (An + C).

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Address of the subscriber - the source of information (BN) - the address of the first subscriber, from which information is entered into the digital computer.

In accordance with the number of words (D) entered in the digital computer, the information from subscribers is entered sequentially, starting with the subscriber with address B and ending with the subscriber with address (Bn + E).

Counter. 3 serves for storing and modifying the addresses of subscribers to which the DVR outputs information.

The decoder 7 selects the required working register 10 in accordance with the address in the counter 3.

Each of the working registers 10

BUT

pulses to the input 34 of the register 2, to the input 23 of the unit 1, to the inputs 64 of the registers 10 and to the inputs 66 of the registers 12.

Before starting operation, input 20 of input 1 of block 1 is given a Initial installation signal, by which outputs 28 and 32 of block 1 are set to the zero state. Then, through input 19 to input 25 of block 1, a command signal is sent, which is memorized in block 1.

When it appears from the digital computer via input 17 at input 22 of block 1 and input 33 of register 2 of the sequential code of the command parcel, block 1 outputs from output 28 to input 35 of the register 2 a signal to enable shift, allowing reception of the serial code of the command

it is intended for reception from the digital computer after-2Q of the registration in register 2.

thirty

A numeric value matching code, convert it to parallel, and send to the subscriber.

Counter 5 is used to store and modify the addresses of subscribers, out of 25 of which the digital computer enters information,

The decryptor 8 selects the required working register 12 in accordance with the address in the counter 5

Each of the working registers 12 is designed to receive a parallel code from the subscriber, convert it into a serial one and transfer it to a digital computer.

Counter 4 is used to store and modify the number of words that need to be output from the digital computer to the subscribers. When the contents of counter 4 become zero, a signal appears at its output.

Counter 6 is slazkit for storing and modifying the number of words that must be entered into the digital computer from subscribers. When the contents of counter 6 becomes -. equal to zero, a signal appears at its output.

The device works as follows.

During the exchange of information between the digital computer and subscribers, the device operates in two modes: in the mode of outputting information from the digital computer to subscribers-receivers and the mode of entering information from source subscribers, both of which can be 55 simultaneously.

In the process of operation of the device from the digital computer through the input 18 of the clock,

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After the end of the reference from the output 31 of the block 3, the input 45 of the counter of the counter 5 and the input 51 is given to the control signal, the address of the subscriber-reception 4 of the number of words sent to the subscriber, into the counter of the source-source, into the counts entered from At the same time, the solution of the shift from the output is removed at the same time, and if, after zapa in counter 6, it is zero, which is determined by the signal at its output but with the removal of the signal from block 1, the signal is released at the output in the case of 6 is zero, so ka 4 is different from zero, with no signal course, signal Allow output 32 blocks 1 n Menno with the arrival of the first wail parcels entering input 17 to the input 22 plaque

From the output of the counter of the ta-receiver, the encoder 7 is fed in and hangs, provided that from the pin 4 does not equal zero, the signal of the 56 decoder. If the soder 4 is equal to zero, then with the 53 decoder 7

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After receiving the command sending from the output 31 of the unit 1 to the input 42 of the counter 3, the input 45 of the counter 4, the input 48 of the counter 5 and the input 51 of the counter 6, the control signal is output, which records the address of the subscriber-receiver to the counter 3 4 numbers of words output from the digital computer to the subscriber, to the counter 5 of the address of the source subscriber, to the counter 6 of the number of words entered from the subscribers to the digital computer, the signal is simultaneously removed. Enable shift from the output 28 of block 1, and if after recording the information into counter 6 its contents is not zero that is defined c by the absence of a signal at its output, then simultaneously with the removal of the signal from block 2 code 1 signal, the resolution of the shift appears at output 32 of block 1. In the case when the contents of counter 6 are zero and the contents of counter 4 are different from zero, which is determined by the absence of a signal at its output, the signal of the resolution of the output 32 of block 1 appears simultaneously with the arrival of the first bit of the numeric parcel coming from the digital computer via input 17 to the input 22 of block 1.

From the output of counter 3, the address of the subscriber-receiver is fed to the input 52 of the decoder 7 and depending on the address, provided that the contents of the counter 4 is not zero, a signal appears at one of the outputs 56 of the decoder 7. If the contents of counter 4 is zero, then from its output to the input 53 of the decoder 7, a signal is given that prohibits the appearance of a signal for all

Outputs 56 of this decoder. From the output of the counter 5, the address of the source subscriber is fed to the input 54 of the inflator 8 and, depending on the address, provided that the contents of the counter 6 is not zero, a signal appears at one of the outputs 57 of the decoder 8. If the contents of counter 6 is zero, then from its output to the input 55 of the decoder 8 a signal is applied that prohibits the appearance of the signal on all the outputs 57 of this decoder.

When information is simultaneously output from the digital computer to the subscribers and inputted from subscribers to the digital computer, the device operates as follows.

After the command parcel from the digital computer, through input 17, a sequential code of the number arrives, which enters the inputs 62 of registers 10 and input 22 of block 1. The shift resolution signal from output 32 of block 1 is fed to inputs 59 of elements 9 and 9 and to inputs 61 of elements 11 and 11 At the same time, the input 63 of the corresponding register 10 from the output of one of the elements 9, to the input 58 of which, in accordance with the address of the subscriber-receiver, a signal is sent from one of the outputs 56 of the decoder 7, the contents of counters 4 and 6 are excellent

Steps control signal that allows writing a serial code from input 62, from the codes 67 of this register, information is sent to the corresponding subscriber via information output 16. Simultaneously with the signal Allowing the shift to the inputs 61 of the elements 11 to input 65 of the corresponding register 12 from the output of one of elements 11, whose input 60, in accordance with the address of the source subscriber, receives a signal from one of the outputs 57 of the decoder 8, receives a control signal permitting the issuance of numerical information received from vuyuschego subscriber 68 to the inputs of register 12 via the data input device 21.

From the output of register 12, the sequential code is fed to the input 70 of the corresponding element I 13, and the input 69 of this element is given a signal from the output 57 of the decoder 8, allowing the serial code from the output of the element 13 to the corresponding input 71 of the element OR 14, from the output of which a numerical parcel through the output 15 of the device is issued to the digital computer.

After exchanging one numerical signal, the resolution of the shift from the output 32 of block 1 is removed simultaneously, if the contents of counter 4 is not zero, from output 29 of block 1 to input 41 of counter 3 and input 44 of counter 4 is given a signal that keeps counter 3 incremented and the contents of counter 4 is reduced by one, at the same time, if the contents of counter 6 is not zero, output 30 of block 1 to input 47 of counter 5 and input 50 of counter 6 is given a signal

by which the contents of counter 5 are increased, and the contents of counter 6 are reduced by one.

Thus, each next numerical parcel is written to register 10 and is outputted from register 12 with the addresses increased by one compared to one.

After that, - if the contents of counters 4 and 6 are not: equal to zero, then at output 32 of block 1, a shift resolution signal appears and occurs; the process of exchanging the next numeric one.

So it goes on until

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from zero

After another reduction in the contents of counters 4 and 6, the following situations are possible.

If the contents of counter 4 become zero, and the contents of counter 6 is different from zero, the signal from the output of counter 4 will go to the input 53 of the decoder 7 and will prohibit the appearance of the signal at the outputs 56 of this decoder, as a result, the appearance of signals at the inputs 63 will be prohibited registers 10 permitting the recording of numerical sums from a digital computer, I enter the inputs to the inputs 62 of these registers, and consequently, the output of information from the digital computer to the receiving subscribers stops; In addition, the signal from the output of counter 4 is fed to the input 27 of block 1 and will prohibit the issuance of a control signal from the output 29 of block 1 to the input 41 of counter 3 and the input 44 of counter 4, which will save the information in these counters. Until the next command send, the device will continue to work only in the mode of inputting information from source subscribers to the digital computer.

/

If the contents of the counter 6 mill

equal to zero, and the contents of counter 4 will be different from zero then the signal from the output of counter 6 will go to the input 55 of the decoder 8 and will prohibit the appearance of the signal at the outputs 57 of this decoder, as a result the appearance of signals at the inputs 65 of registers 12 and the inputs of 69 elements will be prohibited And 13, permitting numerical information from registers 12 to a digital computer, and therefore, the input of information from source subscribers to the digital computer will stop; In addition, the signal from the output of counter 6 will go to input 26 of block 1 and will disable the control signal from output 30 of block 1 to input 47 of counter 5 and input 50 of counter 6, which will save the information in these counters. Until the next command command, the device will continue to work only in the mode of outputting information from the digital computer to the subscribers of the receiver.

If the contents of counter 4 and counter .6 are zero, then due to signals from the outputs of these counters, both input of information into the digital computer and its output to subscribers will be prohibited. Until the next command parcel, the exchange will be terminated and the shift resolution signal

hectares at output 32 of block 1 will not be generated.

The control unit 1 operates as follows.

Throughout the operation of the device, through the input 23, the inputs of the delay element 83 and the element 74 do not receive clock pulses.

Before starting operation, input 24 of the trigger inputs 72 and 73 is given a signal to the Initial installation, according to which they are set to the zero state. At the same time, at the inputs of the .90-92 elements And 74, 76 and 79 and the outputs 28 and 32 of block 1, zero signals appear, and a positive potential is applied to the input 102 of the counter 86, which sets the counter 86 to the zero state.

Then, through the input 25 of block 1, to the input 106 of the flip-flop 73, a command is sent, which sets the flip-flop 73 to one state, at which the positive potential is fed to the inputs 104 and 103 of the elements 76 and 77 and the inputs 78 and 122 of the 78 and 79 is a zero signal.

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The reception of the command sending is carried out by the control unit 1 as follows.

When the sequential code of the command parcel appears through the input 22 of block 1 to the input 88 of the trigger 72, the latter is set to one in which the output signal from the output of the element 76 to the output 28 of block 1 receives a positive signal. The shift resolution, moreover, with a single state of the trigger 72, the passage of clock pulses from the output of the AND 74 element to the input 93 of the counter is 86 cycles.

After the counter 86 counted the number of clock pulses corresponding to the duration of the commands0

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signal The end of a word, coming in on the inputs 109-111 of the elements And 75, 77 and 78.

When the output of the clock delay element 83 appears, the signal of the end of the word from the input of the element 77 is output 31 of block 1, while the signal the word ends from the output of the element 77 and through the element 87 is fed to the input 119 of the element 85.

When a clock pulse appears at the output of the delay element 84, inputs 98 and 99 of the flip-flops 72 and 73 from the input of the element And 75 receive a signal that is reset.

WITH

of these flip-flops and counter 86, after which the signal to allow the shift from the output of 28 of block 1 is removed.

This completes the command-line reception.

When information is output from the digital computer, unit 1 operates as follows.

After booting the command dressing through input 22 to input 88 of trigger 72, the serial code receives the sequential code of numerical input, at which the trigger 72 is set to one, as a result of which output signal 79 comes to output 32 of block 1 in addition, in the case of the single state of the trigger 72, the passage of clock pulses from the output of the AND 74 element to the input 93 of the counter 86 strokes is allowed. After the 86 clock clock counter counts the number of clock pulses corresponding to the duration of of bulk, its on signal is Finished

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words, acts and inputs 109-111 element I 75, 77 and 78.

At nonFfjioHiiH at the input 113 of the element AND 78 of a tactical pulse from the output of the element 83, the signal ends the word from the trace of the element 78 and enters the paths 115 and 116 of the elements 80 and 81, and also through the element 187 to the input of the element 85 delay. If this time at input 27 of block 1 does not have zero sig) 1al, then the signal of the word Rings from the output of the iH 80 element goes to the output 29 of block 1. I When a clock pulse appears | from its output it sends a signal to the inputs 98 and 99 of the flip-flops | 72 and 73, which sets the triggers to the zero state, as a result of which the output of the 32 shift of the block 1 is the shift resolution signal, block 1 is ready to receive the next numeric sign .

i

; When you enter information in the digital computer unit; 1 works as follows. ; From the digital computer to the input 20 of block 1 receives a command parcel. After receiving | the last bit of the sequential: Command parcel code at the output; counter 86, a signal is generated: End of word arriving at the inputs 109-111 of the And 75, 77 and 78 elements.

When a pulse pulse appears at the input 112 of the element AND 77 from the output of the delay element 83, the signal ends the word from the output of the element 77 and enters the output 31 of block 1, as well as through the element OR 87 at the input of the element 85 delay.

When a clock pulse appears at the output of the delay element 84, inputs 98 and 99 of the flip-flops 72 and 73 from the output of the And 75 elements receive a signal to zero these triggers and the counter 72.-When the signal appears, End of a word from the output of the delay element 85, if There is no zero signal at the input 26 of block 1, the input 101 of the trigger 72 from the output of the element AND 82 receives a signal that sets this trigger into one state. As a result, a shift resolution signal is sent from the output of the AND 79 element to the output 32 of block 1, and clock pulses are sent to the input 93 of the meter 86 from the output of the And 74 element.

After the counter 86 counts the number of clock pulses corresponding to the duration of a numeric parcel, a signal appears at its output. End of word word arrives at the inputs 109-111 of the elements And 75, 77 and 78.

When the element 78 appears at the input 113 of the clock pulse from the output of the delay element 83, the signal ends the words from the output of the element 78 and enters the inputs 115 and 116 of the elements 80 and 81 and also through the element OR

87 to the input element 85 delay. If at this time at the input 26 of block 1 there is no zero signal, then the signal End of the word from the output of the element And 81 will go to the output 30 of block 1.

When a clock pulse emerges from the output of the delay element 84 at the input 95 of the element 75, a signal is output from its output to the inputs 98 and 99 of the flip-flops 72 and 73, which sets these triggers to the zero state, as a result of which the output resolution 32 is removed. .

When a signal appears End of a word from the output of delay element 85,

if the input 26 of block 1 does not have a zero signal, the input 101 of the trigger 72 from the output of the element I 82 is blunted by a signal that sets this trigger to one state. As a result, a shift resolution signal is sent from the output of the AND 79 to the output 32 of the block 1, and clock pulses are sent to the input 93 of the counter 86 from the output of the And 74.

Next, the procedure for generating the signals Shift resolution and End of word is repeated.

When combining the mode of inputting information into a digital computer and outputting information and from

Digital Signal Generation The resolution of the shift and the end of a word are carried out for each mode independently of each other.

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Claims (2)

1. A device for interfacing subscribers with a digital computer (DVM) containing two groups of working registers, three groups of AND elements, an OR element, a shift register, the first subscriber address counter, the first subscriber address decoder, the first word number counter and 111 the control unit) and the first input of which is connected to the inputs of the serial code of the shift register and the working registers of the first group and is the input of the device for connection to the output of the serial code of the digital computer, the first output of the control unit is connected to the control input of the shift register, the second output is with the first the inputs of the elements of the first and second groups of the second inputs of the elements of the first group are connected to the outputs of the first decoder addresses of subscribers, the outputs of the elements of the first and second groups are connected respectively to the control the inputs of the working registers of the first and second groups, the information outputs of the working registers of the first group form a group of outputs of the device for connecting to the information inputs of subscribers, the information inputs of the working registers of the second group form a group of inputs of the device for connecting the information outputs of subscribers, the outputs of the serial code of the working registers the second group is connected to the first inputs of elements AND of the third group, the outputs of which are connected to the group of inputs of the element OR whose output is the output of units for connecting to the input of the serial code of the digital computer, the clock input of the shift register is the device input for connecting to the clock output of the digital computer and connected to the clock inputs of the working registers of the first and second groups, and the second input of the control unit, the first and second groups of the bit outputs of the register of the shift are associated respectively with the information inputs of the first counters of the addresses of subscribers and the number of words, the counting inputs and the recording control inputs of which are connected respectively to the third and fourth outputs of the block control, the output of the first subscriber address counter is connected to the information input of the first subscriber address decoder, the output of the first word number counter is connected to the third input of the control unit, the fourth and fifth inputs of which are respectively the device inputs for connecting to the outputs of the command signal and the initial setup signal Digital computer devices, characterized in that, in order to increase the speed five 25 5 0 5 About Q -, five five 441 2 devices, a second subscriber address counter, a second count of the number of layers, a second decoder of subscriber addresses are entered into it, with the third and fourth groups of the bits of the shift register outputs associated respectively with the information inputs of the second subscribers address counters and the number of words, recording control inputs and counting inputs which are connected respectively to the fourth and fifth outputs of the control unit, the output of the second subscriber address counter is connected to the information input of the second subscriber address decoder , The output of the second counter the number of words is coupled with a sixth input of the control unit, and prohibiting the input of the second decoder subscriber address, the second inputs of AND gates of the second and third groups are connected to the outputs of the second decoder subscriber addresses zapreschayu1tsy input of first decoder subscriber addresses connected to the output of the first counter word count. 2. The device according to claim 1, wherein the control unit contains two flip-flops, nine AND elements, three delay elements, a clock counter and an OR element, the first single input of the first flip-flop being the first input of the block, the direct output of this trigger is connected to the first inputs of the first - third elements AND, the outputs of the third and second element. And AND are the first and second outputs of the block, the output of the first element AND is connected to the counting input of the clock counter, and the second input - with the second input of the block and through the sequence The first and second delay elements are connected with the first input of the fourth element I, the first zero inputs of the first and second triggers are connected to the fifth input of the block, the second zero inputs of the first and second triggers are connected to the output of the fourth element I, the inverse output and the second single input of the first the trigger is connected respectively to the installation input of the clock counter and the output of the fifth element And, the direct output of the second trigger is connected to the second input of the third element And and the first input of the sixth element And, the single input and the inverse output of the second trigger are connected 13 respectively, with the fourth input of the block and the first input of the seventh element And, the output of the counter of counters is connected to the second inputs of the fourth, sixth and seventh elements And, the third inputs of the sixth and seventh elements And are connected to the output of the first delay element, the output of the sixth element And is connected to the fourth output of the block and the first input of the OR element, the output of the seventh element AND is connected to the first inputs of the eighth and ninth elements AND and the second input 1.4 3253414 the OR element, whose code through the third power element is connected to the first input of the fifth AND element, the outputs of the ninth and eighth AND elements are the third and fifth outputs of the block, the second input of the ninth And element is the third input of the block, the second the input of the eighth element And is connected to the sixth input of the block and the second input of the fifth element And, the second input of the second element And is connected to the inverse output of the second trigger. f ) f / aJ 28 Of- 91 122 13 Iqk sixteen t 110 t 77 119 115 in t 116 108 18 120 81 2S 30 3f 2ff Z7 32 If - ““ 19t in 87 85 121 82 FIG.