SU1401639A1 - Commutation system checking device - Google Patents

Abstract

The invention relates to communication technology and provides continuous monitoring of a switching system. The device contains a comparison unit 1, input multiplexers 2, output multiplexers 3, switching blocks 4, memory block 5, control register 6, test block 7 and controlled switching system (KKS) 8 The time counter in KKS 8 generates clock pulses operation of all units of the device. The continuity of control of the CCM 8 is ensured by the introduction of blocks 4-7. But the operation of blocks 1, 4, 5, 7, 8 is no longer clear. 6 Il.

Description

05

with so

: The invention relates to communication technology and can be used in digital switching systems.

The purpose of the invention is to provide continuous monitoring of the switching system.

FIG. 1 shows the structural electrical circuit of the switching system control device; in fig. 2 is a structural electrical circuit of the comparison unit; in fig. 3 is a structural electrical circuit of a switching unit; in fig. 4 is a structural electrical circuitry of the memory unit; in fig. 5 is a structural electrical circuit of the test unit; in fig. 6 - structures - Ie electric circuit of the controlled switching system.

 The device contains a comparison unit 1, input multiplexers 2, output multiplexers 3, switching blocks 4, frame unit 5, control register 6, test block 7 connected to the controlled switching system 8.

Comparison unit 1 (FIG. 2) contains a first multiplexer 1-1, a memory block, a trigger 1-3, a comparison element 1-4, and a second multiplexer 1-5.

The switching unit 4 (Fig. 3) contains the elements AND 4-1 and 4-2 and the element OR 4-3. ; Memory block 5 (FIG. 4) contains a block 5-1 of a semiconductor memory and the element: AND 5-2.

A: Test block 7 (Fig. 5) contains a comparison element 7-1 and a register 7-2: offset.

: The controlled switching system - 8 (Fig. 6) contains elements 8-1 of the comparison, shift registers 8-2, fixation blocks 8-3, time counter 8-4, code output converters 8-5, blocks 8- 6 memories, blocks 8-7 comparing time codes, distributor 8-8 and block 8-9 address memory.

The device works as follows.

The switching of incoming and outgoing communication lines is carried out with the help of block 8-9 (Fig. 6) of the address memory of the controlled switching system 8 (Fig. 1). Block 8-9 has memory cells attached to incoming lines of communication. The numbers of the memory cells and the incoming lines are the same. The addresses of the outgoing lines are written to the memory cell, with which the corresponding incoming lines are switched. Communication line commutations in the memory cells of block 8–9 are also recorded as C, O, indicating connection establishment. When disconnecting to each memory cell of block 8-9, the address of its outcome of the communication line and signal x 1, which enters the test block 7 at the moments of reading information from the memory cells of block 8-9, are recorded. Signal OS, 1 provides for the issuance of a test pattern recorded on shift register 7-2 (Fig. 5) of the testing unit, at those time intervals of the group path (GT), which are served by the cells of block 8-9, which have a signal (X 1.

Thus, in the group path of the switching system, a test is issued from test block 7 accompanied by the address of its outgoing communication line from block 8-9 of the address memory. This test passes through the corresponding devices 8-8, 8-6, 8-5 (Fig. 6) of the switching system. We are output through the corresponding multiplexer 3 to the input of the AND 4-2 element (Fig. 3) of the switching unit 4.

At this time, the signal 1 from the control register 6 is fed to the other input of the element 4-2. The signal about (. 1 passes the test through AND 4-2, OR 4-3 elements, which then passes through the shift register 8-2, block 8-3 time fixation (Fig. 6) and enters the input of the comparison element 7-1 ( Fig. 5) of testing unit 7. In element 7-1, the code of the test signal received from block 8-3 is compared with the code from shift register 7-2 of the previously issued test. This comparison is performed using the signal ". 1 from block 8- 9. Address memory. If a comparison occurs, then the operation of the corresponding electrical circuits of the device for controlling the switching system is correct, and If it does not, the test unit 7 generates a signal 9 1, which, together with the address of the incoming (outgoing) communication line, is output to the control node (CU) of the switching system.

When switching incoming and outgoing communication lines, the signal is recorded not only in the address communication block 8-9, but also in the memory block 5. The signal l is read out for the control register 6, from whose output already And 4-1 and 4-2 elements (fig. 3) go to the two signals cXi Id. If 1 1, then C (0. With ct 1, the element AND 4-2 will open, allowing the test to pass through the output multiplexer 3 to the element OR 4-3, and if O (1), then the element 4 4-1 will be opened that transmits the code of a signal that is transmitted on the corresponding input line and is fed from the input multiplexer 2 to the element OR 4-3. The memory block 5 has a cell, each of which provides for storing ss signals (i 1,2, ..., p) read and write to the control register 6 at the same time, which provides control immediately by p blocks 4. The device capacity is N p – m lines connection.

In the process of switching communication lines, the signal ot. enters the blocks 5 and 8-9 from the control unit of the switching system 8. At the same time, the input of the block 5--1 (Fig. 4) is

step: the address A of the memory cell, the information AND, which is a signalized; and a signal that records the signals (in the corresponding memory cell of the block 5-1. The signal enters through the AND 5-2 element and provides Into the rt of the recording, the entry of information into the block 5-1. The read cycles г of the read, the record г and the readout address A come from the counter 8-4 of the time of the switching system.

When testing the electrical circuits of the device, the shift register 7-2 (Fig. 5) provides for the sequential issuance of various codes (O, 1) of test signals. Testing is performed continuously until the corresponding incoming and outgoing communication lines are switched.

When a connection is established in memory block 5, a d o signal is recorded, i.e. one bit of information for each incoming link. In this case, the memory cells of the block 5 are assigned to the m incoming lines of communication serviced by each switching unit 4. The number of bits in each cell is equal to the number of blocks 4. The numbers of communication lines and switching blocks 4 coincide with the numbers of the memory cells and bits in the cells of memory block 5, respectively. Recording the signal O into the corresponding memory cell of unit 5 ensures the passage of switched signals from the incoming communication line through switching unit 4.

The signals from the memory block 5 are read and the corresponding incoming line is connected via the input multiplexer 2 using the LII address 5 from the counter 8-4 of the switching system 8. The same address A is used to interrupt the corresponding outgoing lines using output multiplexers 3 when testing the electrical circuits of the device.

After switching the incoming and outgoing communication lines, signals are transmitted from the incoming lines through the input multiplexers 2 and switching units 4 to the inputs of the shift registers 8-2 (Fig. 6), which have m + 1 bits. The number m + 1 is chosen so that it was possible to store all the hp codes of the switched signals of the previous cycle during one cycle of register 8-2 and compare them one by one using the comparison element 8-1 with the 2 codes of the new signals received from the input multiplexer 2 cycles that are written to the first trigger of the shift register 8-2. At the same time, on the first and (w + -l 1) -th triggers of register 8-2 there will be a new and old codes of the switched signals of the same

five

0 o

5 d

5 5

0

the input of the input multiplexer 2, for example i-ro.

If the polarity of the switched signal in the i-th input line changes, then the codes of the switched signal of the i-th input line recorded on the first and (m + -f 1) -m triggers of register 8-2 are different, which will be fixed by comparing element 8-1, which produces a signal at 1. If the polarity of the signal in the i-th line has not changed, then a signal is produced at 0. Signal 1 is used to record new time in block 8-3 The code of the signal of the i-th input line, previously recorded on the first trigger of shift register 8-2.

The new signal code is recorded in block 8-3 of time stamping along with the time code from time counter 8-4 (Fig. 6). The memory location number in which this information is recorded also comes from a counter of 8-4 times. This number corresponds to the line A address, which also arrives at the weekend and input multiplexers 2 and 3 and into memory block 5. The number of memory cells in block 8-3 time fixation and their numbers correspond to the rn inbound links serviced by the corresponding input multiplexer 2.

The counter 8-4 time provides the generation of clock pulses that synchronize the operation of all blocks of the device. With the help of clock pulses, cyclic reading of information from blocks 8-3 of fixing time and issuing it to the GT, through which it enters the corresponding blocks of the device, is performed. The code of the switched signal, the time code that records the time of arrival of the signal in the switching system, and the address of the incoming line from which the signal came, are transmitted through the GT. The address of the incoming line goes to block 8-9 of the address memory and to block 1 of the comparison (Fig. 1.6), the signal code goes to block 8-9 and to block 7 of testing. The time code passes through block 8-9 and enters the distributor 8-8. Similarly, the time code passes and when testing the electrical circuits of the device.

Each cell of the memory of blocks 8-3 of time fixation is read in a certain time interval of the GT operation (Fig. 6). In the same interval, the transformation of the address of the incoming line is performed. to the address of the outgoing line .4 with the help of block 8-9 of the address memory, i.e., at the address of the AVL, the address is processed from block 8--9. which enters the distributor 8-8. With the help of the distributor, which is a decimator, the switched signals and their time codes are distributed over 8-memory blocks. The distribution of signals is accomplished, 1 by decoding the high-order bits of the address AED. The low bits of this address are used to determine the memory location number of the block 8-6, into which the information is written. Blocks 8-6 of memory have m cells, the numbers of which correspond to the numbers of outgoing lines served by the corresponding output converters 8-5 of the code. Information (time code) from memory cells of blocks 8-6 is read cyclically using signals from time counter 8-4 and sent to the inputs of blocks 8-7, and the outgoing link address that corresponds to the number of the readable memory cell blocks 8-6, and the signal code is output to the output converters 8-5 of the code.

The time code from memory blocks 8-6 is compared in block 8-7 for time code comparison with the time code received from time counter 8-4. When comparing these time codes, signals that provide the distribution of switching signals by means of converters 8 to 5 to the outgoing lines are transmitted to the output converters 8-5 of the code. If the time codes in blocks 8-7 are different, then S o signals are generated that prohibit the output of signals to outgoing lines.

Monitoring of the electrical circuits of the switching system after switching the incoming and outgoing communication lines is carried out using the comparison unit 1 (Fig. 1 and 2). In this case, the switched signals from the incoming lines arrive at the inputs of the first multiplexer 1–1, which passes them into memory block 1-2 using the address of the incoming Aule line from the co-switching system's GT. The same address h also provides with the help of the read cycles of the r. first reading the previous information (signal code) from memory block -2 and writing it to trigger 1-3, and then writing a new signal code to the same memory cell of block 1-2.

The codes of the signals transmitted by outgoing lines, are fed to the inputs of the second multiplexer 1-5 and further using the address of the outgoing lines Ail, are passed to the element 1-4 of the comparison. The other input of the element 1-4 of the comparison receives the signal code from the trigger 1-3. Addresses A and A. and ЯВ are the addresses of interconnected communication lines through which the same signals pass. These signals are compared using reference element 1-4.

The switched signals transmitted on the incoming lines pass through the switching system 8 and are then output to the outgoing lines with a delay tj. The delay time ts is provided (implemented) with the help of memory block 1-2, i.e., when a signal appears on the incoming communication line, it is recorded in block 1-2, and exactly through the operation cycle of the GT switching system this signal appears at the output of the switching system 8, and then it will go through the second multiplexer to the input of comparison element 1-4, and another input of this element I-4 will receive the same signal read from memory block 1-2 and recorded on trigger 1-3 . If the switched signals are different, the signal "from block 8-9 of the address memory of the switching system will receive from the comparison element 1-4 a signal 0., 1, which indicates 3 that the device is faulty.

Claims (1)

Invention Formula A device for controlling a switching system, comprising a comparison unit, input multiplexers, to the information inputs of which are connected input lines, output multiplexers, whose information inputs are outputs for connecting information outputs of the controlled switching system, and control inputs of the input and output multiplexers are inputs to connect the first control output of a controlled switching system, characterized in that, in order to provide continuous monitoring to switching system, serially connected memory block and control register, switching blocks, the first and second inputs of each of which are connected to the outputs of the corresponding input and output multiplexers, and the third and fourth inputs are connected to the corresponding outputs of the control register, test block, inputs and outputs which are the inputs and output for connecting the service outputs and service input of the controlled switching system, while the outputs of the switching blocks are outputs for The information inputs of the controlled switching system. We, the control inputs of the input and output multiplexers are connected to the information input of the memory unit, the information inputs of the input and output multiplexers are connected to the corresponding inputs of the comparison unit, the control inputs of which. are inputs for connecting the second and third control outputs of a monitored switching system.  G (l HsS / i.2 Hiffl.3 Editor A. Shandor Order 2541/56 Compiled by A. Ceselkn Tehred I. VeresKorrektor O. Kravtsova Circulation 660 Subscription VNIIPI USSR State Committee for Inventions and Discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and noligraphic enterprise, Uzhgorod, ul. Design. four FIG. .7