SU1564623A1 - Multichannel device for test check of logic units - Google Patents

Abstract

The invention relates to automation and computing and can be used in test control equipment and tuning of digital nodes and blocks. The purpose of the invention is to expand the functionality of the multi-channel device of the test control of logical nodes. The device contains a memory unit, a switching unit and control units, each of which contains a receiving and storing node, a buffer memory node, a pulse generator, an address decoder, a synchronization node, a load node, and control nodes. By introducing a buffer memory node, a pulse generator, a load node, and a new execution of control blocks and a switching block, the functionality of the device is expanded by enabling control nodes that have bi-directional logic circuits, use of control tests with uncertain values in the test at the outputs of the controlled logical node, the definition of a short circuit at the inputs of the controlled logical node, control in the imp lsnom mode control load capacity controllable logical node, the logical control node at different frequencies supplying a control test, the simultaneous monitoring of multiple logical hosts. 5 hp ff, 11 ill., 3 tab.

Description

The invention relates to automation and computing and can be used in test control equipment and setting up digital nodes and blocks.

The purpose of the invention is to expand the functionality of the device due to the control of different types of logical nodes under load.

FIG. 1 shows a block diagram of the device; in fig. 2 block diagram of the control unit; in fig. 3 - functional circuit of the switching unit; in fig. 4 is a functional diagram of the receiving and accumulating unit; in fig. 5 - functional diagram of the synchronization node; in fig. 6 - functional diagram of the buffer memory node; in fig. 7 is a functional diagram of the pulse generator; in fig. 8 is a functional layout of the display unit; in fig. 9 - functional scheme forto with

signal distributor; on fng. 10 - functional scheme of the node loads; Fig. 11-functional control scheme.

The device (Fig. 1) contains an input block 1, a memory block 2, a switching unit 3 and blocks 4.1-4. Control. FIG. Figure 1 also shows objects 5.1-5 || W control, which are not included in the device and are given to explain the operation of the device.

The control unit 4 (FIG. 2) forms the receiving and accumulating unit 6, the node

synchronization, node 8 buffer PA

t, generator 9 pulses, display unit 10, driver 11 signals, address decoder 12, load node 13 and nodes 14. 1-14.g control

In the switching unit 3 (Fig. 3), a generator of 15 clock pulses includes an element AND 16S, a distributor 17 pulses, triggers 18.1-18. M, elements AND-NO 19.1-19.t, elements NOT 20.1 20. t, elements AND-NOT 21.1-21.t, nodes 2: 2.1-22.t matches, elements OR 2; 3-28 and nodes 29.1-29.t matches, "Nodes 22.1-22.t matches in LUs multi-bit with a common raster channel for each level.

Node 6 reception and accumulation (Fig. Consists of a counting trigger 30, elements AND-NOT 31 and 32, and D-flip-flops 33 Synchronization node 7 (Fig. 5) contains a single pulse shaper 44, clock generator 45, de. Frequency clock 46, element AND-NOT 47, 0-flip-flop 48, elements-AND-HEN 49-52, lS-flip-flops 53 and 54, item NO 55, D-flip-flop 56, item And 57, D-flip-flop 58, shaper 59 of a single pulse, item And -NOT 60, element 61, delay element 62, RS flip-flop 63.1-63.5, switches 64.1-64.5 and switches 65 and 66.

The buffer memory node 8 (FIG. 6) includes a counter 67, elements HE 68 and 69, D-flip-flop 70, element 71 of the operative memory, eleventh AND-NE element 72, D-flip-flop 73, register 74, elements AND 75 and 76, the delay element 77 and the element OR NOT 78.

The generator 9 pulses (Fig. 7) form the elements AND-NOT 79.1-79.p, 80.1-80.p and 81.1-81.p, the element And 82 registers 83-85, the seventh elements And 86.1-86.P and 87.1- 87. P., element 88 comparison, elements OR-NOT 89 and 90 shaper 91 single pulse

diction

He element 92, RS flip-flop 93, D-flip-flops 94, 95.1-95.ti and 96.1-96.P, counter 97, generator 98 clock pulses, D-trigger 99 and element 100.

The display unit 10 (FIG. 8) includes AND elements - NOT 101-103, NOT elements 104 and 105, AND-NOT elements 106.1- Yub.p, NOT elements 107-1C9, AND-NE element 110, elements 111 and 112 indications, switch 113, AND-HE elements 114 and 115, D-trigger 116, oscilloscope 117, binary-decimal counter 118, descrambler 119 and element 120 in5

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Shaper 11 signals (Fig. 9) contains the element 121 delay, the encoder 122, the element NOT 123, elements AND NOT 124-128, elements AND 129-131 and RS-triggers 132-134.

The load node (FIG. 10) includes a switch 135, elements AND-NOT 136-138, D-flip-flop 139, RS-flip-flop 140, register 141, elements -NEY 142-143, counters 144 and 145, source 146 reference level logic zero, source 147 reference level logic unit, comparators 148 and 149, element AND-NOT 150, decoder 151, element 152 of comparison, elements NOT 153 and 154, element AND 155, driver 156 of a single pulse, element AND-NOT 157 , switching element 158, elements And 159-168 and current generators 169-173.

The control unit 14.1 (FIG. 11) contains the elements NOT 174-176, the elements AND-NE 177-183, RS-flip-flops 184-187, the element AND-NO 188, the D-trigger 189, the element AND 190, the element AND-NOT 191 open collector, elements AND 192 and 193, element NOT 194, resistor 195, element EXCLUSIVE OR 196, element OR-NOT 197, resistor 198, setting reference 5 199 of the reference voltage, resistor 200, np-n transistor 201, element AND - NOT 202, element NOT 203 and level 20 generator of logical units.

The input unit 1 is a punched tape input unit.

The memory unit 2 is a magnetic storage device.

Multichannel device test control logical nodes (figure 1) works as follows.

The test program of the control is stuffed on an eight-track punched tape and with the help of a block 1 of input from a punched tape

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is entered preserving the format of a punched tape in memory block 2, where the location of the information fully corresponds to its placement on the punched tape. The eight information outputs of the input block 1 correspond to eight punched tape tracks. In order to synchronize the operation of the input unit 1 and the memory unit 2, during the recording of the control test program, a synchronization signal is used, which is fed from the output of the memory unit 2 to the synchronization input of the control unit 1. In memory block 2, several control test programs can be stored simultaneously for monitoring various types of logic nodes on separate control units 4.

From control unit 4.1 (i -6 t), the inputs of block 3 are supplied with a five-bit binary code of the control test program number stored in memory block 2, which must be sent to the control unit 4.1, and the information request signal. Block 3 with the arrival of these signals organizes the exchange of information of memory block 2 only with block 4.1 of the control. From the outputs of block 3, the information received from block 4.1 of the control enters the inputs of block 2 of memory, in which the test test program is searched by number, and the eight-bit information word corresponding to the eight-track punched tape is output from the outputs of block 2 of memory to block 4.1 of control , the seventh bit of the information word being used to synchronize the operation of the entire device. Block 3 of the tape (total nine binary bits), and the information part occupying the 5th track of the even line of the tape tape (one binary bit). Consequently, the operation code is placed in two lines of punched tape and takes up only ten binary bits. The weights of perforations in the address part of the operation code are determined from Table. one.

In addition to the basic operations represented on the punched tape by the operation code, there are also auxiliary operations that are not encoded with a special code (binary) 5:

survey - the presence of punching in the sixth track of the odd string of punched tape;

sync - the presence of punching in the seventh track of the odd and even Q rows of punched tape;

The end of the control test program is the presence of punching in the eighth track of the odd line of punched tape.

The control unit 4.1 (FIG. 2) is in operation B in the request mode of the test control program from the memory block 2 and in the mode

object control 5.1 control. i

In request mode test program

The control at the outputs of node 7 generates 0 with a five-bit code of the test program number, a control program that must be entered into the node 8 of the buffer memory, which ensures the autonomous operation of the control unit 4.1, and a request signal from the test program. In addition, a signal is set at the control output of the synchronization node 7, allowing the recording of the test program control to the node 8 of the buffer memory. Number test

The control test program is transmitted and the program goes to the inputs of block 3, runs seven bits in the control box 4.1, and is fed to the corresponding inputs from which the signal from the 22 22.1 coincidence nodes (Fig. 3) is received, and the request signal is sent to S-input RS-flip-flop 18.1, and RS-flip-flops

dew, and the eighth bit is used to stop the exchange of information with the control unit 4.1 and prepare for the exchange of information with any other block 4. The control block 4.1 converts the control test program received from block 2 (in the punched tape format) the tasks of operations that must be performed by the control unit 4.1 to ensure the control of the object 5.1 of the control. The operation is specified using the corresponding operation code located on a punched tape. The operation code consists of an address part occupying 1-5 tracks of the odd line and 1-4 tracks of the even line of the repro program is fed to the inputs of block 3 and fed to the corresponding inputs

nodes 22.1 match (Fig. 3), and the request signal is applied to the S input of the RS flip-flop 18.1, and the RS flip-flops

18.1-18.rn are set to the initial zero state (not shown). The pulses from the generator 15 clock pulses through the element And 16 is fed to the input of the distributor 17 pulses,

which polls its elements AND-NOT 19 with its outputs, i.e. the resolving signal sequentially polls all the elements of the NAND 19.1-19.t, implementing the priority scheme for choosing the control unit 4.1. The request signal translates the trigger 18.1 into one state and when the signals on the NAND 19.1 element coincide, the prohibiting

the signal from the output of the element 19.1, stopping the arrival of pulses at the input of the distributor 17. The distributor of pulses remains in the state corresponding to polling of the 1st control unit, prohibiting the passage of signals: from the remaining t-1 control units to memory block 2. Request signal; element output 19.1 through the element 20 does not arrive at the control inputs of the nodes 22.1 and 29.1 matches and at the i-th input of the element OR 23. The enable signal at the control input of block 22.1 matches allows the test program number of the control to pass through the node 22.1, match and arrive at the corresponding inputs of the elements OR 24-28s from the output of which the number

the control test program is fed to the outputs of block 3 and from them to the inputs of block 2 of memory. The request signal, which arrives at the 1st input of the element OR 23, conducts the output of block 3 and from it to (the corresponding input of memory block 2. T1 when the memory block 2 receives the control test program number and the request signal, memory block 2 This module outputs to its outputs line by line a control test program, which is received at the corresponding inputs of block 3. Through the control input node, the node 29.1 matches six bits of the control test program and the synchronization signal is fed to the 1st outputs of block 3, which are connected to corresponding inputs block and 4.1 controls and, respectively, from the outputs of the receiving and accumulating unit 6. The receiving and accumulating node 6 | converts the per-tape format of the operation codes into the internal format of the operation codes of the block 4 1 of the control, which are shown in Table 2. At the outputs of the node 6 receiving and accumulating, an eleven-bit control test program is formed in which the first nine bits are the address part of the opcode, the tenth bit is the information part of the opcode, the eleventh bit is the interrogation signal. The synchronizing signal is transmitted from the input to the output of the receiving and accumulating unit 6. The eleven bits of the control test program and the synchronization signal from the receiving and accumulating unit 6 are fed to the corresponding inputs of the buffer memory node 8 prepared for recording by the synchronizing unit 7. By

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the end of the test program control to the corresponding input of block 3 (Fig. 3) from the output of block 2 of memory, the operation code of the end of the test program control KTP is supplied, which passes through the AND-NOT 21 L element prepared by the output of the item HE 28.1 and goes to R- input RS-trigger 18.1, transfer it to the initial zero state, thus removing the request signal and the control test program number from memory block 2 and prohibiting the control test program and synchronization signal from passing through the node 29.1 to control block 4.1, stopping recording information in zel 8 buffer memory. In addition, the RS flip-flop 18 запрет 1 removes the prohibition from the corresponding input of the element I 16, allowing the exchange of information from memory 2 with any other control unit.

The essence of each operation performed by the control unit 4.1 is as follows.

one . Operation K361. This operation enables the switching mode, i.e. automatic separation of the contacts of the object 5.1 of the control into input and output, and after the operation K3Јj, an operation Ko K36oo, corresponding to the input contacts, or K (- K360, corresponding to the output contacts of the object 5.1 of the counter) is going on. contacts of the object 5.1 controls the input and output, respectively.

2. Operation K 62. This operation enables the masking mode, which consists in prohibiting the monitoring of the output reactions of the object 5.1 control on any required contacts (masking) or the removal of this prohibition (unmasking). After the operation, an operation is necessary that corresponds to the output contacts of the object 5.1 of the control, which must be masked or K y - K56oi corresponds to the output contacts of the object 5.1 of the control, which must be masked. These operations actually mask or unmask the output contacts of the object 5.1 control.

3. Operation K, 63. This operation enables a logical mode of action.

and comparison of the output reactions of the object 5.1 control on input effects

9. 15

with reference. The Gusle operation K3bz is necessarily performed by the operation K ,, -, corresponding to the input actions in the form of a logical zero on the corresponding operation to the input contact, or operation K, -, corresponding to the input actions in the form of a logical unit. If the corresponding operations of the contact object 5.1 of the control are output, then these operations set the reference output reactions of the object 5.1 of the control.

4. Operation K. This operation resolves the mode of impulse actions on the object 5.1 of the control, i.e. it is used to prepare the control unit 4.1 for a pulsed mode. After operation K364- an opera

Chi - K) 60o, preparing any contact or group of contacts of the corresponding operations to receive impulse effects in the form of a burst of pulses with given parameters.

Next is the operation K365 - K38, providing the main signal is read only for the required period of pulses in the packet, operation KE90-K40, providing the required pulse duration in the packet, operation K4) Q-Cg, providing the required number of pulses in the packet, and operation, which ensures the start of the clock pulse generator in the pulse generator 9, which ensures the supply of pulse actions to the object 5.1 of the control.

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one of the operation according to the control test programs

The control test program consists of sets of operation codes (words), divided by the code Kop. The first word is switching, according to which there is a separation of the contacts of the object 5.1 of the control into input and output, and this word is of a strictly defined length, according to the number of nodes 14.1 of the control in block 4.1 of the control. It records the operation codes K ,, for the input contacts of the object 5.1 of the control or for it is not used in the control of the control nodes 14.1, and the d output contacts record the code of the operations, KS10, depending on the required load equivalent. Operation codes K. - K5) 0 are recorded in a strictly defined place of the switching word, according to the number of the output contact of the object 5.1 control. It should be noted that each of the Kodo of operations K - and K, - K jfio corresponds to only one contact of the control area 5.1 by the operation code number (1-360). The following words are informational. They set the input effects on the object 5.1 of the control, also contain reference information 55 of the object's response 5.1 control to the input effects.

5. Operation K, - K510. For these operations to the output contacts of the object

5.1 control connects load equivalents to provide control of the object 5.1 control under load, with the load equivalent encoded in the first five bits of the address part of the operation code.

6. Operation K51). This operation indicates that the object 5.1 control is monitored throughout the test control program.

7. Operation K „p. This operation monitors the validity of the object 5.1 of the control after filing

certain inputs on it, i.e. This operation compares the output reactions of the control object 5.1 with the reference ones.

8. Operation Ktp. In this operation, the input of the test test program to the node 8 of the buffer memory is stopped.

10 9. KO operation (|. This operation is Q

This is used to encode what is next for a Kop operation while monitoring a 5.1 control object under load.

In the control mode, the synchronization node 7 outputs to the node 8 of the buffer memory a control signal allowing the reading of information from the node 8 of the buffer memory. In addition, the synchronization node 7 generates a synchronization signal, which, arriving at the node 8 of the buffer memory and the signal generator 11, synchronizes 5 days of the entire control unit 4.1 and reads the control test program from the node 8 of the buffer memory. The control test program from the outputs of node 8 of the buffer memory is fed in operation to the corresponding inputs of the shaper 1 1 signals, to the address decoder 12 and to the load node 13 in accordance with the synchronization signal from the synchronization node 7. With each synchronization, only the signal is read.

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one of the operation according to the control test programs

The control test program consists of sets of operation codes (words) separated by the code Kop. The first word is a switching word, according to which the contacts of the object 5.1 of the control are divided into input and output, and this word is of strictly defined length, according to the number of nodes 14.1 of the control in block 4.1 of the control. It records the operation codes K ,, a- for the input contacts of the monitoring object 5.1 or for the control nodes 14.1 not involved in the control, and for the output contacts, the operation codes, KS10, depending on the required load equivalent. Operation codes K. - K5) 0 are recorded in a strictly defined place of the switching word, according to the number of the output contact of the object 5.1 control. It should be noted that each of the operation codes K - and K, - K jfio corresponds to only one contact of the control object 5.1 by the operation code number (1-360). The following words are informational. They set the input effects on the object 5.1 of the control, as well as contain reference information- 5 of the response of the object 5.1 to the control on the input effects.

The control mode is divided into two sub-modes: functional control and

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control under load. The operation of block 4.1 control in the control mode will be considered on the example of control according to the test program given in Table. 3. In the functional control, the load unit 13 is disconnected and the test control program arriving at its inputs from the node 8 of the buffer memory is not implemented.

1st word. In the initial state n of the output of the signal generator 11, there is a signal permitting the switching relay, which is fed to the corresponding input of all control nodes 14.1, preparing them to receive the switching word. The address part of the operation code from the outputs of the buffer memory node 8 is fed to the corresponding inputs of the binary-decimal 12 address, where it decodes with | and from the corresponding output (address) is fed to the input of the selected 14.1 control. The information part of the operation code is fed to the input of the signal generator 11, from which, after gating with a clock signal from the synchronization unit 7, v. conversion to signal Record O Incoming. And the corresponding input of all nodes 14.1 control. At node 14.1 of the Control, the signal of the Switching signal, Address 11 and Record 0 occurs. By this coincidence, the node 14.1 of the control is ready to transfer effects to the object 5.1 of the control. A similar operation occurs with all tiiH operation codes corresponding to the input contacts of the object 5.1 on the desktop or unused. According to the operations that correspond to the code contacts of the object 5.1 of the control (K4gs, K ,,, K4q5, K500), no match occurs at the 14.1 of the control. These nodes 14.3, 14.5, 14.6 and 14.9 control are prepared to receive responses of the object 5.1 of the control to the input actions. At the end of the switching word, there are operation codes K00 and Kop, which are necessary for the control of the object 5.1 of the control under Load. The interrogation signal, which is allocated at the corresponding output of the signal generator 11 by the first word operation code K00, is eliminated in the synchronization node 7, ensuring that the monitoring of the object 5.1 of the control is prohibited until the input actions are applied to it.

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2nd word. At the beginning of the second word of the po test control program, the operation code K36J goes, which, arriving at the inputs of the driver of 11 signals, removes from its outputs and, accordingly, from the input of nodes 14.1 controlling the switching signal, preparing nodes 14.1 of the control; to the transfer of input effects on the object 5.1 of the control and to the reception of its output reactions to these effects. The address part of the operation code K ,, 1 from the outputs of node 8 of the buffer memory is supplied to the corresponding inputs of the address decoder 12, where it is decrypted, and from the corresponding output by the address is fed to the input of the selected node 14.1 of the control. The information part of the operation code is fed to the input of the signal generator 11, from which, after gating with a clock signal from the synchronization node 7, and converted into a signal, the Record 1 is fed to the corresponding input of all the 14.1 control nodes. At node 14.1, the address and signal coincide. Record 1. By this coincidence, node 14.1 of the control transmits a logical effect in the form of a logical unit through the corresponding output of the control unit 4.1 to the control object 5.1. Information about the logical impact is stored in the control node 14.1 until it is changed according to the control test program. According to the operation code K31, the control node 14.3 similarly receives information on logical unity, but uses it not to transmit to the control object 5.1, but for comparison with information received from the control object 5.1, i.e. uses it as a reference. Similarly, work with operation codes, K1 K81, and K61 corresponds to the output contact of the object 5.1 of the control, since the E switching word in sixth place is the operation code corresponding to the output. According to the operation code Kop from the output of the signal generator 11, a Polling signal is extracted, which is generated from the eleventh bit of the test program of the control using a clock signal and fed to the corresponding input of all control nodes 14.1 to determine the short circuit at the input contacts of the object 5.1 of the control, to the corresponding input display node 10 to indicate the current word number of the test program

control and to the corresponding input of the synchronization node 7 for interrogating the states of the inputs of the synchronization node 7, to which the control object 5.1 fails to match the output of the control object 5.1 with the reference, the signals from the corresponding outputs of the control node 14.1, and for polling the state the first inputs of the synchronization node 7, to which they receive in the event of a failure of the 5.1 control circuit on a short circuit, the signals from the corresponding outputs of the nodes 14.1 control. In addition, signals about the malfunction of the monitoring object 5.1, if they are present in the word, from the outputs of the monitoring nodes 14.1, are fed to the corresponding inputs of the display node 10 to indicate the faulty contact of the monitoring object 5.1 and the type of failure (non-comparison, short circuit). In the event of a malfunction at the corresponding inputs of the synchronization node 7 by a signal, the Polling stops the output of the clock signal from the synchronization node 7 and, therefore, the reading of information from the node 8 of the buffer memory, i.e. the monitoring process is terminated, and on the display unit 10 the number of the word in which the fault is present, the type of fault and the defective contact of the control object 5.1 is displayed. If there is no malfunction in the given word of the test program, monitoring continues.

3rd word. According to the operation code, similarly to the second word, a logical impact in the form of a logical zero or a signal is written to the input of the object 5.1 of the control. With the arrival of the operation code K, the pulse mode arrives at the inputs of the signal generator 11, which arrives at the corresponding input of all nodes 14.1 control, to the corresponding input of the generator 9 pulses and prepares them for operation. The code of the operation of the CIO (its address part) is fed to the inputs of the decoder 12 of the address, where it is decrypted, and fed to the input of the corresponding code. perazim node 14.2 control, which coincidentally addresses and signal pulse mode is switched to the transfer of impulse actions on the object 5.1 control. Further by

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the test program of the control for the address decoder 12 receives the address portions of the operation codes corresponding to the value of the period K 80, the duration K400, the number of pulses in

pulsed action K4) 5-, which, after decoding, arrive at the corresponding inputs of the generator 9 pulses and make the necessary settings in it. When the address decoder 12 arrives at the inputs of the address part of the operation code K4W, which triggers the pulse mode, it is decrypted, the pulse generator 9 receives a work permit at the corresponding input, and a control signal is output at its output, which enters the synchronization node 7 and prevents the issue sync signal on its output, stopping reading test control program. From the corresponding output of the generator 9 pulses, the given impulse effects are fed to the input of all the control nodes 14.1 and pass only through those control nodes 14.1 that were prepared for the pulse mode according to the test program. The corresponding input of the display unit 10 is an oscilloscope input that can be monitored by pulsed effects at the inputs of the monitoring object 5.1 or pulsed responses at its outputs. At the end of the pulse mode, a control signal is output at the corresponding output of the pulse generator 9, which, arriving at the corresponding input of all the control nodes 14.1, closes their pulse channels. In addition, the pulse generator 9 extracts a control signal which, arriving at the corresponding input of the synchronization node 7, enables the output of a clock signal at its output and the reading of the test program from the node 8 of the buffer memory continues. Performing all subsequent operations in this word is similar to performing the second word.

4th word. The operation code Kg6f, arriving at the inputs of the signal generator 11, extracts at its corresponding output a switching signal, which is fed to the control nodes 14.1. According to the operation code K 1, on the corresponding node 14.4 of the control, the signal of the Switching, the address and the signal is recorded. Record 1 and node 14.4 of the control

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is transferred from the transmitting input effects on the object 5.L control to the receiving response from it. According to the operation code K50 on the corresponding node 14.5 of the control, the switching signal coincides, the address and the signal O and the control node is transferred from the response object 5.1 of the control to the input actions that transmit it. This provides for re-communication of the object 5.1 control, i.e. change the appointment of his contacts. The operation code K36j, the input inputs of the signal generator 11, selects at its corresponding output a Masking signal that arrives at the node 14 of the control. According to the operation code К „р on the corresponding node 14.9 of the control, the signal masking coincides, the addresses and the signal 3 | record O. By this coincidence, the transmission to the output of the node 14.9 x | control of the malfunction is forbidden by comparison if it is present. Masking is maintained until canceled (de-masked) according to the test control program. Further control of the object 5.1 control on this word | av; illogical control on the previous words.

5th word. The operation code, as in the previous word, turns on the masking mode. According to the operation code n4, the corresponding node 14.9 of the control coincides with the signal Masking, the address and the signal. Record 1. By this coincidence, the output signal of the 14.9 control of the malfunction signal is allowed to exit to the output in case of its presence, which provides unmasking. Further control of the facility 5.J. control by this word is similar to control by previous words.

With the arrival of the signals of the operation code at the inputs of the generator 11, the End of the array signal is outputted to the input of the synchronization node 7, where it removes the read mode and stops the clock signal — the control program test stops and the control object 5.1 is stopped. . In addition, the array signal is fed to the corresponding input of the display unit 10, for

indications that object 5.1 controls are valid.

In each (1 + 1) -th word, only changes in the operation codes with respect to the 1st word are recorded, since the information on the operation codes is stored in the control nodes 14.1 until it is changed according to the test program. I

The difference in the control mode under load is that the control node 7 by signal The end of the array does not stop reading the control test program from the node 8 of the buffer memory, but feeds it cyclically to the control object 5.1. In addition, a load node 13 participates in the work, which receives from the node 8 of the buffer memory the first five bits of the address part of the operation codes K4J, K610, which are the code, the equivalent load values that need to be connected to the output terminal of the monitoring object 5.1. . Signals 0 and Record 1 are sent to the corresponding inputs of the load node 13 from the outputs of the signal builder 11, according to the test control program. With the arrival of the first signal, Record 1, corresponding to the first output of the control object 5.1, or, respectively, the operation code K (Table 3) according to the code of the equivalent load to the output of the control unit 14.3 (the operation code gs

in the switching word it is in third place) the equivalent load is connected through the corresponding load input of the load node 13 and the test program of the control goes on

on the object 5.1 control. During the process of passing (monitoring the test program of the control unit t13 loads by a signal Poll, coming from the output of the imager 11 signals according to the codes of the operation of the CoP on

its corresponding input monitors the logic level present at the monitored output contact of the object 5.1. control If the monitored level is within acceptable limits, then the signal End of the array from the output of the driver 11 signals by operation code

 is supplied to the corresponding input of the load unit 13 and the load unit 13 is prepared for connecting the equivalent load to the next output control object of the control object according to the test program controlling, corresponding to the operation code. Test Pro17156462318

The control gram is applied to the object of the second bit in the D-flip-flop 34, the tri-5.1 control is fared as many times as the third bit in the D-flip-flop 35, and the quad-outs must be controlled under load. With the arrival after the signal Record 1m operation code K00 or the corresponding signal Record

of the same bit into the D-flip-flop 36, of the same bit into the D-flip-flop 37 and sixth bit into the D-flip-flop 43. On the falling edge of the clock signal, the counting flip-flop 30 switches to one state, overlapping the AND-NE element 32 and opening

About and code of operation of the KLP or sootvetop

of the same bit into the D-flip-flop 36, of the same bit into the D-flip-flop 37 and sixth bit into the D-flip-flop 43. On the falling edge of the clock signal, the counting flip-flop 30 switches to one state, overlapping the AND-NE element 32 and opening

50 direct output is an NE-31 element. The second sync signal passes through the prepared IS-NOT element 31 and the back edge of the corresponding C-inputs records the next sixteen bits of information, the first bit being written to the P-thigger 38, the second bit d - to D-flip-flop 39, third bit d - to D-flip-flop h-C, fourth bit d - to D-flip-flop 4, fifth

The interrogation signal applied to the load node 13 at its corresponding output is allocated a control signal arriving at the input of the synchronization node 7, and the output of the sync signal at its output is stopped, ceasing monitoring. In addition, this control signal is fed to the corresponding input of the display unit 18 to indicate the validity of the monitoring object 5.1 under load. If the monitored level of any output contact is 20 bits in D-ttzigger 42. The rear edge of the object 5.1 control goes out of the synchronization signal, the counting trigger 30 of permissible limits, then the control switches to the zero state, the output signal from the node 13 loads , overlapping the element AND-NOT 31 and subcontracting the input of the synchronization node 7, pushing the element AND-HE 32 to work. stops monitoring, and with the corresponding 25 This process repeats cyclically, the output of the load node 13 information about the faulty contact of the object 5.1 of the control enters the input of the node 10 of the display to indicate the type of malfunction (load fault) and indicate the faulty contact of the object 5.1 of the control.

The synchronization node 7 can output sync signals to its control output of various frequencies, which provides control of the control object 5.1 at various frequencies of the control test program.

In the Cycle mode, the synchronization node 7 prohibits stopping the test program 4d from the node 8 of the buffer memory. we control the signal. The end of the array in the mode of requesting information on and the test program is cyclically fed to the triggers 63 using switches to the object 5.1 control. 64 exposes the five-bit code Node 6 for receiving and accumulating (Fig. 4) the measure of the requested test program works in the following way. On the first 45 control. The single impulse produced by the six inputs of the node is fed by the shaper 44 of a single pulse synchronously with the synchronization signal, a pulse, fed to the S input by the RS-trigger arriving at the seventh input, the test pattern 48 and setting it into unit-1 control program from unit 2 memory condition. The first generation pulse in the initial state all triggers of the node $ 0 torus 45 clock pulses through the defra are in the zero state. The frequency amplifier 46 and the formation switch 66 from the first to the sixth inputs are fed to the input of the AND-HE element 49, fed to the D-inputs of the respective open through another input of the direct output D-flip-flops. The sync signal passes through trigger 48, the inverse output cut prepared by the inverse output of which sets trigger 53 on the counting trigger 30 AND-NOT element 32 to the first S input of one state and on the falling edge carries out Nue. The signal from the output of the trigger 53 to the corresponding C-inputs is recorded at the control output of the block, which discharges information into the D-trigger 33, allowing the information request mode.

carried out the deployment of push-pull information from memory block 2 to eleven-bit one-step information for receiving it in the buffer memory node 8. Information is provided to the first-eleventh outputs of the receiving and accumulating unit 6 from the direct outputs of the respective D-flip-flops, and the clock signal is transmitted from the seventh input to the twelfth output.

The synchronization node 7 (Fig. 5) provides two modes of operation of the device: the mode of requesting information from memory block 2 and the mode of reading information

the second bit in the D-flip-flop 34, the third bit in the D-flip-flop 35, the fourth

of the same bit into the D-flip-flop 36, of the same bit into the D-flip-flop 37 and sixth bit into the D-flip-flop 43. On the falling edge of the clock signal, the counting flip-flop 30 switches to one state, overlapping the AND-NE element 32 and opening

direct output element AND-NOT 31. The second sync signal passes through the prepared element AND-NOT 31 and the falling edge records the following six-bit information at the corresponding C-inputs, the first bit being written into P-thigger 38, the second bit in D-flip-flop 39, third bit d - in D-flip-flop h-C, fourth bit d - in D-flip-flop 4, fifth

The bit is in the D-Tzigger 42. With the falling edge of the clock signal, the counting trigger 30 switches to the zero state, closing the AND-HE element 31 and preparing the AND-HE element 32 to work. This process is repeated cyclically,

The bit is in the D-Tzigger 42. With the falling edge of the clock signal, the counting trigger 30 switches to the zero state, closing the AND-HE element 31 and preparing the AND-HE element 32 to work. This process is repeated cyclically,

from node 8 of the buffer memory. in the mode of requesting information on triggers 63, using switches 64, a five-bit code is set, and it implements push-pull information from memory block 2 to eleven-digit one-step information for receiving it in the buffer memory node 8. Information is provided to the first-eleventh outputs of the receiving and accumulating unit 6 from the direct outputs of the respective D-flip-flops, and the clock signal is transmitted from the seventh input to the twelfth output.

The synchronization node 7 (Fig. 5) provides two modes of operation of the device: the mode of requesting information from memory block 2 and the mode of reading information

ten

15

20

25

The impulse from the output of the NAND 49 element arrives at the output of the block, providing a request for information, and on the falling edge triggers the trigger 48 to the initial zero state, stopping the arrival of pulses from the generator 45

clock pulses at the output of the block.

(

The mode of reading information. An nSmbc produced by the single pulse shaper 59 is fed through the element 61 to the S input of the flip-flop 53 and sets it to the zero state, enabling the read mode. The signal from the inverted output of the trigger 53 is fed to the input of the element F 5 /, to the other inputs of which the permit signals from the inverted output of the trigger 54 and from the direct output of the trigger 56 echo signals, allowing the pulse of the 45 clock pulses to pass through the And 57 element to the control In this case, by setting different dividing coefficients of the frequency divider 46 using the switch 66, it is possible to obtain various information readings. The state of flip-flop 54 is confirmed on the El-input by pulses arriving through the AND-HE element 50, provided that 30 At the third input of the node there is no inhibitory signal. When a prohibitory signal is applied in the case of a pulsed mode, the element stroke IS 50 and the S-input of the rigger 54 is transferred to the Single state, prohibiting its Inverse output from passing the clock pulses to the control output of the flock. After the end of the pulse re- & im, the first clock pulse of the forward Yodit trigger 54 to the initial zero state and the issuance of clock pulses The control output of the node continues. The polling signals are sent to the IN-51 Input of the element, closed in the Idle state by the inverse output of the trigger 58, and the NOT 55 input to the element. The first Poll signal with the falling edge through the NOT 55 element switches the trigger 58 to the zero state, preparing the AND- element NOT 51 to receive follow-up polling signals. In the case of at least one fault signal at the inputs of the AND-47 element, the polling signal passes through the IS-NOT element 51, the IS-NOT element 52 and arrives at the C input of the trigger 56, switching it to the zero state and prohibiting the passage of clock signals. pulses

156462320

to the control output of the node. If the malfunction signals do not arrive at the inputs of the NAND 47 element, the readout of the control test program from the buffer memory node 8 continues until a signal arrives at the input of the synchronization node 7 End of the array, which enters the second S input of the trigger 55, translates it into a single state, stopping the read mode. The read mode can be performed cyclically, for which switch 65 is turned off and the signal ends at the end of the array through the IS-NE element 60, the delay element 62, and the element 61 at the R input of the trigger 53, including the read mode. The output signal of the element IS-NE 60 is used to automatically reset the entire device (the reset circuit of the device to simplify the diagrams are not shown). The delay value of the delay element 62 is selected based on the time required to set the entire device to its initial state. To stop cyclical reading of information, it is necessary to turn on switch 65 again. When monitoring object 5.i of the load control, switch 65 is in the off position and the reading of information occurs cyclically. With the arrival of the input element AND-NOT 52 of the signal about the end of the control 35 under load, it passes through the element IS-NOT 52 and enters the C input of the trigger 56 and puts it into the zero state, stopping the information reading, and the control mode under load ceases.

The node 8 of the buffer memory (Fig. 6) works as follows. In the initial state, the counter 67 and the register 45 74 are set to zero, and the triggers 70 and 73 are in the single state. The circuit built on the triggers 70 and 73, the element NOT 68, the element IS-NOT 72 and the element 73, selects from the clock frequency input to the node when recording information every odd pulse except the first one. An eleven-digit code is sent to the input of the data of element 7G of the RAM, which must be recorded. Each selected odd pulse arrives at the input of the AND 75 element, the second input of which is prepared by the potential from the control input of the node, and

55

The node 8 of the buffer memory (Fig. 6) works as follows. In the initial state, the counter 67 and the register 74 are reset, and the triggers 70 and 73 are in the single state. The circuit built on the triggers 70 and 73, the element NOT 68, the element IS-NOT 72 and the element 73, selects from the clock frequency input to the node when recording information every odd pulse except the first one. An eleven-digit code is sent to the input of the data of element 7 G of the RAM, which must be written. Each selected odd pulse arrives at the input of element AND 75, the second input of which is prepared by potential from the control input of the node, and

 the element 75 and the element OR NOT 78 are fed to the input of a sample of the memory element 71, recorded information on the leading edge, and the counting input of the binary counter 67. The signal from the control input through the element 69 does not enter reading the memory element 71, allowing information to be recorded at the address of the cell of the memory element 71, which is determined by the state of the outputs of the counter 67. On the falling edge of the pulse from the output of the OR-NE 78 element, the counter 67 increases its state by one, preparing ement RAM memory 71 to receive the next information. Record the information readout information from the block 2 of m tee,

The generator 9 pulses (Fig, 7) 5 works as follows. On the I-NE elements 79-81 and the AND element, the resolving pulsed signal is received, preparing them for the first address corresponding to the required period, pulse duration and number of pulses in a packet. Each specific period and duration match its specific address. , corresponding to the period, h 5 element AND-NOT 79.1 records 1 corresponding bit: RGR 8 and address, corresponding to the duration, through element AND-NOT 80.1 records

, 1 to the appropriate discharge before stopping the flow of

pulses per discharge circuit

register 84, Addresses, corresponding to the size of the packet, through the elements AND-H 81.1 write 1 in the corresponding register bits 85.1. With the address of the address corresponding to the start of the generator of the rator, the element E 83 will output a signal from its output that, arriving at the C-gate of the trigger 99, translates it into the zero state (in the initial state

each odd pulse, as well as up to the removal at the control input of the signal that permits recording.

register 84, Addresses, corresponding to the size of the packet, through the elements AND-NE 81.1 write 1 to the corresponding bits of the register 85.1. With the output of the address corresponding to the start of the generator, to the element E 83, its output will push the signal, which, arriving at the C-gate of the trigger 99, transfers it to the zero state (in the initial state

When reading information at the input write-read of the memory element 71, control signals are received from the control inputs and

clock pulses that through ele 30. - "," ".," Signal from the direct output of the trigger dE

The mentor OR-NE 78 is received at the input of you-S-Tune to stop reading the border of the memory element 71.

then nii trigger 99 is set to 1

information from node 3 of the buffer memory for the time of the pulse mode. With its AND output, trigger 99 permits the arrival of a frequency from the generator of 98 clock pulses of the AND 100 element to the C inputs of the triggers. In the initial state, the trigger 94 records by 1, which begins to shift

and to the counting input of the counter 67, and through the delay element 77 - to the C input of the register 74. The binary counter 67 on the address inputs of the memory element 71 sets the address of the cell from which the information should be counted (in the initial state - zero address). At the outputs of the memory element 71, an eleven-digit code is allocated, which is fed to the D-inputs of the register 74, and the leading edge of the C-input pulse is written to the register. The magnitude of the delay of the delay element 77 is selected based on the time required to establish information at the outputs of the RAM block 71. Zad35

information from node 3 of the buffer memory for the time of the pulse mode. With its MI version output, trigger 99 permits the arrival of a frequency from the generator of 98 clock pulses of the AND 100 element to the C inputs of the triggers. In the initial state, the trigger 94 recorded 1, which begins to shift

40 Before the match on the element AND 86.1 from 1 recorded in register 83, and up to this point the information in the triggers 96 is not shifted, since they were in the initial state

45 in O. Prch coincidence on the element K 86.1 the element OR-NOT 89 selects a signal which, arriving at the R-input of the trig

Hera 93 translates it into a single state, forming the leading front in it by the pulse front from the output of the current pulse element 5Q. In addition, this OR-NOT 78 counter 67 increases the signal through the element NO 92 and enters its state by one, by preparing the next cell of the element 71

RAM for reading. The D-inputs of the flip-flops 94 and 96.1 are read, and the next clock pulse from the 98 clock-pulse generator clears the information before the -, - flip-flops are set to 1, and the AND 86.1 disappears from the control inputs of the read-element mode. Using node 8 of the buffer memory allows blocks 4.1 controls

the Next clock pulses

work offline after

reading information from memory block 2,

The generator 9 pulses (Fig, 7) works as follows. The inputs of the IS-NE 79-81 and the AND 82 element receive the enabling pulse mode of the signal, preparing them to receive addresses corresponding to the required period, the pulse duration and the number of pulses in the packet. Each period and duration corresponds to its specific address. The address corresponding to the period, through the element IS-NE 79.1, writes 1 to the corresponding bit: RI 83, and the address, corresponding to the duration, through the element IS-NE 80.1 writes 1 to the corresponding bit.

the register 84, the addresses corresponding to the burst size, through the elements IS-NE 81.1, write 1 to the corresponding bits of the register 85.1. With the address of the address corresponding to the generator start-up, the element I 83, from its output, pushes a signal which, arriving at the C-start of the trigger 99, brings it to the zero state (in the initial state

 -. -

then nii trigger 99 is set to 1

It should be to stop reading

information from node 3 of the buffer memory for the time of the pulse mode. With its MI version output, trigger 99 permits the arrival of a frequency from the generator of 98 clock pulses of the AND 100 element to the C inputs of the triggers. In the initial state, the trigger 94 recorded 1, which begins to shift

Before the match on the element And 86.1 from 1, recorded in register 83, and up to this point, the information shift in the triggers 96 does not occur, since they were in the initial state

in O. Prch coincidence on the element K 86.1 the element OR-NOT 89 selects a signal which, arriving at the R input trig

on the D inputs of the triggers 94 and 96.1, and the next clock pulse from the generator 98 clock pulses, these triggers are set to 1, and on the And 86.1 element the coincidence disappears. Next clock pulses

geram 96, and since the code written

23156462324

in register 84, the lesser one records the contact of the object 5.1 of the control, and

sled in register 83 (the value of the pulse duration is less than the value of the period), then the match on the element And 87.1 comes earlier than on the element And 86.1. The element OR-NOT 90 selects a signal which, arriving at the R input of flip-flop 93, transfers it to its original steering state, forming the rear edge of the output pulse. Trigger-I 95 continues shift 1 to match on AND 86.1, i.e. the process is repeated cyclically and at the output of the pulse generator 9 a pulse sequence f is selected with specified parameters. The output pulses go to the C input of the binary counter 97, where it is counted until the match on the comparison element 88 is compared with the number specified on the register 85. When a match is reached, the comparison element 88 selects a signal that is fed to a single pulse shaper 91,

if at least one malfunction is present, which is supplied by the logic zero level, the level of the logical unit appears at the corresponding outputs of elements 106.1-106.p, which is fed to the corresponding input of the display element 111, where

10 the LED lights up corresponding to the faulty contact of the object 5.1 control.

If there is a signal of at least one fault at the inputs of the elements

15 that AND-NOT 101, a positive signal from its output is fed to the input of the display element 112, where the LED lights up, indicating a malfunction due to incomparability.

20 if there is at least one

a fault at the inputs of the AND-H element 102, then a positive signal from its output is fed to the input of the indication element 112, where the LED lights up,

The impulse from the output of which is realized - 25 signaling about the malfunction

The initial installation of the generator 9 Pulses, as well as enters the output of the generator for the installation of circuits of the pulsed mode at the nodes 14.1 control unit. The trigger 99 is installed in a single pass through elements 107 and 108, a final state, blocking its input to the inputs of the AND-NOT elements 114, and the inverse output of the AND 100 element, and allowing the passage of the signal through it. End of the array, which enters the input of the node 10 indication and a direct output allows further reading of information from node 8 of the buffer memory. The generator 9 pulses provides the device operation of the pulse mode.

35

is given through the element NOT 104 at the input of the element AND-NO 114, passes through it and the element AND-NO 115 at the C-input of the D-flip-flop 116, which was in the initial state at 1, and on the leading edge brings it to the zero state because its D-input is connected to the common bus of the device. A positive signal from the inverse output of the D-flip-flop 116 is fed to the input of the display element 112, where the LED lights up,

The display unit 10 (FIG. 8) operates as follows. Failure signals according to the object non-comparison | 5.1 control go to the corresponding inputs of the display unit 10 and are fed to the corresponding inputs of the AND-NE elements 101 and to the first inputs of the corresponding elements 106. 1-106 ...P. Fault signals on the short circuit of the object 5.1 of the control are fed to the corresponding inputs of the display unit 10 and fed to the corresponding inputs of the AND-NE element 102 and to the second inputs of the corresponding elements 106.1-106. Signals of non-failure on the load of the object 5.1 of the control are fed to the corresponding inputs of the display unit 10 and fed to the COOT- corresponding inputs of the AND-NE element 103 and to the third inputs of the corresponding elements 106.1-106. Each of the elements AND-NE 106.1-106. If there is at least one fault present, which is supplied by the logic zero level, the corresponding outputs of the elements 106.1-106 appear. The level of the logical unit appears, which is fed to the corresponding input of the display element 111 where

The LED corresponding to the faulty contact of the 5.1 control object lights up.

If there is a signal of at least one malfunction at the inputs of the element IT-NOT 101, then a positive signal from its output is fed to the input of the display element 112, where the LED lights, indicating a malfunction by non-comparison.

0 If there is at least one

a fault at the inputs of the NAND 102 element, then a positive signal from its output is fed to the input of the indication element 112, where the LED lights up,

short circuit

If there are no faults at the inputs of these elements, then there is a low level at their outputs, which,

is given through the element NOT 104 at the input of the element AND-NO 114, passes through it and the element AND-NO 115 at the C-input of the D-flip-flop 116, which was in the initial state at 1, and on the leading edge brings it to the zero state because its D-input is connected to the common bus of the device. A positive signal from the inverse output of the D-flip-flop 116 is fed to the input of the display element 112, where the LED lights up,

signaling that 5.1 controls are valid.

an object

In the control mode under load, the element AND-NOT 114 is closed with zero potential from the switch 113, at which the switching contact is connected fc by the common bus of the device, and the closing contact is connected to the input of the element AND-NOT 114, and the End of array signal does not pass. In this mode, if at least one malfunction occurs at the input of the NAND 103 element, then a positive signal from its output goes to the input of the display element 112, where the LED lights up, indicating that the monitoring object 5.1 is not suitable for the load. If there is no malfunction, then at the output of the NAND 103 element there is a zero level, which through the element NOT 10 is fed to the input of the element NAND 110, allowing the passage through it of a signal indicating the end of the load control mode, which enters the input of the node 10 indication and through the element NOT 105 is fed to the input of the prepared element AND-NOT 110, from the output of which the signal through the element IS-NO 115 is fed to the C input of the D-flip-flop 116, switches it to the zero state, the LED in the display element 109 is turned on, which indicates a fit object object 5.1 control. The polling signals arrive at the counting input of the binary-decimal counter 118, where they are counted, and through the decoder 119 are output to the display element 120 to indicate the current word of the control test program.

For control in pulse mode, an oscilloscope 117 is provided in the display unit 10, the output of which is connected to the control point of the control object 5.1. The second input of the oscilloscope is connected to the common bus of the device.

Shaper 11 signals (Fig.9) works as follows. An eleven-digit code is fed to the input of the signal generator 11, which is fed to the inputs of the encoder 122. The encoder 122 serves to extract the control signals determining the operating modes of the control unit 4.1: the Masking signal, which is input to the NAND 124 element, the signal Logical actions which is input to the element IS-NOT 126, a signal. Pulse mode, which enters the input of the element IS-NOT 127, a signal. The end of the array that arrives at the input of the element IS-NOT 128. Each signal has its own specific code. The tenth bit of the input code is used to generate the signals Record 1 and Record O and is fed to the input of the element AND 129 through the element NOT 123 and to the input of the element And 130, The eleventh bit of the code serves to form the Poll signal and is fed to the input of the element

0

five

0

five

0

five

0

five

0

five

And 131. The clock frequency is applied to, the input of the driver 11 signals and through the delay element 121 gates the elements AND-NOT 124-128 and the elements AND 129-131. The delay is selected based on the time required to set the signals at the outputs of the encoder 122. In the initial state, the trigger 133 is in the one state, and the triggers 132 and 134 are in the zero state. The signals from the outputs of the elements AND-NOT 124- 126 and 127, are fed to the S-inputs of the corresponding triggers and set them to one state, each of these signals setting two other triggers to the zero state, the signal from the output of the IS-NOT element 125 sets all triggers to the zero state, i.e., at a given time only one of the modes is possible. The Masking signal is allocated on trigger 132, the switching signal is on trigger 133, the Pulse mode signal is on trigger 134, the End of Array signal is on AND-NE 128, Record O is on AND 129, and Signal 1 is on 130, Poll signal - on the element And 131.

The load unit 13 (Fig. 10) operates as follows. In the control mode, the switch 135 is in the open state under load. Signals Record O arrive at the input of the element AND-NOT 136, and the signals Record 1 enter the input of the element AND-NOT 137, from whose outputs they are through the element AND-NO 138, through the element AND-NO 142, opened by the direct output of the trigger 139, is fed to the input of binary counter 144 where it is counted. With the arrival of the first signal, Record 1 at the input of the AND-NOT 137 element, the trigger 139 switches to the zero state on the falling edge of this signal. The AND-HE 142 and 150 elements overlap with their output and also include the depot 151. The signal from the inverse output of this trigger into the register 141 records the code of the equivalent of the load that must be connected to the output of the object 5.1 of the control. The outputs of the decoder 151 are connected to the corresponding inputs of the switch unit 158. Switch unit 158 includes relays and their amplifiers by the number of contacts of the object 5.1 control. The windings of the relay are connected at one end to

power supply, and the other through the amplifier - to the corresponding outputs of the decoder 151. The relays have normally open contacts. The closing contacts of all relays are combined and connected to the inputs of comparators 148 and 149, as well as to the outputs of current generators 169-173. The closing contacts of all relays are connected to the corresponding contacts of the object 5.1 control. Thus, the decoder 151 includes one relay from all the relays of switch unit 158 corresponding to the code recorded in counter 144. The required load magnitude is given by the current generated by current generators 169-173, the currents of which are distributed according to the following: 1 I0 2K s if at the outputs of elements 159-163 there is a logical unit, and at the outputs it is element) in AND 164-168 it is a logical zero, IK 10 2k, if at the outputs of elements 159-163 it is a logical zero, and elements And 164-168 - logical unit, 1K 0, if the outputs of the elements - a logical zero. In this case, 1K is the current of the k-ro generator current; 10 - normalized maximum input current of the TTL logic element connected to the output of the element having zero state; L O is the normalized maximum input current of a TTL logic element connected to the output of an element having a zero state, k 1,2,3,4,5.

The load value is set from register 141 in binary code, supplied to the corresponding inputs of the AND elements 159-168, and the device determines the current direction (Load for O, load day 1) automatically. Comparators 148 and 149 and reference sources 146 and 147 serve this purpose. If the voltage on the contact of the object 5.1 control is less than the level O, i.e. the output of the contact under study has a low potential, a logical unit is present at the output of the comparator 148, and a logical zero at the output of the comparator 149, and the current generators produce a flowing current of the corresponding magnitude. If the voltage on the contact of the 5.1 control is greater than level 1 (high potential), the output of the comparator 148 is a logical zero, and at the output of the comparator 149 is a logical unit, and the current generators

produce a flowing current. If the voltage on the contact of the control object 5.1 is between the levels

 O and G

then the outputs of both com Q 5 5

0

0

five

0

five

There are logical zeros in the parators, current generators do not produce, and logical inputs appear at the inputs of the N-157 element from the outputs of the HE elements 153 and 154, indicating a malfunction of the test object 5.1 of the control. The third input of the AND-NOT element 157 receives a Polling signal and, in the event of a match at the inputs of the element, the NE-157 is outputted through the AND element 155 to the output signal, which stops monitoring under load, and the signal from the output of the decoder 151 enters the display unit 10 for indication of a faulty output 5.1 object. If there is a discrepancy at the inputs of the NAND 157 element, the output signal is not generated and monitoring continues. With the arrival of the signal at the S-input of the trigger 140, the end of the array, the trigger 140 is set to one and opens the AND-143 element with its direct output. t through the IS-NE element 143 and is counted on the binary counter 145. When the codes $ recorded in the counters 144 and 145 coincide, on the comparison element 152, the single pulse shaper 156 selects the initial setting pulse of the triggers 139 and 140 and the counter 145. this element is II 143 is closed, terminating access to the signal recording O and counter Recording 1 NOT-AND gate 142 is opened, and the decoder 151 and de-energizes the relay is turned off at block 158 the switch. The relay contacts open and disconnect the contact of the control object 5.1 from the current generators. Signals Record O and Record 1 are fed to the input of counter 144, where they are added to the previously counted signals until the next arrival of the signal Record 1, after which the control process with a load is repeated for the next output contact of the object 5.1 control. If, after comparing the codes on the comparison element 148, a Polling signal is received before the signal arrives Record 1, then it passes through 29156462330

direct exit trigger 139 straight shoulder trigger 184 enters

covered

element AND-NOT 158 and enters the input element AND 155, the output of which indicates that the process control under load is completed.

Node 14.1 control (Fig. 11) works as follows. In the initial state, the triggers 184-187 and 189 are in the zero state. The elements 190 and I-HE 191 with an open collector are closed by the direct output of the trigger 185, and the second output of the control unit 14.1 is in the high-impedance state. When reading a test program from the buffer memory node 8, a switching test first takes place and there is a resolving potential at the inputs of the AND-NE elements 179 and 180, and an inhibitory potential at the inputs of the AND-NOT elements 181-183, which is also NOT the element 174 is fed to the inputs of the elements AND-NE 177 and 178. The inputs of the node 14.1 of the control receive the contact addresses of the object 5.1 of the control corresponding to the input and signals Record O, which through the open element IS-HE 179 are fed to the S input of the trigger 185 and translate it into one state by preparing the item An open collector and 190 and AND-NOT 199s receive information from trigger 184 through AND 192 and 193, OR-NOT 197, and HE 203, in addition, trigger 189 is prepared for operation. At the end of the commutation, the signal former 11 generates an enable signal only for AND-NE elements 177 and 178, another 15

20

to the input of the EXCLUSIVE OR element 196 for comparison with the information on the contact of the control object 5.1, which is fed to another input of the EXCLUSIVE OR element 196. If these levels do not match, if the contact of the 5.1 object of the control is input, that may occur ground or power, the signal of noncomparison arrives at the D-input of the trigger 189 and upon the arrival of the signal the Poll converts it to the single state and with its inverse output the trigger 189 blocks the element AND 190 and the element AND-HE 191 with an open collector, translating the output of node 14.1 to trolley bus in a high impedance state and prevents it from breaking down. In addition, the trigger 189 signals the malfunction of the object 5.1 control on the input and the flow of the control test program is stopped,

25, a trigger output signal is supplied to indicate a faulty contact to the corresponding input of the display unit 10. If incomparability occurred at the output contact, i.e. if a

30, the trigger 185 is in the zero state, the non-comparison signal through the IS-NE element 202 is output to the control node 14.1 to indicate the faulty output contact and also for

35 stop test program control. In case the control object's contact needs to be re-connected, i.e. change the ownership of the contact from the input to the output or other inputs of these elements are prepared up to P ° t at the input of the element NOT 17 and, respectively, the outputs of the elements NOT 175 and 176. Naturally, the inputs of the elements AND-NOT the inputs of the elements AND-NOT 177 and 178 179 and 180 are fed. Allowing addresses and signals are written. Record 0 and the potential. Depending on the incoming record 1, which by coincidence of the signal of the record, Record O or Record are transmitted to the S and R inputs of the trigger 184, 45, it is set to one or zero state, which is transmitted to the output of the control node 14.1, setting the input impact logic zero

111 at the inputs of the AND-NE elements 179 and 180 trigger 185 is set to

a single or zero state, opening or closing elements AND 190 and AND-NOT 191 with an open collector, or a logical unit to the input of the objects 50, if it is necessary to mask the output 5.1 of the control, provided that the contact of the object 5.1 of the control is input. Logical unit i.e. do not compare its output level with the reference information recorded in trigger 184, at the inputs of elec- tron resistors 195, 198 and 200, pn-trans-H755 cops NOT 175, AND-NOT 181 and 182, the resistor 201 and the setting point 199 of the reference with resolving potential. By matching. The logical zero to the formation at the inputs of the element AND-NE 181 is attached to the output of the element AND-NE 191 from the res and the signal Record O trigger open collector. The information from 186 is translated into a single state formed by a logic unit level generator 204 tuned to

five

0

to the input of the EXCLUSIVE OR element 196 for comparison with information on the contact of the control object 5.1, which is fed to another input of the EXCLUSIVE OR element 196. If these levels do not match, if the contact of the 5.1 object of the control is input, what can happen in the case of a closure ground or power, the signal of noncomparison arrives at the D-input of the trigger 189 and upon the arrival of the signal the Interrogation translates it into a single state and with its inverse output the trigger 189 blocks the element 190 and the element AND-191 with an open collector, translating the output of the node 14 .1 control in a high impedance state and protect it from failure. In addition, the trigger 189 signals the malfunction of the object 5.1 control on the input and the flow of the control test program is stopped,

5, a signal from the trigger output is supplied to indicate a faulty contact to the corresponding input of the display unit 10. If incomparability occurred at the output contact, i.e. if a

0, the trigger 185 is in the zero state, the non-comparison signal through the IS-NE element 202 is output to the control node 14.1 to indicate the faulty output contact and also for

5 stop test control program. In case the control object's contact needs to be re-connected, i.e. change the ownership of the contact from the input to the output or vice versa at the input of the element NOT 17 and, accordingly, the resolving potential is fed to the inputs of the elements AND-H 179 and 180. Depending on the signal received, Record O or Record

111 at the inputs of the AND-NE elements 179 and 180 trigger 185 is set to

The control and its inverse output overlaps the element IS-HE 202, prohibiting the generation of a signal of non-comparison at the output of the node 14.1 Control. If it is necessary to disguise the contact of the object 5.1 control, coincidence occurs at the inputs of the AND-HE element 182 and the trigger 186 is transferred to the zero state, opening the AND-HE element 202. If necessary, applying to the object contact 5.1 of the control for a pulse effect on the input of the HE elements 176 and AND-NO 183 an enable signal is given. Upon the arrival of the contact address of the object 5.1 of the control, to which the pulse action is to be applied, the trigger 187 is set to one and the output allows the pulse to pass through the AND-HE element 188 and then through the HE element 1J94, the elements Both 192 and 193, OR-NOT-97, HJE 203, AND 190 and AND-NOT 191 with an open collector to the object 5.l control, and depending on what was previously written to trigger 184, the output of the node 14.1 of the control, positive or negative pulses are formed. At the end of the impulse the mode, the R-input of the trigger 187 receives a signal that transfers the trigger 187 to the initial zero state, stopping the supply of pulsed actions to the object 5.1 of the control. The signals from the outputs of the HE elements 174-176 prohibit the recording of information in the trigger 184 in the switching, masking, and pulsed modes.

Claims (6)

1. Multichannel device of test control of pogic nodes, containing a memory block, a switching unit and ha control units, the first output of the 1st group of information outputs of the switching unit is connected to the Synchronization Input of the 1st control unit, where 1 Г, т 7 are other outputs ten the switching inputs of the switching unit, the equipotential input of which is connected to the first output of the information output group of the memory block, the information outputs of the memory block, except the first output, are connected to the (t + 1) -th group of information inputs of the switching unit, the control unit contains direct and accumulation node, synchronization node, indication node, n control nodes, address encoder, signal generator, the synchronization input of the receiving and accumulating node being input 15 of the synchronization of the control unit, the group of information inputs of which is connected to the group of information inputs of the receiving and accumulating node, the group in the strokes of the synchronization node is 20 groups of outputs of the number of the test program of the control unit, the inputs-output of the control units form the group of inputs and outputs of the control unit for connecting to the group of inputs and outputs 25 of the control object, the group of the first fault outputs of the control nodes is connected to the first group of decision inputs of the synchronization node, the first second and third outputs are connected to the first, second and third inputs of the control nodes operating mode, the group of gating inputs of the monitoring nodes is connected to the first group of the address decoder outputs, in order to expanding the functional capabilities of the device due to the control of typical logical nodes under load 40 coy, (m + 1) - the group of information outputs of the switching unit is connected to the group of address inputs of the m block, the group of information inputs of which is the group of information The 45 control inputs of the device, the output of which is connected to the output of the readiness of the memory block, the control block additionally containing, in the buffer memory, a pulse generator 30 35 The i-th group of information outputs of the block is 50 COB) load node, and the group connections are connected to the group of information inputs of the 1st control unit, the group of inputs-outputs of the 1st control unit is the 1st group of I / O devices for connection to the inputs-outputs of the 1st control object, the group of outputs of the test program number The 1st control unit is connected to 1-1 group of informational outputs of the receiving and accumulation unit connected to the group of formation inputs of the buffer unit of the node, the first synchronization input to 55 is connected to the output gate of the receiving and accumulating node, the fifth output of the synchronous node Cpd tion with an input authorization unit recording buoy Fern memory, a second input of synchronous the switching inputs of the switching unit, the control input of which is connected to the first output of the group of information outputs of the memory block, the information outputs of the memory block, except the first, are connected to the (t + 1) -th group of information inputs of the switching unit, the control unit containing the receiving node and accumulation, synchronization node, indication node p control nodes, address decoder, signal conditioner, and the synchronization input of the receiving and accumulating node is input 5 synchronization of the control unit, the group of information inputs of which is connected to the group of information inputs of the receiving and accumulating node, the group of outputs of the synchronization node is 0 group of outputs of the number of the test program of the control unit, the inputs-outputs of the control units form the group of inputs and outputs of the control unit for connection to the group of inputs and outputs 5 of the control object, the group of the first malfunction outputs of the control nodes is connected to the first group of resolution inputs of the synchronization node, the first, second and third outputs of the signal conditioner are connected respectively to the first, second and third inputs of the control nodes operation mode, the group of gate inputs of the control nodes is connected to the first A group of outputs of the address decoder, characterized in that, in order to expanding the functionality of the device due to monitoring of different types of logical nodes under load, (t + 1) - the group of information outputs of the switching unit is connected to the group of address inputs of the memory block, the group of information inputs of which is the group of information inputs of the device, the readiness output of which is connected with the output — the readiness of the memory unit, and the control unit additionally contains a buffer memory node, a pulse 0 generator five 0 OWL) node load, and group the information outputs of the receiving and accumulating node are connected to a group of information inputs of the buffer memory node, the first synchronization input of which is connected to the information output gate of the receiving and accumulating node, the first output of the synchronization node is connected to the write enable input of the buffer memory node, the second synchronization input of which combined with the synchronization input of the pulse generator and connected to the second output of the synchronization node, the first group of resolution inputs of which is connected to the first group of information inputs display unit, the second group of information inputs of which are connected to the second group of permission inputs of the synchronization node and the second outputs of the control nodes, the fourth and fifth inputs of the operation mode of which are connected respectively to the fourth and fifth outputs of the pulse former and the first and second settings of the mode the work of the load node, the group of information inputs-outputs of the control unit is connected to the group of load inputs of the load node, the group of fault outputs of which is connected to the third g The information inputs of the display node, the first control input of which is combined with the polling inputs of the monitoring of the control nodes, the load node, the synchronization node and connected to the sixth output of the pulse former, the seventh output of which is connected to the second control input of the display node and inputs completion of the control cycle of the load node and the synchronization node, the output of the control under the load of the load node is connected to the third control input of the display node and the input of the control completion under the load of the node with synchronization, the first group of outputs of the buffer memory node is connected to the first group of inputs of the address decoder, with the first group of inputs of the pulse generator operation mode and the group of inputs to specify load parameters of the load node, the second group of outputs of the buffer memory node is connected to the second group of inputs of the decoder addresses and the second group of inputs for setting the pulse driver operation mode, the third group of outputs of the buffer memory node is connected to the third group of inputs for setting the operation mode of pulse generator , the second output of the pulse generator is connected to the enable input of the pulse generator, the output of the operating mode of which is connected to the lock input of the synchronization node, the outputs of the clock pulses of the pulse generator are connected to the information inputs - Q 5 0 5 Q l 5 Q, five control nodes, the sixth inputs of the operation mode setting of which are combined and connected to the shutdown output of the pulse generator, the input group of the operation mode assignment of which is connected to the second output address decoder group. 2. The device according to claim 1, characterized in that the receiving and accumulating node contains a counting trigger, two AND-NOT elements and eleven D-flip-flops, with the information inputs from the first to the sixth D-flip-flops forming a group of information inputs of the node, the synchronization input of which connected to the first inputs of the NAND elements, the counting input of the counting trigger and is the output of the node information strobe; the outputs of the D-flip-flops from the first to the eleventh form a group of information outputs of the node; the direct and inverse outputs of the counting trigger are connected respectively Actually, with the second inputs of the first and second elements NAND, the synchronization inputs of the D-flip-flops from the first to the sixth are combined and connected to the output of the second NAND element, the output of the first AND-NAND element is connected to the synchronization inputs of the D-flip-flops from the seventh to the eleventh, The information inputs of the D-flip-flops from the seventh to the eleventh are respectively connected with the information inputs of the D-flip-flops from the first to the fifth. 3. The device according to claim 2, in which the signal conditioner contains a delay element, an encoder, a NOT element, five AND-NOT elements, three AND elements and three RS flip-flops, with the synchronization input of the imaging device connected to the input of the delay element whose output is connected with the first inputs of the NAND elements and the AND elements, the second inputs of the first to the fifth elements of the NAND are connected respectively to the outputs from the first to the fifth encoder, the first, second and third groups of inputs of the shaper operation mode are connected respectively to the first, second second and third groups of encoder inputs, the output element is coupled to the second input of the first AND gate, a first input of third AND input group specifying mode shaper connected to the input of NOT circuit and the second input of the second AND gate, the second the input of the third group of inputs for setting the operating mode of the driver is connected to the second input of the third element AND, the output of the first element IS NOT connected by the input t of the first RS trigger, the first inputs of the second and third RS trigger, the output of the second element IS NOT connected to the first input of the first element - to RS-flip-flop and the second inputs of the second and third RS-flip-flops, the output of the third element is NOT connected | the second input of the first RS-flip-flop, the input of the second RS-flip-flop, and the third input of the third RS-flip-flop, the output of the fourth element IS-NOT is connected to the input of the third RS-flip-flop and the third inputs of the first and second RS-flip-flops, the outputs of the first, second of the third RS flip-flop, the outputs of the first, second and third elements of foB AND and the output of the fifth element AND-NOT are the first, second, third, fourth, fifth, sixth and seventh outputs, respectively. 4. The device according to claim 1, This is what the sync node contains: two single pulse formers, a clock generator, a frequency divider, six Pj-HEj elements, three D-flip-flops, a HE element, two AND elements, a delay element, two Switches , two RS-flip-flops, groups of Switches, a group of RS-flip-flops, the first and second groups of node resolution are connected to the inputs of the first AND-NOT element, the output of which is Connected to the first input of the second AND-NOT element, the second input of which is combined with the input element is NOT and is connected to the polling input of the result of the control node The control termination input of which is connected to the inverse care of the third NAND element and the first input of the first RS flip-flop, the inverse output of which is connected to the first input of the first And element, the second input of which is connected to the first input of the fourth and fifth elements 1I-NOT and with the change-over contact of the first switch, the closing contacts of which are connected to the outputs of the frequency divider, the input of which is connected to the outputs of the clock generator, the output of the first driver single-c5 OR, nine elements NAND, four The first pulse is connected to the setup input into 1 of the first D-flip-flop, the direct and inverse outputs of which are connected respectively to the second VRS-flip-flop, D-flip-flop, three AND elements, AND-N element with an open collator, level generator logical unit, and the output of the first element 0 about 0 The fourth element IS-NOT and the second input of the first RS flip-flop, the direct output of the first RS flip-flop is the first output of the node, the second output of which is connected to the output of the first element AND, the third and fourth inputs of which are connected respectively to the inverse output of the second RS- the trigger and the direct output of the second D-flip-flop, the information inputs of the D-flip-flops, the switch contact of the second switch and the switch contacts of the group switches are connected to the width of the logical zero potential, the break contact of the second switch with It is connected to the input of the third NAND element, the output of which is connected via the delay element to the first input of the second element I, the output of the second generator of a single pulse is connected to the second input of the second element I, the output of which is connected to the R input of the first RS trigger, block 5 The operation of the node is connected to the second input of the fifth NAND element and S-BXO-House of the second RS flip-flop, the R-input of which is connected to the output of the fifth NAND element, the output of the element is NOT connected to the synchronization input of the third D-flip-flop, the inverse output of which is connected to the third input of the second NAND element, the output of which is connected to the first input of the sixth AND NAND element, the output of which is connected to the synchronization input of the second D-flip-flop, the second input of the sixth AND-NOT element is the input of the termination control under the node load, making contacts the group switches are connected to the R-inputs of the corresponding RS-flip-flops of the group, the S-inputs of the flip-flops of which are connected to the break contacts of the corresponding switches of the group, the output of the fourth AND-NE element is connected to the synchronization input of the first D-trig Hera, inverse outputs of the RS-TpnrrepoB group and the output of the fourth NAND element form a group of outputs of the node. 5.. The device according to claim 1, characterized in that the control node contains an element OR NOT, five elements are NOT, the element is EXCLUSIVE OR, nine elements AND NOT, four RS-flip-flop, D-flip-flop, three AND elements, NAND element with open collector, logical unit level generator, and the output of the first element that is NOT connected to the first inputs of the first and second elements AND-NOT, the second inputs of which are connected to the output of the second element NOT, the output of the third element is NOT connected to the third inputs of the first and second elements AND-NOT, the fourth inputs of the first and second elements AND-NOT and the first inputs from the third to the seventh elements of the NAND are not connected and connected to the gate input of the node; the first input of the operation mode setting of the node is connected to the input of the second element NOT and the second inputs of the fifth and sixth elements of the NAND, the second input of the operation mode of the node connection n with the input of the third element NOT and the second input of the seventh element NAND, the third input of the operation mode of the node is connected to the input of the first element NOT and the second inputs of the third and fourth elements of the NAND, the fourth input of the operation mode of the node is connected to the fifth input of the second and the third inputs of the third and fifth elements AND-NOT, the fifth input setting the operation mode of the node is connected to the fifth input of the first and third inputs of the fourth and sixth elements AND-NOT, the outputs of the first and second elements AND-NOT are connected respectively with S- and R-inputs first RS-flip-flop, the inverse output of which is connected to the first input of the first element AND, the second input of which is combined with the input of the fourth element NOT and connected to the output of the eighth element AND-NOT, the first input of which is the information input of the node, the outputs of the third and fourth elements AND -NOT connected respectively to the S- and R-inputs of the second RS-flip-flop, the output of which is connected to the first input of the NAND element with an open collector, the first input of the second And element and to the input of the O-D flip-flop setting, the synchronization input of which is the polling input of the control result of the node, the first fault output of which is connected to the output of the ninth NAND element, the first input of which is combined with the information input of the D-flip-flop and connected to the output of the EXCLUSIVE OR element, the first input connected to the first input of the third And element and By the output of the first D-flip-flop, the outputs of the fifth and sixth elements of the NAND are connected respectively to. S and R inputs ten 20 25 f5 30 35 40 0 five the second RS flip-flop, the inverse output of which is connected to the second input of the ninth NAND element, the output of the seventh NAND element and the sixth input of the node operation mode are connected respectively to the S and R inputs of the fourth RS flip-flop, the output of which is connected to the second input of the eighth AND-NOT element, the outputs of the first and third elements AND are connected respectively to the first and second inputs of the OR-NOT element, the output of which is connected to the second input of the second element AND and the input of the fifth element NOT, the output of which is connected to the second input of the AND element - NOT with from the red collector, the output of which is connected to the second input of the EXCLUSIVE OR element, to the output of the logic unit level generator and is the input-output of the node, the second output of the faults which is connected to the third inputs of the second AND element, the NAND element with the open collector and the inverse output D -trigger, the output of the second element And is connected to the control input of the level generator of the logical unit, the output of the fourth element is NOT connected to the second input of the third element I. 6. The device according to claim 1, characterized in that the load node contains a switch, seven elements AND-KE, D-flip-flop, RS-flip-flop, register, two counters, the source of the reference level of logic zero, the source of the reference level of the logical unit, two comparators , decoder, reference element, two NOT elements, eleven AND elements, single pulse shaper, switching element, five current generators, with outputs from the first to fifth And elements connected to the first inputs of the mode setting, respectively, from the first to fifth generators First, the second inputs of the current mode generator from the first to the fifth generators are connected to the outputs of the And elements, respectively from the sixth to the tenth one, the outputs of the current generators are combined and connected to the information input of the switching element and to the first inputs of the first and second comparators, the second inputs of the first and second the comparators are connected respectively to the source outputs of the element of the logic zero level and the source of the reference level of the logical unit, the output of the first comparator is connected to the first inputs of the And elements from the first to n and with the input of the first element NOT, the output of which is connected to the first input of the first element NAND, the output of the second Comparator is connected to the first inputs of the elements AND from the sixth to the tenth and with the input of the second element NOT, and its OD with the second input of the first NAND element, the group of inputs for setting the node load parameters is connected to the group of information inputs of the register, the first output of which is connected to the second inputs of the first ii sixth And elements, the second output of the register is connected to the second inputs of the second and seventh elements And, the third register output is connected to the second: the third and eighth i elements, the fourth register output is connected: the second inputs of the fourth and ninth PI elements, the fifth register output is connected to the second inputs of the fifth: tenth AND elements, the sync input register is connected to the inverse output of the D-flip-flop, the direct output of which is connected to the first inputs of the third and third elements AND-NOT p to the gate input of the decoder, the Group of information inputs of which is connected to the first group of inputs of the comparison element and to the group the bit outputs of the first counter, the counting input of which is connected to the output of the second NAND element, the second input of which is combined with the first input of the fourth AND NAND element and connected to the output of the fifth AND AND element, the first input of which is connected to the output of the sixth AND element -NO, the first inputs of the sixth and seventh elements AND-NOT ow - five 0 The first and second inputs of the node operation mode, respectively, the second inputs of the sixth and seventh elements AND –NAY are combined and connected to the switching contact, the switching contact of which is integrated with the information input of the D-flip-flop and connected to the potential potential logical bus zero, the output of the seventh element And -NOT connected to the second input of the fifth NAND element and the synchronization input of the D-flip-flop, installation input in 1 which is combined with the R-input of the RS-flip-flop, with the zeroing input, the second counter and connected to the output of the single pulse former, the input of which is connected to the output of the reference element, the second group of inputs of which is connected to the group of the bit outputs of the second counter, the counting input of which connected to the output of the fourth NAND element, the second input of which is connected to the output of the RS flip-flop, the S input of which is the input of the end of the monitoring cycle of the node, the polling input of which is connected to the third input of the first element AND-NOT and the second input of the third AND-NOT element, the output of which is connected to the first input of the eleventh AND element, the output of which is the output of the termination control under the load of the node, the output of the first AND-NE element is connected to the second input of the eleventh AND element, group of outputs The decoder is connected to a group of control inputs of the switching element and is a group of outputs of the malfunction of the node whose load input group is connected to the group of information inputs of the switching element. 43 1564623 44 Continued table. i To control object 5A of FIG. 2 Oh HONEY Pavly Pavly Synervmopa9 C form-, fl / fl iU Crazy b Haf / ukZ  From node 7 Former 11 g one. | Si r eleven with   . " .. t § four four I i S5 sz. With decoder 12 Susch Јffj№ 8 CpopMupofn-mem H From the node On 1 / green 7 Ma nodes /4.1 Shdze № On nodes Ш Fiz.9 On the bond / 110 euz / ioitil la Zoo On OK 5 Node 7 Figi