SU663058A1 - Stepping motor control device - Google Patents

Description

The invention relates to the field of automation and is intended for use in automatic control and regulation systems with stepper motors.

Stepper motor control devices are known that contain power amplifiers and a pulse distributor, forming a stepper motor winding switch, a number register connected to the counter inputs, an input key, matching blocks, and a generator 1. However, these devices cannot be used in redundant control systems, as they are insufficiently reliable and have low noise immunity due to non-confirmation of the initial data before processing information, which leads to the accumulation of failures and loss of operation nosti. Such devices cannot also be used in remote control systems, as in this case they lose their working capacity due to time variations in the communication lines. In addition, devices have a large number of connections, determined by the width of the input code.

The closest to the invention to the technical entity is a device for controlling a stepper motor, comprising a multi-channel power amplifier, each channel of which is connected to the output of a control signal conversion unit consisting of an input key, a master oscillator, a number input register, an input key of a frequency divider, counter, switching trigger with counting

the input, input and output keys of the write driver, inverter, trigger signal reset, decoder, input counter with input key, transformer galvanic isolators, zero code indicator and pulse distributor 2.

A disadvantage of this device is its inability to use it in redundant control systems, c. particular three-channel. In this case, the control channels (pulse distributors) accumulate failures that occur in the channel itself or in the system - the input information sensor, which leads to improper processing of steps by the stepping motor. A similar phenomenon occurs when the channels of the input information device are different from each other for each of the channels. Then in the next cycle of work, the impulse processing is wrong. To reset the output triggers of the pulse distributor by the signal "Reset impossible, because the number of combinations of states at the outputs of the distributors is equal to the number of control phases of the stepping motor (2). Thus, any initial installation of the winding switches without analyzing the state of the research institutes of adjacent channels also leads to incorrect working off of the steps in the operation cycle of the device. In addition, in the distributors of pulses, a failure can occur in a static mode prior to the start of testing, since the “Reset is confirmed only. -“ condition ”is“ forward running, and all other elements are not standing under the signal “Cj5poc. information stepper motor, reduces the reliability, noise immunity and accuracy of conversion and reduces the functionality of the known device. -. The aim of the invention is to improve the reliability, noise immunity and accuracy of information conversion and to expand the functionality of the device for controlling the engine. This is achieved. The fact that a polling trigger with separating inputs is introduced into each of the control channels of the device, which serves to generate a polling signal of the pulse distributor memory elements, AND-NOT synchronization cells, designed to analyze the output states of the adjacent channel pulse distributors and to correct a degraded channel, the inhibit cell to disable the IS-NOT cells when synchronizing the input information, and the inverters necessary to trigger the corresponding AND-NOT cells Synchronize u at zero levels at the outputs of the distributors of impulses of adjacent channels; the inverter outputs are connected respectively to the first and second inputs of the odd AND-NOT synchronization cells, and the inputs are connected to the first and second inputs of the adjacent even AND-NOT synchronization cells, while the third inputs of all AND-NOT cells, synchronization are combined and connected to the output a prohibition cell, the prohibiting input of which through the corresponding bus is connected to the output of the input key of the control signal conversion unit, and the second input, to the single output of the Poll trigger with the separate inputs, single and. the zero inputs of which are respectively connected to the single output of the trigger signal of the Reset and the output of the output key of the recorder of the control signal conversion unit, and the outputs of the AND-NO synchronization are connected to the inputs of the pulse distributor's memory elements through corresponding slots. the control signal, and the outputs of the pulse distributors of the control signal conversion unit of each control channel are pairwise connected to the first and second inputs of the corresponding even-numbered cells of the adjacent channels AND IS NOT and the corresponding power amplifiers. Thus, the introduction of synchronization and IS-NE cells and inverters allows for the initial installation of the pulse distributor memory elements to the final state, which they must occupy after working out any bundle of input code, both in the positions corresponding to the excited motor windings, so and in positions corresponding to their de-energized condition. This allows you to add a device to control the engine using the power amplifier of a moratorial element as a power source, completely eliminates the consequences of failures in the control channels, ensures the normal operation of the device when working on various numerical values of the input information and prevents the accumulation of failures in the device . In addition, such an embodiment of the device extends its functional capabilities, allows its use in reliable redundant three-channel structures and increases reliability. In FIG. 1 shows a functional diagram of the described device; in fig. 2 is a functional diagram of a control signal conversion unit; in fig. 3 shows time diagrams of the device operation; The device (see Fig. 1) contains a scap motor 1, power amplifiers 2, control channels 3-5 and in each channel a control signal conversion unit 6, a fpnrrep 7 interrogation signal with separate inputs, the output of which is connected with the first input of the prohibition cell 8, connected by its output to the third inputs of the sync I-NE 9-12 cells The first and second inputs of the odd I-NE 9 and II synchronization cells are connected respectively to the outputs of the inverters 13, 14, and 15, 16. The control signal conversion unit 6 contains buses "Address 17," Output information 18, "Sync pulse input 19 , "Reset 20," Record 21, "Output of unitary code 22," Inputs of pulse distributor 23. In addition, the input key 24, master oscillator 25, register 26 input numbers, frequency divider 27 with output key 28, counter 29, switching trigger 30 with counting m input meters, information input keys 31-34, input 35 and output 36 keys of the write driver, counting triggers 37 and 39 of the write driver, inverter 39, reset trigger 40 of the signal “reset, decoder 41, input counter 42 with key 43, transformer galvanic 44-46 connectors connected by their inputs to the bus "Address 17," Input information 18 and "Sync pulse input 19, and zero code indicator 47, which contains the input cell OR 48, key 49, trigger 50 with isolation inputs and output key 51 Single output trigger 40 signal "Reset connected to the bus "Reset 20, output of output key 36 of write driver to bus" Record 21, output of input key 24 to bus "Output of unitary code 22, and inputs of memory elements of distributor 52 pulses are connected to buses" Inputs of pulse distributor 23. The device operates as follows in a way. Input signals in each of the channels. Controls arrive at transformer galvanic isolations 44-46 in the sequence indicated in FIG. 3. The signal received via the bus, “Address 17 via galvanic isolation 46 sets the final trigger of the input counter 42 to the state“ 1, as a result, a signal is received at the input of the key 43 that permits the passage of pulses from the bus “Sync pulse input 19 through galvanic spread The key 45 and the key 43 to the input of the input counter 42. In this device, a paraphase code is used to transmit digital information over long distances, or the number is represented in a dynamic way, which ensures a high noise immunity of the device. Thus, after the signal passes through the bus, the Address 17 clock signals accompanying the input information arrive at the input counter 42, and the information itself along with the clock pulses go to the number input register 26. After the arrival of a certain number of clock pulses, the decoder 4 generates a “Reset” signal, which sets “1 flip-flop 40” of the “Reset. Then, after some time determined by the structure of the decoder 41 and the number of pulses of the input information, the trigger 40 of the signal "Reset is set to" O, i.e. the circuit elements are reset to their original state according to the links shown in FIG. 2. The leading edge of the pulses of the signal "Reset on the bus" Reset 20 channels 3-5 of the control sets "1 triggers 7 polls of all control channels and, since the control pulses at the inputs of the distributors 52 pulses, and hence on the bus “The output of unitary code 22 is absent, i.e. the prohibition signal on the prohibiting inputs of the prohibition 8 cells of all control channels is absent, then the unit-level signal from the outputs of the polling triggers, passing through the cell 8, opens the synchronization cells 9-12 of each of the control channels 3-5 through the connections shown in FIG. 1, Depending on the state of the outputs of the pulse distributors 52, at the outputs of the synchronization cells 9-12, the signals of the installation of the elements of the pulse distributors appear so that if the levels at the inputs of the cells 9-12 coincide, the signals are generated or are absent if the specified levels. For example, if the corresponding output to the first winding (Output 1) of the distributors 52 of the impulses of the control channels 4 and 5 control signal is high, and the corresponding output of the control distributor pulse control channel 3 - a low signal (motor winding is de-energized), then the high signal The level, passage through the synchronization cell 12, set a high level on the memory elements of the control channel 3 pulse distributor corresponding to this motor winding. The synchronization cell 11 in this case is closed by low levels coming from the outputs of the inverters 15 and 16. After setting the high level to Exit. 1 of the pulse distributor 52 in the control channel 3 at the outputs of the respective synchronization cells 12 of the control channels 4 and 5 also produces setting signals confirming a high level at the corresponding first winding memory element of the pulse distributor of the control channel 3. Thus, the state of the pulse distributors is corrected. Before correction of the distributor 52, the pulses of channel 3 of the control, the synchronization cells of channels 4 and 5 of the control are closed by a low level coming from the output of the distributor of pulses (Output 1) of channel 3, and are opened after correcting the outputs of channel 3 of control. The device works accordingly in the case when the outputs of the distributors 52 of the pulses of the control channels 4 and 5 contain a low level signal, and the output of the pulse distributor of the control channel 3 is a high level signal. In this case, the low level signals, having passed through the inverters 15 and 16, open the synchronization cell 11 and set the low level on the corresponding first winding memory elements of the distributor 52 of the control channel 3 pulses. Synchronization cell 12 is closed at low levels. Next, confirmation of the low levels of the pulse distributors 52 of the control channels 4 and 5 occurs. With other combinations of conditions. The inputs of the pulse distributors of the channels 3-5 of the control of the correction of the elements of the TGTM are carried out in a similar way, including through other outputs (Out. T). After the last pulse of the sequential input code has been received, the entire digital information is recorded in the number input register 26, and the last sync pulse accompanying the input code overflows the input counter 42, from the pulse output of which the overflow signal arrives at the installation input of the last counting trigger 38 of the write driver, sets it to state "1 and closing key 43. In this case, the passage of pulses from the master oscillator 25 through the input key 35 to the counting one is allowed, the input of the first account th trigger shaper 37 entries. After the overflow of the counting triggers 37 and 38 of the write drivers, the circuit elements of the device and the bus Record 21 receive a signal Record. In this case, information from register 26 is rewritten via keys 3134 to counter 29, and polling triggers 7 are set to the state "O, removing from the memory elements of the pulse distributors 52 the signals of the initial setting. At the same time, in the case of the availability of information other than zero, the state of the "1 switching trigger 30" is set, allowing the passage of pulses to the input of the counter 29 and the input of the frequency divider 27. The delay time of the "Record select" signal is such that it guarantees the rewriting of information from register 26 after the end of all transients on the elements of the device circuit arising after entering input information from the bus "Input information 18. Depending on what sign the input information came to the distributor 52, forward travel conditions, confirmed by the signal "Reset from trigger 40 of signal Reset, remain or, if there is a single level, reversal conditions are recorded in the sign bits. Next, the frequency from the master oscillator 25 passes through the switch 28, is fed to the input of the frequency divider 27, at which the signal from the output of the trigger 40 of the signal "Reset had 1 recorded initial conditions that ensure the appearance of pulses at the output of the frequency divider with a delay of these initial conditions , which guarantees the scheme from false positives due to chipping and increases the speed of the device. Control pulses are passed to counter 29, bus "Output of a unitary code 22 and dispenser 52 pulses until the time that the hook 29 counter overflows. Simultaneously pulses

control for the whole time of their action gives a prohibitory signal on the prohibition of the inputs of the ban 8 cells of all channels that

663058

Claims (2)

reliability, noise immunity and accuracy of information conversion and enhancement of functionality, increases the immunity of the circuit and its reliability when the system triggers polling. After the counter 29 is full, the switching trigger 30 is set to the "O" state and closes the keys 24 and 28 ... After the end of the specified cycle, the circuit is ready for processing the next sending of input information. As follows from FIG. 2, the processing of information is possible in the case when the register 26 contains a binary code other than zero. Then, the input cell OR 48 of the zero-code indicator 47 produces at its output a high level signal, which permits the passage of the signal to Record to the trigger 50, setting it to the state "1. In case of receipt of zero information via the bus, Input information 18 trigger 50 remains in the state "O", i.e. in the state in which its trigger signal set the control signal through the output switch 51 and does not pass. Thus, the proposed device in comparison with the prototype allows, in order of time, to increase the reliability of the circuit, to increase its noise immunity by an amount determined by the ratio, where tfcx is the time to prepare the circuit for operation; t ay is the time of exposure to the initial conditions; as well as extend the functionality and improve the accuracy of the input signal conversion. This ratio depends on the frequency of the input information signals, the speed of the applied elements and other factors. In the general case, this ratio can reach a significant value, by an order of magnitude and more increasing the immunity of the proposed device. As compared with the known scheme. The invention is a device for controlling a stepper motor, comprising a multi-channel power amplifier, each channel of which is connected to the output of a control signal conversion unit consisting of an input key, a master oscillator, a number input register, an input key of a frequency divider, a frequency divider, a counter, a switching trigger with a counting input, input and output keys of the write driver, inverter: trigger signal "Reset, decoder, input counter with input key, transformer galvanic Zero code indicator and pulse distributor, characterized in that, in order to increase each of the control channels, a polling trigger with separate inputs of the inhibit cell, AND-NO synchronization cells and inverters are entered, the outputs of which are connected respectively to the first and second inputs of odd cells synchronization, and inputs - with the first and second inputs of neighboring even-numbered cells AND IS NOT synchronization, while the third inputs of all AND-NOT synchronization cells are combined and connected to the output of the prohibition cell, which prohibits the input The second input is connected to the output key of the control signal conversion unit, and the second input is connected to the single output of the polling trigger, the single and zero inputs of which are respectively connected to the single output 663058 10 signal triggers Reset to the output of the output key of the recording unit of the control signal conversion unit, with the outputs of the AND-NOT synchronization cells connected to the inputs of the pulse distributor connected by the output of each channel to the first and second inputs of the corresponding even-nes of the AND-NOT synchronization of adjacent channels. Sources of information taken into account. During the examination 1. Discrete electric drive with stepper motors, under total. ed. M. G. Chilikina. M., “Energie, 1971, p. 559. 2. Author's testimony of the USSR № 514441, cl. H 02 R 7/62, 1975. „Ld / ks “Bx. inf. ,VC. sync, K „CSpac P : l. ppppppppp.